JPH05243319A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05243319A
JPH05243319A JP4044384A JP4438492A JPH05243319A JP H05243319 A JPH05243319 A JP H05243319A JP 4044384 A JP4044384 A JP 4044384A JP 4438492 A JP4438492 A JP 4438492A JP H05243319 A JPH05243319 A JP H05243319A
Authority
JP
Japan
Prior art keywords
layer
bump
semiconductor element
pad
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4044384A
Other languages
Japanese (ja)
Inventor
Hiroyuki Tsutsumi
浩幸 堤
Haruo Shimamoto
晴夫 島本
Yasuhiro Teraoka
康宏 寺岡
Hiroshi Tobimatsu
博 飛松
Toru Tachikawa
透 立川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4044384A priority Critical patent/JPH05243319A/en
Publication of JPH05243319A publication Critical patent/JPH05243319A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To realize a reliable junction with a flat surface of a bump, by forming an interlayer film smaller than an interlayer opening and located at each opening part of interconnecting patterns in a semiconductor device. CONSTITUTION:A contact region, through which first-layer Al wiring pad 2a, a second-layer Al wiring pad 2b, and a third-layer Al wiring pad 2c are electrically connected, is formed around a bonding pad while first and second interlayer films 3a and 3b are formed at a central part of the bonding pad. Since these two interlayer films 3a and 3b raise the height of a central surface of a bump 4 by their thicknesses, unevenness in the surface of the bump 4 is reduced. Consequently, the bump 4 is adequately put in contact with an inner lead 7a, and thereby thermal energy of a laser beam is effectively transmitted from the inner lead part 7a to the bump 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、半導体素子に関し、
特にボンディングパッドの改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
Particularly, it relates to improvement of the bonding pad.

【０００２】[0002]

【従来の技術】図５は、半導体素子上に形成された従来
のボンディングパッドを示す断面図である。図におい
て、１は半導体素子、２ａは半導体素子１の表面上に形
成された第１層Ａｌ配線パッド、３ａは半導体素子１と
第１Ａｌ配線パッド２ａの周縁部を覆って形成された第
１層間膜、２ｂは第１層Ａｌ配線パッド２ａ及び第１層
層間膜３ａの開口周縁部を覆って形成された第２層Ａｌ
配線パッド、３ｂは第２層Ａｌ配線パッド２ｂの周縁部
及び第１層層間膜３ａを覆って形成された第２層層間
膜、２ｃは第２層Ａｌ配線パッド２ｂ及び第２層層間膜
３ｂの開口周縁部を覆って形成された第３層Ａｌ配線パ
ッド、３ｃは第３層Ａｌ配線パッド２ｃの周縁部及び第
２層層間膜３ｂを覆って形成された表面保護のパッシベ
ーション膜である。また、４は第３層Ａｌ配線パッド２
ｃ及びパッシベーション膜３ｃの開口周縁部を覆って形
成される。例えば、Ａｕなどのよるバンプと呼ばれる突
起電極（以下バンプと呼ぶ。）である。2. Description of the Related Art FIG. 5 is a sectional view showing a conventional bonding pad formed on a semiconductor device. In the figure, 1 is a semiconductor element, 2a is a first layer Al wiring pad formed on the surface of the semiconductor element 1, and 3a is a first interlayer formed to cover the peripheral portions of the semiconductor element 1 and the first Al wiring pad 2a. The films 2b are the second-layer Al formed to cover the opening edge portions of the first-layer Al wiring pad 2a and the first-layer interlayer film 3a.
Wiring pads 3b are second layer interlayer films formed so as to cover the peripheral portions of the second layer Al wiring pads 2b and the first layer interlayer film 3a, and 2c are second layer Al wiring pads 2b and the second layer interlayer film 3b. The third-layer Al wiring pad 3c formed to cover the peripheral edge of the opening is a passivation film for surface protection formed to cover the peripheral edge of the third-layer Al wiring pad 2c and the second-layer interlayer film 3b. Further, 4 is the third layer Al wiring pad 2
c and the passivation film 3c are formed so as to cover the peripheral edge portion of the opening. For example, it is a protruding electrode called a bump made of Au or the like (hereinafter referred to as a bump).

【０００３】図５において、第１層層間膜３ａ、第２層
層間膜３ｂ、パッシベーション膜３ｃは、それぞれ、第
１層Ａｌ配線パッド２ａ、第２層Ａｌ配線パッド２ｂ、
第３層Ａｌ配線パッド２ｃの周縁部までを覆っており、
その内側には、各々開口部５ａ、５ｂ、５ｃが形成され
ている。これら第１層、第２層層間膜３ａ、３ｂの開口
部５ａ、５ｂの寸法と、パッシベーション膜３ｃの開口
部５ｃの寸法との間には特に規定がない。また、各層の
Ａｌ配線パッド及び層間膜、パッシベーション膜は均一
な厚さで形成されている。従って、層間膜３ａ、３ｂや
パッシベーション膜３ｃの段差ｔのために図示のように
パッドの周縁部に凹凸が生じ、バンプ４の表面には凹凸
がそのまま反映された突起部４ａが形成されてしまう。In FIG. 5, a first-layer interlayer film 3a, a second-layer interlayer film 3b, and a passivation film 3c are a first-layer Al wiring pad 2a, a second-layer Al wiring pad 2b, and a second-layer Al wiring pad 2b, respectively.
It covers up to the peripheral edge of the third-layer Al wiring pad 2c,
Openings 5a, 5b, 5c are formed inside thereof. There is no particular regulation between the dimensions of the openings 5a and 5b of the first and second interlayer films 3a and 3b and the dimensions of the opening 5c of the passivation film 3c. Further, the Al wiring pad, the interlayer film, and the passivation film of each layer are formed with a uniform thickness. Therefore, due to the step difference t of the interlayer films 3a and 3b and the passivation film 3c, unevenness is generated in the peripheral portion of the pad as shown in the drawing, and the bumps 4a are formed on the surface of the bump 4 with the unevenness as it is. ..

【０００４】次に実装動作について説明する。図６は半
導体素子１を実装する状態を示す展開斜視図、図７は実
装時のバンプ４の接合部の拡大断面図、図８は半導体素
子の実装時の断面図である。図６において、１は半導体
素子、４はバンプ、６はテープ基材、６ａは半導体素子
１を実装するためのセンターデバイス孔、６ｂはアウタ
ーリード孔、６ｃはテープ基材６の長尺方向にテープを
送り出したり、あるいは位置決めするためのスプロケッ
トホール、６ｄはテープ基材６のリードサポート部、７
はテープ基材６上に形成されたリードで、センターデバ
イス孔６ａに突き出した部分を、インナーリード部７
ａ、アウターリード孔６ｂ上の部分をアウターリード部
７ｂと呼ぶ。半導体素子１をテープ基材６に実装するた
めには、バンプ４とインナーリード部７ａを位置合わせ
して載置し、ボンディングツール（図示せず）によって
加熱、圧着することによって接合させたり、あるいは、
レーザー光をインナーリード部７ａに照射して、その熱
エネルギーでバンプ４とインナーリード部７ａを接合す
る。図７において、符号１〜７ａは図６のものと同一で
ある。８はボディングツールである。図示のように、バ
ンプ４とインナーリード部７ａを位置合わせした状態
で、ボンディングツール８を下降させ、熱圧着により接
合させている。図８において、符号１〜７ａは図７のも
のと同一であり、９は例えばガラス板などによる押さえ
治具、図示の矢印はレーザー光である。図示のように、
バンプ４とインナーリード部７ａを位置合わせした状態
で接触させ、レーザー光を照射し、その熱エネルギーで
バンプ４とインナーリード部７ａを接合させる。Next, the mounting operation will be described. FIG. 6 is a developed perspective view showing a state in which the semiconductor element 1 is mounted, FIG. 7 is an enlarged sectional view of a bonding portion of the bump 4 at the time of mounting, and FIG. 8 is a sectional view at the time of mounting the semiconductor element. In FIG. 6, 1 is a semiconductor element, 4 is a bump, 6 is a tape base material, 6a is a center device hole for mounting the semiconductor element 1, 6b is an outer lead hole, and 6c is a longitudinal direction of the tape base material 6. A sprocket hole for feeding or positioning the tape, 6d is a lead support portion of the tape substrate 6, 7
Is a lead formed on the tape base material 6, and the portion protruding into the center device hole 6a is connected to the inner lead portion 7
a, the portion above the outer lead hole 6b is referred to as an outer lead portion 7b. In order to mount the semiconductor element 1 on the tape base material 6, the bumps 4 and the inner lead portions 7a are aligned and placed, and they are bonded by heating and pressure bonding with a bonding tool (not shown), or ,
The inner lead portion 7a is irradiated with laser light, and the thermal energy of the laser light joins the bump 4 and the inner lead portion 7a. 7, reference numerals 1 to 7a are the same as those in FIG. 8 is a boding tool. As shown in the figure, the bonding tool 8 is lowered in a state where the bump 4 and the inner lead portion 7a are aligned with each other, and they are bonded by thermocompression bonding. In FIG. 8, reference numerals 1 to 7a are the same as those in FIG. 7, 9 is a pressing jig made of, for example, a glass plate, and the arrow shown is a laser beam. As shown,
The bumps 4 and the inner lead portions 7a are brought into contact with each other in a aligned state, laser light is irradiated, and the bumps 4 and the inner lead portions 7a are bonded by the thermal energy.

【０００５】[0005]

【発明が解決しようとする課題】従来の半導体素子のボ
ンディングパッドは以上のように構成されているので、
バンプ４の表面に凹凸が生じやすいので、バンプ４とイ
ンナーリード部７ａとの良好な接合を得ることが困難で
あるという問題点があった。Since the conventional bonding pad of the semiconductor element is constructed as described above,
Since the bumps 4 are likely to have irregularities on the surface, it is difficult to obtain good bonding between the bumps 4 and the inner lead portions 7a.

【０００６】この発明は上記のような問題点を解消する
ためになされたもので、バンプ表面の平坦化を図り信頼
性の高い接合ができる半導体素子のボンディングパッド
を得ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a bonding pad for a semiconductor element, which is capable of flattening the bump surface and achieving highly reliable bonding.

【０００７】[0007]

【課題を解決するための手段】この発明に係わる第１の
発明の半導体素子のボンディングパッドは、配線パター
ンの各々の層間膜開口部内に、開口部の寸法よりも小さ
い寸法の層間膜を形成したものである。In the bonding pad of the semiconductor element according to the first aspect of the present invention, an interlayer film having a size smaller than the size of the opening is formed in each interlayer film opening of the wiring pattern. It is a thing.

【０００８】この発明に係わる第２の発明の半導体素子
のボンディングパッドは、配線パターンの各々の層間膜
開口部の寸法を小さくし、開口部をボンディングパッド
の中央に設けたものである。The bonding pad of the semiconductor element of the second invention according to the present invention is one in which the dimension of each interlayer film opening of the wiring pattern is reduced and the opening is provided at the center of the bonding pad.

【０００９】この発明に係わる第３の発明の半導体素子
のボンディングパッドは、配線パターンの各々の層間膜
開口部の寸法を小さくし、開口部の形成位置を水平方向
に互いにずらしたものである。In the bonding pad of the semiconductor element of the third invention according to the present invention, the dimension of each interlayer film opening of the wiring pattern is made small, and the formation positions of the openings are horizontally shifted from each other.

【００１０】[0010]

【作用】この発明による半導体素子のボンディングパッ
ドは、層間膜の段差の影響が小さくなる。In the bonding pad of the semiconductor device according to the present invention, the influence of the step of the interlayer film is reduced.

【００１１】[0011]

【実施例】実施例１．以下、この発明の実施例１を図に
ついて説明する。図１はこの発明の実施例１によるボン
ディングパッドを示す３層Ａｌ配線パターンの断面図で
ある。なお、図１において、第１層層間膜３ａ、第２層
層間膜３ｂの開口部５ａ、５ｂには、開口部５ａ、５ｂ
の寸法より小さい層間膜３ａ、３ｂが各々形成されてい
る。すなわち、第１層Ａｌ配線パッド２ａ、第２層Ａｌ
配線パッド２ｂ、第３層Ａｌ配線パッド２ｃを電気的に
導通させるためのコンタクト領域をボンディングパッド
の周縁部に形成しながら、ボンディングパッド中央部に
は、第１、第２の層間膜３ａ、３ｂが形成されるので、
ボンディングパッド中央部に新たに形成された２つの層
間膜３ａ、３ｂの厚さ分だけ、バンプ４の中央部の表面
が高くなり、バンプ４の表面の凹凸が小さくなる。EXAMPLES Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a sectional view of a three-layer Al wiring pattern showing a bonding pad according to a first embodiment of the present invention. In FIG. 1, the openings 5a and 5b are formed in the openings 5a and 5b of the first-layer interlayer film 3a and the second-layer interlayer film 3b.
Interlayer films 3a and 3b each having a size smaller than the above are formed. That is, the first layer Al wiring pad 2a, the second layer Al
A contact region for electrically connecting the wiring pad 2b and the third-layer Al wiring pad 2c is formed in the peripheral portion of the bonding pad, and the first and second interlayer films 3a and 3b are formed in the central portion of the bonding pad. Is formed,
The surface of the central portion of the bump 4 becomes higher and the unevenness of the surface of the bump 4 becomes smaller by the thickness of the two interlayer films 3a and 3b newly formed at the central portion of the bonding pad.

【００１２】次に実装動作について説明する。図２は第
１の実施例によって形成されたボンディングパッドを有
する半導体素子の実装時の接合部の拡大断面図である。
図２において、バンプ４の表面の凹凸は小さくなってい
るので、インナーリード部７ａとの接触が良くなり、レ
ーザ光の熱エネルギーが効率よくインナーリード部７ａ
からバンプ４へと伝わり、インナーリード７ａとバンプ
４との良質な接合が行われる。Next, the mounting operation will be described. FIG. 2 is an enlarged cross-sectional view of a joint portion at the time of mounting a semiconductor element having a bonding pad formed according to the first embodiment.
In FIG. 2, since the bumps 4 have small irregularities on the surface, the contact with the inner lead portion 7a is improved, and the thermal energy of the laser light is efficiently supplied to the inner lead portion 7a.
Is transmitted to the bumps 4, and the inner leads 7a and the bumps 4 are joined together in good quality.

【００１３】実施例２．図３はこの発明の実施例２によ
る半導体素子のボンディングパッドを示す断面図であ
る。図３のものは、第１層層間膜３ａ、第２層層間膜３
ｂの開口部５ａ、５ｂの寸法を十分に小さくしてボンデ
ィングパッド中央部に形成されている。すなわち、開口
５ａ、５ｂの寸法は、層間膜３ａ、３ｂの段差ｔが、バ
ンプ４の表面にほとんど反映されない程度に十分小さ
く、かつ、ボンディングパッドの中央部に形成されてい
るので、周縁部のパッシベーション膜開口部５ｃによる
段差ｔともつながらないので、バンプ４の表面は全体と
して平坦なものとなる。従って、インナーリード部７ａ
とバンプ４との接触が良好なものとなり、良質な接合が
得られる。Embodiment 2. 3 is a sectional view showing a bonding pad of a semiconductor device according to a second embodiment of the present invention. In FIG. 3, the first layer interlayer film 3a and the second layer interlayer film 3 are shown.
The opening portions 5a and 5b of b are formed in a central portion of the bonding pad with a sufficiently small size. That is, the dimensions of the openings 5a and 5b are sufficiently small that the step t of the interlayer films 3a and 3b is hardly reflected on the surface of the bump 4 and are formed in the central portion of the bonding pad. Since there is no step t due to the passivation film opening 5c, the surface of the bump 4 becomes flat as a whole. Therefore, the inner lead portion 7a
And the bumps 4 are in good contact with each other, and good quality bonding can be obtained.

【００１４】実施例３．図４はこの発明の実施例３によ
る半導体素子のボンディングパッドを示す断面図であ
り、図示のように、第１層層間膜３ａ、第２層層間膜３
ｂの開口部５ａ、５ｂの寸法を小さくし、かつ開口部５
ａ、５ｂの水平方向の位置を互いにずらせて形成しても
よい。図４のものは、第１層層間膜３ａ、第２層層間膜
３ｂの段差ｔが水平方向の位置で重ならないので、段差
による影響が顕著に現れず、バンプ４の表面の凹凸は小
さくなる。Example 3. FIG. 4 is a sectional view showing a bonding pad of a semiconductor device according to a third embodiment of the present invention. As shown in the drawing, the first layer interlayer film 3a and the second layer interlayer film 3 are formed.
b, the size of the openings 5a, 5b is reduced, and
The horizontal positions of a and 5b may be offset from each other. In the case of FIG. 4, since the step t of the first layer interlayer film 3a and the second layer interlayer film 3b do not overlap at the horizontal position, the effect of the step does not appear remarkably and the bumps 4 have small irregularities on the surface. .

【００１５】[0015]

【発明の効果】以上のようにこの発明によれば、半導体
素子のそれぞれの配線パターンの層間膜開口部に開口部
より小さい層間膜を形成したので、インナーリードとバ
ンプとの良質な接合が得られる。As described above, according to the present invention, since the interlayer film smaller than the opening is formed in the interlayer film opening of each wiring pattern of the semiconductor element, a good bonding between the inner lead and the bump can be obtained. Be done.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の実施例１によるボンディングパッド
を示す断面図である。FIG. 1 is a sectional view showing a bonding pad according to a first embodiment of the present invention.

【図２】この発明の実施例１によるボンディングパッド
が形成された半導体素子の実装時を示す断面図である。FIG. 2 is a cross-sectional view showing a semiconductor element having a bonding pad formed thereon according to the first embodiment of the present invention when it is mounted.

【図３】この発明の実施例２によるボンディングパッド
を示す断面図である。FIG. 3 is a sectional view showing a bonding pad according to a second embodiment of the present invention.

【図４】この発明の実施例３によるボンディングパッド
を示す断面図である。FIG. 4 is a sectional view showing a bonding pad according to a third embodiment of the present invention.

【図５】従来のボンディングパッドを示す断面図であ
る。FIG. 5 is a cross-sectional view showing a conventional bonding pad.

【図６】従来のボンディングパッドが形成された半導体
素子の実装方法を示す展開斜視図である。FIG. 6 is a developed perspective view showing a conventional method for mounting a semiconductor element having a bonding pad formed thereon.

【図７】従来のボンディングパッドが形成された半導体
素子の実装時の断面図である。FIG. 7 is a cross-sectional view during mounting of a semiconductor element having a conventional bonding pad formed therein.

【図８】従来のボンディングパッドが形成された半導体
素子の実装時の断面図である。FIG. 8 is a cross-sectional view of a semiconductor element having a conventional bonding pad formed therein when being mounted.

【符号の説明】[Explanation of symbols]

１ 半導体素子 ２ａ 第１層層間Ａｌ配線パッド ２ｂ 第２層層間Ａｌ配線パッド ２ｃ 第３層層間Ａｌ配線パッド ３ａ 第１層層間膜 ３ｂ 第２層層間膜 ３ｃ バッシベーション ４ バンプ ７ａ インナーリード部 1 semiconductor element 2a first layer interlayer Al wiring pad 2b second layer interlayer Al wiring pad 2c third layer interlayer Al wiring pad 3a first layer interlayer film 3b second layer interlayer film 3c passivation 4 bump 7a inner lead portion

フロントページの続き (72)発明者 飛松 博 伊丹市瑞原４丁目１番地 三菱電機株式会 社北伊丹製作所内 (72)発明者 立川 透 伊丹市瑞原４丁目１番地 三菱電機株式会 社北伊丹製作所内Front page continuation (72) Inventor Hiroshi Toimatsu 4-chome, Mizuhara, Itami City, Kita Itami Works, Mitsubishi Electric Co., Ltd. (72) Inventor, Toru Tachikawa 4-c, Mizuhara, Itami City, Kita Itami Works, Mitsubishi Electric Corporation

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 少なくとも２層以上の配線パターンを有
する半導体素子において、半導体素子のそれぞれの配線
パターンの層間膜開口部に上記開口部より小さい層間膜
を形成したことを特徴とする半導体素子。1. A semiconductor element having a wiring pattern of at least two layers, wherein an interlayer film smaller than the opening is formed in an interlayer film opening of each wiring pattern of the semiconductor element. 【請求項２】 少なくとも２層以上の配線パターンを有
する半導体素子において、半導体素子のそれぞれの配線
パターンの層間膜開口部を小さくし、上記開口部をボン
ディングパッドの中央部に形成したことを特徴とする半
導体素子。2. A semiconductor element having a wiring pattern of at least two layers, characterized in that an interlayer film opening of each wiring pattern of the semiconductor element is made small and the opening is formed at a central portion of a bonding pad. Semiconductor device that does. 【請求項３】 少なくとも２層以上の配線パターンを有
する半導体素子において、半導体素子のそれぞれの配線
パターンの層間開口部を小さくし、上記開口部を水平方
向の位置を互いにずらせて形成したことを特徴とする請
求項２記載の半導体素子。3. A semiconductor element having a wiring pattern of at least two layers, characterized in that the interlayer openings of the respective wiring patterns of the semiconductor element are made small and the openings are formed so that their horizontal positions are offset from each other. The semiconductor device according to claim 2.
JP4044384A 1992-03-02 1992-03-02 Semiconductor device Pending JPH05243319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4044384A JPH05243319A (en) 1992-03-02 1992-03-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4044384A JPH05243319A (en) 1992-03-02 1992-03-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05243319A true JPH05243319A (en) 1993-09-21

Family

ID=12690016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4044384A Pending JPH05243319A (en) 1992-03-02 1992-03-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05243319A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854513A (en) * 1995-07-14 1998-12-29 Lg Electronics Inc. Semiconductor device having a bump structure and test electrode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5854513A (en) * 1995-07-14 1998-12-29 Lg Electronics Inc. Semiconductor device having a bump structure and test electrode

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