JPH05243254A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a crack and characteristic change of a semiconductor chip due to a thermal environmental variation in a high output semiconductor device. CONSTITUTION:Assemblies of pectinated emitter and base electrodes 2, 3 are disposed in parallel on a semiconductor chip 1, grooves 6 reaching opposed both sides of the chip are provided between the assemblies thereby to absorb a distortion of an active region due to a warpage of the chip generated due to a difference of linear expansion coefficients of the chip and a package, thereby preventing characteristic change and a crack.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high power semiconductor device.

[0002]

2. Description of the Related Art A conventional semiconductor device, for example, a silicon power transistor, has a strip-shaped emitter electrode 2 on an active region 7 of a semiconductor chip 1 as shown in FIG.
a and a large number of base electrodes 3a are alternately arranged and are connected as one electrode at a site other than the active region 7 on the surface of the semiconductor chip 1 to form an assembly of striped lead electrodes, or FIG. As shown in a) and (b), a plurality of strip-shaped emitter electrodes 2 and base electrodes 3 are combined to form a comb-shaped aggregate, and the aggregates are arranged in parallel on the semiconductor chip 1, Alternatively, a silicon oxide film or a polycrystalline silicon film is formed between these aggregates, or an insulating separation region between the aggregates is provided between these aggregates by an ion implantation method, a thermal diffusion method, or the like. The semiconductor chip 1 in which the leak current between them is suppressed is placed on the plane of the copper-based package 4 having good thermal conductivity by Au-Sn solder 5
Alternatively, it is mounted using solder of Au-Si eutectic alloy.

In these high-power semiconductor devices, the higher the output power, the larger the active area of the semiconductor chip and the larger the size of the semiconductor chip.

[0004]

In this conventional semiconductor device, the linear expansion coefficient of the package is larger than the linear expansion coefficient of the semiconductor chip by about one digit, so that the semiconductor chip warps in a concave shape at a high temperature and also has a low temperature. In such a state, a phenomenon that it warps in a convex shape occurs, and in a temperature environment change in actual use, or in a thermal reliability test, characteristic deterioration due to strain of the semiconductor chip surface active layer, or on the active region In many cases, a crack of a semiconductor chip that alternately extends over different electrodes was generated, resulting in a loss of function.

In order to prevent such problems, a method of dividing a semiconductor chip into small parts and mounting them has been proposed. However, this method increases the number of mounting steps and is a work within a small package. Because of this, it is often difficult.

[0006]

The semiconductor device of the present invention comprises:
Strip-shaped first and second strips are formed on the active region of the semiconductor substrate.
Of the assembly of the semiconductor chips provided by arranging the electrodes in an alternating manner and combining a plurality of the respective electrodes with each other outside the active region to combine them in a comb shape The semiconductor chip is provided with grooves which are provided between the semiconductor chips and reach the opposite sides of the semiconductor chip.

[0007]

By providing this groove, when the semiconductor device encounters a change in the thermal environment and the semiconductor chip is warped,
Since the stress is absorbed by the groove, strain in the active region is prevented, and even if a crack occurs, it occurs along the groove and has no influence on the function of the semiconductor chip. Since the groove is not intended for electrical insulation between the aggregates, it may have a depth that can absorb the strain of the semiconductor chip due to thermal change, regardless of the dimension of the active region in the depth direction.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

1A and 1B are a plan view and a schematic sectional view showing an embodiment of the present invention.

As shown in FIGS. 1A and 1B, strip-shaped emitter electrodes 2 and base electrodes 3 are alternately arranged on the upper surface of a semiconductor chip 1 and a plurality of respective electrodes are connected and combined. A plurality of aggregates are arranged in parallel, and a groove 6 parallel to the strip-shaped emitter electrode 2 on the active region 7 is provided between each aggregate from one end to the other end of the semiconductor chip, and the back surface 1Au of the semiconductor chip 1 is provided. The semiconductor chip 1 is mounted by bonding it onto the copper-based package 4 via the Sn solder 5.

The groove 6 may be provided between each group in which a plurality of aggregates having the electrodes are arranged.

[0012]

As described above, according to the present invention, the groove for absorbing the stress due to the warp of the semiconductor chip generated when the semiconductor device encounters the change of the thermal environment is provided on the upper surface of the semiconductor chip. It is possible to prevent the deterioration of the characteristics due to the change of the thermal environment which has occurred in the high power semiconductor device or the generation of cracks extending over the electrodes which are alternately different on the active region. For example, at -65 ° C to + 175 ° C. The durability in the temperature cycle between them is 10 times or more than the conventional one, and the reliability is improved.

[Brief description of drawings]

FIG. 1 is a plan view and a sectional view showing an embodiment of the present invention.

FIG. 2 is a plan view showing a first example of a conventional semiconductor device.

3A and 3B are a plan view and a cross-sectional view showing a second example of a conventional semiconductor device.

[Explanation of symbols]

 1 Semiconductor Chip 2,2a Emitter Electrode 3,3a Base Electrode 4 Package 5 Au-Sn Solder 6 Groove 7 Active Area

Claims (2)

[Claims] 1. A strip-shaped first electrode and a second electrode are alternately arranged on an active region provided on a semiconductor substrate, and a plurality of respective electrodes are connected to each other outside the active region to be combined in a comb shape. A semiconductor device comprising: an assembly; and a groove that is provided between the assembly of semiconductor chips provided by arranging the assembly in parallel with each other and reaches both opposite sides of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the groove is provided between all of the aggregates.