JPH05242678A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To transfer and to copy all memory cell data of adjacent cell array sections by connecting the I/O terminals of two sense amplifiers and two fixed terminals and providing transfer gates which are selectively connected to selection switch terminals. CONSTITUTION:Adjacent data line pairs D1 and D2 share a data register DR1 through a transfer gate TG1. Employing a two pair column decoder CD2, one pair data lines D1 and D2 of a terminal cell array section 1u1 are simultaneously selected. Moreover, by controlling the TG1, either the data line pair D1 of a fixed terminal (a) or the data line pair D2 of a fixed terminal (b) are connected to the data register DR1 through selection switch terminal c. Thus, all data of the terminal cell array section 1u1 are respectively transferred and copied to adjacent odd number data line pairs D1, D3,... +127 and even number data line pairs D2, D4,... D128 of an internal cell array section 1c2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to data transfer between a plurality of memory cell array units.

[0002]

2. Description of the Related Art A memory cell array having a basic memory capacity of 512.times.512 bits as a unit constituting a conventional semiconductor memory device has a sense amplifier (SA) group 2 of a cell array section 1 as shown in FIG. 256 data line pairs D1 to D256 to be input to are arranged in parallel in the column direction, and 512 word lines w1 to w512 connected to the column decoder (XDEC) group 5 are arranged in parallel to the row direction. Figure 3
As shown in the enlarged view of part A in (b), for example, the memory cell array MC is connected to the data D1a and D1b in the data line pair D1 and the word lines w511 and w512, and the read / write of the memory data is performed on the lower side. Sense amplifier S in SA group 2
It is performed through the data register DR1 of the data register (DR) group 3 which passes through the input / output terminal I / O of A1 and is adjacent to the lower side.

In this arrangement, each sense amplifier SA1
To SA256 and data registers DR1 to DR256
The layout pitch of is determined according to the pitch of the memory cells MC connected to the data line pair, and is set under the constraint.

Generally, the capacity size of a memory cell is 1M, 4
As the capacity increases to M, 16 Mbits, memory cells M
C tends to be reduced, but this also requires each sense amplifier SA connected to the memory cell MC and the data register DR, and in particular, each data register DR.
Are required to have high sensitivity, which causes problems in circuit technology. Also,
Generally, the data register DR is required to have a larger layout pitch α than that of the sense amplifier SA, so that the reduced layout of the data register is a particular problem.

The split type semiconductor memory device shown in FIG. 4 developed to solve this problem has an upper side of 256 × 512.
Cell array unit 1U2 having bit memory cells MC and cell array unit 1D having the same number of memory cells MC on the lower side
2 are arranged to face each other, and a shared DR group 3C is provided in the middle and dedicated DR groups 3U and 3 are provided on the upper and lower sides in the column direction, respectively.
Have D.

Here, the cell array portion 1U2 includes an upper SA group 2UU and a lower SA group 2U arranged vertically in the column direction.
D and D, and odd-numbered data line pairs D1, D3, ... D2
53, the lower end of D255 is SA1 of the lower SA group 2UD
SA126 is connected to the input / output terminal I / O, and the other end is connected to even-numbered data lines D2, D4, ...
It is formed in a comb shape with B as a boundary.

Here, the cell array portion 1U2 is also substantially divided into upper and lower parts by a curved broken line BB. Further, the lower cell array unit 1D2 is also configured to be vertically symmetrical with respect to the shared DR group 3C. Here, for example, the data of the memory cell MC connected to the data line pair D1 is sensed by the lower sense amplifier SA1, and passes through the input / output terminal I / O to latch the data register DR1 of the shared DR group 3C.

The cell array portions 1U2 and 1D2 of the two-divided semiconductor memory device have the same number of memory cells MC as a whole.
However, compared to the basic cell array unit 1 shown in FIG. 3A, each sense amplifier SA and data register DR
Is halved from 256 to 128, the layout pitch of each sense amplifier SA and data register DR is expanded, and the pitch of the data register DR can be doubled to 2α.

Next, the data transfer / copying operation between the data lines will be described. For example, when the data of all the memory cells MC on the same word line wi in the cell array unit 1U2 is transferred / copied to another word line Wj in the same cell array unit 1U2, it is at the upper and lower ends of the cell array unit. D
This can be performed by way of the R groups 3U and 3C.

However, for example, the upper cell array section 10
When the data No. 2 is transferred to the lower cell array unit 1D2, it is necessary to transfer the data to the central DR group 3C shared by the two cell array units 1U2 and 1D2.
Odd-numbered data line pair D1, sharing the DR group 3C
D3, ..., D253, D255 can be performed. However, even-numbered data line pairs D2, D4, ... D254, D
It is designed so that data on 256 cannot be transferred or copied.

[0011]

In the conventional semiconductor memory device, when all the data on the word lines in the divided cell array section is transferred / copied to the adjacent cell array section, the data register shared by both cell array sections is used. Since it is necessary to transfer the data to the data line, there is a problem that the data cannot be transferred or copied between the data lines that do not share the data register.

An object of the present invention is to provide a semiconductor memory device capable of transferring / copying all data even between adjacent divided cell array sections.

[0013]

A semiconductor memory device of the present invention includes a plurality of memory cells arranged in a matrix at intersections of a plurality of word lines and a plurality of data line pairs, and two pairs of end portions. An inner sense amplifier group which is connected to the other ends of all the data line pairs connected to the two-pair column decoder and is arranged on the inner side in the column direction, and two fixed ends are input and output of the inner sense amplifier group. An end cell array unit arranged at both ends in the column direction, a double-sided sense amplifier group arranged on both sides in the column direction, and the double-sided sense amplifiers. One end of each group is connected to every other pair of column decoders at one end, and the other end is connected to every other end to form a pair of data lines formed in a comb shape with the adjacent side; Twice as many words An internal cell array section having a line, and an input / output terminal of the selection switch of the transfer gate group and one of both side sense amplifier groups facing the selection switch terminal disposed between the end cell array section and the internal cell array section. And a shared data register group having data registers which are connected to corresponding data input / output terminals and shared with each other.

In the semiconductor memory device of the present invention, a plurality of memory cells arranged in a matrix at intersections of a plurality of word lines and a plurality of data line pairs and two pairs of columns each having two pairs of end portions. An inner sense amplifier group which is connected to the other ends of all the data line pairs connected to the decoder and is arranged on the inner side in the column direction, and two fixed ends which form a pair of input and output ends of the inner sense amplifier group. A pair of cell array sections each having a transfer gate group connected to each other and arranged to face each other in the column direction, and data input / output terminals connected to correspond to the selection switch terminals of the transfer gate group facing each other. And a shared data register group having a shared data register.

[0015]

The present invention will be described below with reference to the drawings. FIG. 1 is a schematic plan view of the first embodiment of the present invention.
The semiconductor memory device of this embodiment has 128 word lines w1.
˜w128 and data line pairs D1 to D256 are connected to 128 × 516 memory cells MC arranged in a matrix at the intersections, and two pairs of column-direction end portions are connected to each pair of column decoders CD2. Data line pair D1
An inner sense amplifier (SA) group 2u connected to the inner side end of D256 and arranged inward in the column direction, and two fixed ends a and b are respectively formed as a pair of input / output terminals I / O of the SA group 2u. Having a transfer gate (TG) group 4U connected thereto,
The end cell array section 1u1 arranged on the upper side in the column direction of the three cell array sections 1u1, 1C2, 1d1 and the end cell array section arranged on the lower side in the same symmetrical configuration as the internal cell array section 1C2. Part 1d1, one end of each of which is connected to a pair of column decoders CD1 and SA groups 2CU and 2CD arranged on the upper and lower sides, and an odd number of pairs D
The other ends of 1, D3, ... D253, D255 are connected to the upper SA group 2CU, and similarly configured even-numbered pairs D2, D
4, ... D254, D256, data line pairs D1 to D256 formed by interlacing with each other with a curved broken line BB as a boundary.
And an internal cell array section 1C2 having 256 word lines w1 to w256, and end cell array sections 1u1, 1
It is arranged between d1 and the internal cell array section 1C2,
Selective switch ends c of the TG groups 3U and 3D and input / output end I / Os of the SA groups 2CU and 2CD on both sides facing each other.
And shared DR groups 3U and 3D provided with data registers DR1 to DR128 which are respectively connected to corresponding data input / output terminals I / O and shared with each other.

Here, the structure of the internal cell array section 1C2 is similar to that of the conventional lower cell array section 1D2 shown in FIG.

Upper and lower cell array sections 1u1, 1
The number of d1 word lines is the same as the conventional cell array unit 1U of FIG.
It is half of 256 of 2 and all digit line pairs D1 to
Two adjacent D256, for example D1 and D2, are transferred to the transfer gate TG1 via the sense amplifiers SA1 and SA2.
Connected to fixed ends a and b, and the selection switch end c thereof is the input / output end I / of the data register DR1 of the shared DR group 3U.
It is connected to O. That is, the adjacent data line pair D1, D
2 share the data register DR1 via the transfer gate TG1.

Therefore, in this embodiment, the two pairs of column decoders CD2 are used to simultaneously select the two pairs of data numbers D1 and D2 in the end cell array section 1u1 and further control the transfer gate TG1 to control the fixed end a. Since either the data line pair D1 or the data line pair D2 of the fixed end 6 is connected to the data register DR1 via the selection switch end C, all the data in the end cell array unit 1u1 are respectively adjoined in the internal cell array unit 1c2. Odd numbered data line pair D1, D
3, ... D127 and even-numbered data line pairs D2, D4 ... D
It is possible to transfer / copy to each 128. Moreover, the layout layout pitch of the data register DR, which is most severely restricted, is 2α and can be kept the same as the conventional one.

FIG. 2 is a schematic plan view of the second embodiment of the present invention. In the semiconductor memory device of this embodiment, the word lines of the end cell array units 1u1 and 1d1 of the first embodiment shown in FIG. 1 are doubled and the shared DR groups 3U and 3D are set to one. .. That is, the end cell array unit 1u1 has 25
Six word lines w1 to w256 and data line pairs D1 to D2
256 arranged in a matrix at the intersection with 56
An inner SA group arranged inside in the column direction by connecting to the memory cell MC of × 516 and the data line pairs D1 to D256 whose two ends in the column direction are connected to the paired column decoder CD for two pairs. 2u and two fixed ends a and b are inside SA
TG connected to each pair of input / output terminals I / O of group 2u
The group 4U and the cell array unit 1d2 of the same structure symmetrically arranged in the column direction are paired. The shared DR group 3C has a TG to which the data input / output terminal I / O faces each other.
It has data registers DR1 to DR128 which are connected corresponding to the selection switch terminals c of the groups 4U and 4D and which are shared by both upper and lower data line pairs.

The data of the memory cells MC on both cell array units 1u2 and 1d2 are shared DR group 3C in the same manner as the circuit operation of the end cell array unit 1U1 of the first embodiment.
Through the memory cell MC of the cell array section of the other party paired with each other
Common data registers DR1 to D
The pitch design of R128 is 2α as before.

In the above embodiment, the scale of the memory cell is 51.
Although 2 × 512 is used, in the first embodiment, a plurality of internal cell array portions can be arranged in series inside the column to increase the scale. In that case, the SA groups 2u and 2d subject to pitch limitation
Since the number of SA groups 2CU and 2CD, which are twice as gentle as that of the SA group, is increased, there is an advantage that the entire pitch layout design is facilitated.

Further, in the second embodiment, the number of word lines in the cell array section can be halved to make two pairs of cell array sections 1U2 and 1D2, that is, a total of four cell array sections.

[0023]

As described above, according to the present invention, the data register between adjacent cell array sections can be shared by the data lines of the cell array section having the one-sided sense amplifier configuration.
Since the transfer gate, which is connected to the two I / O terminals and two fixed terminals of the sense amplifier and is selectively connected to the selection switch terminal, is provided, the data of all the memory cells in the adjacent cell array section are transferred to each other.・ Has the effect that copying is possible.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a first embodiment of the present invention.

FIG. 2 is a schematic plan view of a second embodiment of the present invention.

3A and 3B are a schematic plan view of a semiconductor memory device and an enlarged schematic view of an A portion thereof, respectively.

FIG. 4 is a schematic plan view of an example of a conventional semiconductor memory device.

[Explanation of symbols]

1C2 Internal cell array section 1d1, 1u1 Edge cell array section 1u2, 1d2 Cell array section 2CD, 2CU, 2d, 2u SA group 3C, 3D, 3U DR group 4D, 4U TG group 5C2, 5D1, 5D2, 5U1, 5U2 XDEC
Group Di i-th data line pair Wi i-th word line MC memory cell SA1 first sense amplifier TG1 first transfer gate DR1 first data register I / O I / O end a, b fixed end c Selection switch end CD1 1 pair column decoder CD2 2 pair column decoder α Data register pitch

Claims (2)

[Claims] 1. A plurality of memory cells arranged in a matrix at intersections of a plurality of word lines and a plurality of data line pairs, and all end portions of each pair are connected to a 2-pair column decoder. An inner sense amplifier group that is connected to the other end of the data line pair and is arranged inward in the column direction; and a transfer gate group that has two fixed ends connected to a pair of input and output ends of the inner sense amplifier group, respectively. An end cell array section arranged on both ends in the column direction, a double-sided sense amplifier group arranged on both sides in the column direction, and a column decoder for one pair each having one end on one side of the two-sided sense amplifier group. An internal portion having a data line pair formed by interleaving the opposite ends connected to every other side and interdigitated with the adjacent side, and word lines twice as many as the end cell array unit. Cell eyelay section for A data input / output terminal is arranged between the end cell array section and the internal cell array section, and corresponds to the selection switch terminal of the transfer gate group and the input / output terminal of one of the two side sense amplifier groups facing it. And a shared data register group having data registers connected to each other and shared by each other. 2. A plurality of memory cells arranged in a matrix at intersections of a plurality of word lines and a plurality of data line pairs, and all end portions connected to a pair decoder for two pairs. An inner sense amplifier group that is connected to the other end of the data line pair and is arranged inward in the column direction; and a transfer gate group that has two fixed ends connected to a pair of input and output ends of the inner sense amplifier group, respectively. And a pair of cell array portions arranged to face each other in the column direction, and a data register shared corresponding to each other corresponding to the selection switch end of the transfer gate group whose data input / output ends face each other. A semiconductor memory device comprising: a data register group.