JPH05242673A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the circuit layout area and to increase the amplification gain of a data bus amplifier by employing a prescribed column selecting gate. CONSTITUTION:When transistors(TR) Q5 and Q6 become conducting by a column selecting signal CS, in a column selecting gate 14, TRsQ1 and Q2 are connected to a data bus DB. By this, signals on bit lines BL and BLX are supplied to the data bus DB through TRsQ1, Q2, Q5, and Q6 and noise signals on the data bus DB side do not enter into the bit lines BL and BLX. On the other hand, during a writing, TRsQ3 and Q4 become conducting by writing signals W and the TRsQ5 and Q6 become conducting by the column selecting signal CS. By this, the data bus side signals are supplied to the bit lines BL and BLX through TRsQ5, Q6, Q3 and Q4 and data are writte in a sense amplifier 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a column select gate of a semiconductor memory device. More specifically, the present invention relates to a DRAM column address selection circuit.

As the storage capacity of DRAM has increased, the speed of access has been increasing. With faster access,
The timing relationship of each clock becomes strict, and a slight timing error causes malfunction. In particular, in the column selection circuit, the reset state of the bit line is released → The word line is driven and the memory cell signal appears on the bit line → The sense amplifier is driven → The signal amplitude of the bit line is increased → The column selection gate is turned on and the bit line is turned on. It is necessary to strictly adhere to the order of transmitting the signal to the data bus → amplifying the data bus signal → outputting the data from the output circuit. In particular, with regard to the timing from the driving of the sense amplifier to the conduction of the column select gate, if a margin is taken, the access time becomes long and the performance as a chip deteriorates. Before amplifying the signal or during the initial stage of the amplification, the sense amplifier malfunctions due to the noise signal due to the inflow of charges from the data bus side, resulting in the problem that the stored data is destroyed, which is troublesome. is there.

The inventor of the present invention has attempted to solve this problem by the above invention. This is because the signal is transmitted through the gate of the MOS transistor without directly connecting the bit line to the data bus line,
The interference from the data bus side is blocked to prevent malfunction. The present invention further relates to a circuit system in which this circuit is improved and a layout area can be reduced.

Further, the present invention has devised a signal voltage amplification system for the data bus. As shown in FIGS. 7 and 8, the reset voltage of the data bus is used as the power supply voltage, a level shift circuit is inserted at the input portion of the data bus voltage to the data bus amplifier, and the voltage lower than the power supply voltage is used as the data. It is to be the input to the bus amplifier. As a result, the data bus amplifier can be operated in the highest gain region.

[0005]

2. Description of the Related Art FIG. 9 shows a conventional semiconductor memory device, and FIGS. 9A and 9B respectively show a circuit diagram and a layout state of a conventional semiconductor recording device.

In FIG. 9 (A), reference numerals 10, 12, 1
Reference numeral 4 denotes a cell array, a sense amplifier, and a column selection gate (direct sense column I / O gate), respectively. In the cell array 10, the word line 16 is connected to the bit line BL via the transistor 20 having the capacitor 18, and the bit line BLX is arranged. The sense amplifier 12 includes transistors Q ₅₁ , Q ₅₂ , and Q.
Signals from the cell array 10 are amplified and supplied to the column selection gate 14 including ₅₃ and Q ₅₄ .

On the read side of the column selection gate 14, transistors Q ₁₁ and Q ₁₂ for receiving the signals of the bit lines BL and BLX and a transistor Q ₁₃ for receiving the column selection signal CS are provided. When the transistor Q ₁₃ is turned on, the signals on the bit lines BL and BLX are supplied to the read data bus 22 via the transistors Q ₁₁ and Q ₁₂ . In this way, the transistor Q ₁₁ , which receives the signals of the bit lines BL and BLX,
Since the signal cannot be written when Q ₁₂ is provided, a write-only gate circuit 24 is provided to enable writing of the signal. This write-only gate circuit 2
4 is a transistor Q ₁₄ , which receives the column selection signal CS,
Q _15, includes transistors Q _16, Q ₁₇ which receives the write signal W, the transistors Q _16, Q ₁₇ is rendered conductive by the write signal W, the transistors Q _14, Q ₁₅ by the column selection signal CS
Is turned on, the signal on the write data bus 26 is transmitted to the bit lines BL and B via the transistors Q ₁₄ , Q ₁₅ , Q ₁₆ and Q _17.
It is designed to be supplied to the LX.

[0008]

FIG. 9B shows a layout state of the conventional semiconductor memory device shown in FIG. 9A. As can be seen from FIG. 9B, the read data bus 2
2 and the write data bus 26 are respectively wired, and the transistor Q _{11 is provided under the} data buses 22 and 26, respectively.
It arranged forced to ~Q _13, Q ₁₄ ~Q _17.

It is not an essential purpose to separate the data bus for reading and writing, and the voltage of the bit line is originally MO.
The purpose was to prevent the voltage on the data bus side from being received by the gate of the S transistor from flowing into the bit line or the sense amplifier. However, due to the connection relationship of the circuits, it is necessary to use a separate system for reading and writing the data bus, and as a result of the increase in the number of wirings, the chip area increases. Here, by dividing the memory cell array to limit the length per bit line to a short value, a value required for the memory cell output signal (for example, 150 m
V), 64 rows and 12 rows of sense amplifiers
There will be as many as 8 rows. In such a case, the number of wirings of the data bus also increases in proportion to the number of sense amplifier rows, so that the number of wirings is a serious problem.

Further, in a circuit for amplifying the voltage of the data bus, when an input voltage having a voltage level equal to the power supply voltage for driving the amplifier circuit is applied, the input DC bias voltage becomes excessive as a general characteristic of the transistor. Therefore, there is a problem that the amplification gain is reduced.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of reducing the layout area of a circuit. Another object of the present invention is to provide a semiconductor memory device capable of improving the amplification gain of a data bus amplifier.

[0012]

According to the present invention, a pair of bit lines (BL, BLX), a data bus (DB), and a column selection signal (CS) are used to generate the bit lines (BL, BL).
X) and a column selection gate (14) connecting the data bus (DB), the column selection gate (14) includes a pair of bit lines (B).
L and BLX) are connected to their respective gates to form a differential pair, and first and second transistors (Q ₁ and Q ₂ ) and the first and second transistors (Q) based on a column selection signal (CS). 6th and 5th transistors (Q) for connecting the respective drains of the _first and Q ₂ ) to the data bus (DB).
₆ , Q ₅ ) and the write signal (W), the gate of the first transistor (Q ₁ ) and the fifth transistor (Q ₁ )
₅ ) and third and fourth transistors (Q ₃ , Q ₄ ) respectively connecting the gate of the second transistor (Q ₂ ) and the sixth transistor (Q ₆ ). And

The present invention also includes a data bus (DB),
In a semiconductor memory device including a data bus amplifier (36) for amplifying a signal of the data bus (DB), a power supply voltage (V _CC ) is supplied to the data bus amplifier (36), A voltage changing circuit (44, 46) is provided, which sets the reset voltage of the bus (DB) to the power supply voltage (V _CC ), shifts the level further downward, and supplies it to the input terminal of the data bus amplifier (36). To do.

FIG. 1 shows a semiconductor memory device according to the principle of the present invention, and (A) and (B) respectively show a circuit diagram and a layout state of the semiconductor memory device according to the principle of the present invention. In FIG. 1A, the cell array 10 and the sense amplifier 12 are the same as those in the conventional semiconductor recording device (FIG. 9), and thus the description thereof will be omitted.

In the column selection gate 14 of the present invention, the data bus (DB) is commonly used for reading and writing, and in order to realize this, the circuit portion between the bit lines BL and BLX and the data bus DB is improved. added. That is, the column selection gate 14 receives the transistors Q ₁ and Q ₂ for receiving the signals of the bit lines BL and BLX and detecting the voltage of the sense amplifier 12, the transistors Q ₃ and Q ₄ for receiving the write signal W, and the column selection signal CS. Includes receiving transistors Q ₅ , Q ₆ .

[0016]

In the column selection gate 14 shown in FIG. 1A, the transistors Q ₅ , Q _{6 are} supplied by the column selection signal CS.
Is turned on, the transistors Q ₁ and Q ₂ are connected to the data bus DB. As a result, the bit lines BL, BLX
Is supplied to the data bus DB through the transistors Q ₁ , Q ₂ , Q ₅ , Q ₆ , but conversely the data bus DB is supplied.
The signal on the side (noise signal) does not enter the bit lines BL and BLX.

On the other hand, at the time of writing, the write signal W turns on the transistors Q ₃ and Q ₄ , and the column selection signal CS turns on the transistors Q ₅ and Q ₆ . As a result, the signals on the data bus DB side are transmitted to the transistors Q ₅ , Q ₆ , and Q.
_It is supplied to the bit lines BL and BLX via ₃ and Q ₄ , and the data is written in the sense amplifier 12.

A layout state of the semiconductor memory device according to the principle of the present invention shown in FIG. 1A is shown in FIG. Figure 1
As can be seen from (B), the data bus DB is common for reading and writing, and the number of wirings is reduced as compared with the conventional device (FIGS. 9A and 9B).

In the present invention, column selection can be performed immediately after the word line 16 is selected and the memory cell output signal appears on the bit lines BL and BLX. by this,
A timing margin for selecting the sense amplifier 12 and the column becomes unnecessary, and the access time can be shortened by selecting the column at high speed without fear of malfunction of the sense amplifier 12.
(This is a merit of the circuit system in which a transistor for receiving a gate is inserted between the bit line and the data bus.) When such a configuration is taken, the increase in the circuit area in the vicinity of the column select gate, which has been a demerit, is It is suppressed by the circuit of the present invention.

FIG. 2 shows the relationship between the sense amplifier, the column selection gate, and the bit line when implementing the present invention. The sense amplifier SA and the column selection gate I / O are commonly used for both the left and right bit line pairs BL, BLX; BL, BLX by switching the switch transistor 28. (At the extreme end of the cell array, it is not commonly used but only one side.) Although such an arrangement is not an essential condition for the present invention, by doing so, substantial bit lines BL, BL
Since the X pitch can be increased, the column select gate I /
The layout of O becomes easy. The memory chip has many combinations (for example, 64 times) of such sense amplifiers SA, column selection gate I / Os, and bit lines BL and BLX.
It is repeatedly arranged. It will be understood from this that how the present invention can reduce the number of data bus lines by half in the whole chip.

The problem that the gain of the data bus amplifier decreases when the input voltage reaches the power supply voltage level has been solved in the present invention by inserting a level shift circuit. That is, in the present invention, the MOS transistor is diode-connected, and the bias current flowing through the MOS transistor is supplied from the data bus, so that the function of discharging the voltage charged in the wiring parasitic capacitance of the data bus is also used.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 3, the data bus wiring structure of the DRAM is hierarchized up to the final output circuit, and the column selection gate 14 of the present invention is local to the cell array 10 of the minimum division unit. It connects to the data bus 30. The local data bus 30 is connected to the global data bus 34 depending on the address accessed by the block select 32. The voltage of the global data bus 34 is amplified by the preamplifier 36, and this preamplifier 36 is also connected to the main data bus 38 depending on the address based on the GDB select 37. The main data bus 38 has a main sense amplifier and write amplifier 40.
Are connected. The amplifier 40 has a common I / O bus 42.
Connected to.

Needless to say, the present invention is not limited to such a hierarchical structure and can be applied to any data bus. FIG. 4 shows a layout state of the column selection gate 14 in the semiconductor memory device of FIG.
As can be seen from FIG. 4, the local data bus (LDB)
Under the wiring of 30, transistors Q ₁ , Q ₂ , Q ₅ , Q ₆
Are arranged, it is possible to prevent an increase in layout area despite the large number of transistors. In addition,
BL1, BL1X, BL3, BL3X are bit lines formed of polysilicon, silicaide or the like, the local data bus 30, the ground line GND are formed of aluminum or the like, and CS1 and CS3 are for column selection signals. , And W is a line for a write signal.

FIG. 5 shows another layout state of the column selection gate 14 in the semiconductor memory device of FIG. 3, and like the layout state of FIG. 4, the layout area can be prevented from increasing.

Next, FIG. 6 shows a semiconductor memory device according to another embodiment of the present invention. In FIG. 6A, the transistors Q ₁ and Q ₂ are not directly grounded, but are grounded via the transistor Q ₇ . By doing so, since the transistors Q ₁ and Q ₂ have a common impedance at the sources, the function as a differential amplifier becomes stronger, and the voltage amplification factor can be increased while reducing DC power consumption. The gate of the transistor Q ₇ is to cut the time of writing, the transistors Q _3, signal XW of the write signal W and the reverse phase to the Q ₄ enters. The merit of inserting the transistor Q ₇ is that the writing speed can be increased in addition to the differential amplification function. At the time of writing, the gates of the transistors Q ₃ and Q ₄ are at a high level and the transistors Q ₃ and Q ₄ become conductive, which causes the drains and gates of the transistors Q ₁ and Q ₂ to be coupled to each other. Configure a latch circuit. This latch connection works so as to maintain the data of the bit lines BL1 and BL1X until then in the initial stage of the write operation, and thus works to prevent the write. If this function is too strong, it may prevent writing at high speed when repeating random read / write cycles in the static column mode. Therefore, at the time of writing, the gate of the transistor Q ₇ is lowered to a low level to cut off the transistor Q _7, and the latch connection of the transistors Q ₁ and Q ₂ is released to achieve the purpose of speeding up the writing.

The circuit shown in FIG. 6B is basically the same as that shown in FIG.
Although it is the same as that of (A), the transistor Q ₇ is not inserted in each column, but is reduced to, for example, one in 64 columns to prevent an increase in the area occupied by the transistor Q ₇ .

Next, FIG. 7A is a specific circuit diagram of the semiconductor memory device of FIG. In FIG. 7A, the signals on the bit lines BL and BLX are the sense amplifier 12
Is amplified by and enters the voltage sense front end 44. This voltage sense front end 44 and transistor Q ₅ ,
The column selection gate 14 is constituted by Q ₆ . The signal from the column selection gate 14 is supplied to the local data bus 3
0, the block selection switch 32, and the global data bus 34, and the load unit (bit line load pMOS unit) 44.
And a level shift circuit (current sink and level shift unit) 46 to a data bus amplifier (voltage sense amplifier or preamplifier) 36.

The load section 44 includes a transistor Q ₂₁ ,
Including Q ₂₂ , the level shift circuit 46 includes a transistor Q
₂₃ , Q ₂₄ , Q ₂₅ , Q ₂₆ are included, and the data bus amplifier 36
Includes transistors Q ₂₇ , Q ₂₈ , Q ₂₉ , Q ₃₀ . The transistors Q _21, Q _22, the clock phi ₁ is supplied to the transistor Q _25, Q _26, the clock phi ₂ are supplied, the clock phi ₁ when the writing that is XWE (external application) is " It is at the "H" level only when it is at the "L" level and XRAS (externally applied) is at the "L" level, and is at the "L" level otherwise, and the clock φ ₂ is XR.
It is "H" level when AS (external application) is "L" level, and is "L" level otherwise. In addition, XWE,
FIG. 7B shows a circuit for generating clocks φ ₁ and φ ₂ based on XRAS. In FIG. 7B, reference numerals 48 and 50 are clock generators, and reference numeral 52 is NO.
Reference numeral 54 is an R circuit, and reference numeral 54 is an inverter (inverting circuit).

The feature of the present invention is that it has a local data bus 30 and a global data bus 3.
4 is pulled up to the power supply voltage V _CC by the pMOS transistors Q ₂₁ and Q _{22 of the} load section 44. The gates of the transistors Q ₂₁ and Q ₂₂ are grounded during the read operation, and therefore, are biased to the triode region and exhibit characteristics close to pure resistance (see FIG. 7C). Therefore, the data bus voltage is reset to the V _CC level.

Conventionally, n is diode-connected to this portion.
Although a MOS transistor was used, in this case, the voltage dropped from V _{CC by} the threshold value of the transistor is applied to the data bus. As a result, the data bus voltage is not necessarily ideal for the operation of the column selection circuit 14 in the case of a design in which V _CC is originally low. The reason is that when V _CC is low, the voltage lowered by the threshold value becomes a level close to half of the power supply voltage V _CC . For example, if V _CC is 1.5 V, the bit line is reset to 0.75 V, which is half the power supply voltage V _CC .
As a result, the gate voltage of the transistors Q ₁ and Q ₂ is approximately half the same level as the power supply voltage V _CC (actually there is an increase or decrease of the cell output voltage, but this value is 100).
It can be ignored approximately because of mV order). If the voltage lowered from V _CC by the threshold value (0.7V) is the reset level of the data bus, this is 0.8V.
That is, there is not much difference from the bit line of 0.75V.
As a result, the gate voltage and the drain voltage of the transistors Q ₁ and Q ₂ are not so different from _{each other} .
₂ will be biased in the low gain region.

On the other hand, if the data bus is pulled up to the power supply voltage V _CC by the pMOS transistors Q ₂₁ and Q ₂₂ , the above conventional problem does not occur. Furthermore, the merit of resetting the data bus to V _CC level is
This means that the power supply voltage V _CC is resistant to the bump down phenomenon. Bump down means that when some circuits operate inside the chip due to the influence of the wiring resistance of the power supply wiring, the voltage instantaneously drops due to the influence. At this time, in the conventional nMOS diode connection, the voltage of the data bus does not follow the change of the power supply voltage V _CC (when the parasitic capacitance of the data bus is large and V _CC is momentarily lowered, it is pulled up to V _CC. (Since the diode-connected nMOS transistor is in the reverse bias state of the diode and cuts off), the voltage relationship between the power supply voltage V _CC and the data bus is relatively _deviated and the operation of the data bus amplifier 36 is hindered (there is a problem). The input voltage level is relatively high with respect to the power supply voltage V _CC ).

On the other hand, if the data bus is reset to V _CC by the pMOS transistors Q ₂₁ and Q ₂₂ , V _CC
Is transmitted to the data bus (since the pMOS transistor is not diode-connected and is not cut off due to its resistance), the above-mentioned conventional problems do not occur.

Incidentally, when the data bus is pulled up to the power supply voltage V _CC as described above, there is a problem that the input voltage level becomes V _CC level for the data bus amplifier 36. In this case, the transistors Q _{27 to} Q _{30 in} the input portion of the data bus amplifier 36 have a high gate voltage with respect to the drain, and may enter the bias state in the triode region, resulting in a small gain. Therefore, the transistor Q ₂₃ ~
A level shift circuit 46 is constituted by Q ₂₆ , and a voltage obtained by lowering the voltage of the data bus by the gate-source voltage of the transistors Q ₂₃ and Q ₂₄ is applied to the data bus amplifier 36. The level shift circuit 46 is configured by using a voltage of about the threshold current generated by causing the transistors Q ₂₅ and Q ₂₆ to pass minute currents and causing the currents to generate in the transistors Q ₂₃ and Q ₂₄ . The currents flowing through the transistors Q ₂₅ and Q ₂₆ are not only for level shifting, but the data bus voltage is prevented from being relatively excessively lifted due to bump down by always pulling the data bus charge slightly to the ground side. It also has the function of doing.

The data bus amplifier 36 is a differential amplification type current mirror load type voltage amplification type amplifier, and the output thereof is connected to a current driver 56 composed of pMOS transistors Q ₃₁ and Q ₃₂ . The transistors Q ₃₁ and Q ₃₂ are for driving the main data bus 38, and when the data bus amplifier 36 is selected, the transistor Q ₃₃ is turned on to differentially amplify the current to the bus 38. give.

A current detection amplifier (main sense amplifier and write amplifier) 40 is connected to the end of the main data bus 38, and the current driven by the transistors Q ₃₁ and Q ₃₂ is detected, and the latch circuit 58 makes a large amplitude. It amplifies and provides read data to the output buffer amplifier.

The load section 44 and the level shift circuit 46 shown in FIG. 7 can be applied to other types of circuits.
As shown in FIG. 8, it can be applied to the case where the output of the sense amplifier, that is, the latch type sense circuit 12 is directly connected to the data bus 30 through the column selection gate 14 '.
Here, since the transistor of the sense amplifier 12 also starts operating from the state of half the power supply voltage, if the reset potential of the data bus 30 is also reset to a level close to half the power supply voltage, the charge of the data bus 30 will be sensed. 12
It takes time to pull out from the side, and access becomes slow.
On the other hand, according to the present invention, the potential of the data bus 30 is set to the power supply voltage V _CC (including the internal power supply voltage created in the chip), so that this problem is solved.

[0038]

As described above, according to the present invention,
Since the column select gate has a unique circuit configuration, the layout area of the circuit can be reduced. Further, according to the present invention, since the voltage of the data bus is changed, the amplification gain of the data bus amplifier can be improved.

[Brief description of drawings]

FIG. 1 shows a semiconductor memory device according to the principles of the present invention,
(A) and (B) are a circuit diagram and a layout state diagram, respectively.

FIG. 2 is a diagram showing a relationship between a sense amplifier, a column selection gate, and a bit line.

FIG. 3 is a circuit diagram of a semiconductor recording device according to an embodiment of the present invention.

FIG. 4 is a layout state diagram of column select gates in the semiconductor memory device of FIG.

FIG. 5 is another layout state diagram of the column selection gate in the semiconductor memory device of FIG.

FIG. 6 is a circuit diagram of a semiconductor memory device according to another embodiment of the present invention.

FIG. 7 is a circuit diagram of a semiconductor memory device having a level shift circuit.

FIG. 8 is a circuit diagram of another semiconductor memory device having a level shift circuit.

9A and 9B show a conventional semiconductor memory device, and FIGS.
Are a circuit diagram and a layout state diagram, respectively.

[Explanation of symbols]

10 ... Cell array 12 ... Sense amplifier 14 ... Column selection gate Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ ... Transistor W ... Write signal CS ... Column selection signal DB ... Data bus

Claims (7)

[Claims] 1. A pair of bit lines (BL, BLX), a data bus (DB), and the bit line (BL, BLX) and the data bus (D) based on a column selection signal (CS).
In a semiconductor memory device including a column selection gate (14) connected to B), the column selection gate (14) has a pair of bit lines (BL, BLX) connected to respective gates to form a differential pair. The first and second transistors (Q
₁ and Q ₂ ) and a sixth and a fifth connecting the drains of the first and second transistors (Q ₁ and Q ₂ ) to the data bus (DB) based on the column selection signal (CS). Transistors (Q ₆ , Q ₅ ) and a gate of the first transistor (Q ₁ ) and the fifth transistor (Q ₅ ) are connected to the second transistor (Q ₂ ) based on the write signal (W). Gate and the sixth
A semiconductor memory device comprising: a _third transistor and a fourth transistor (Q ₃ , Q ₄ ) respectively connecting the transistor (Q ₆ ). 2. The semiconductor memory device according to claim 1, wherein a seventh transistor (Q ₇ ) is connected between the first and second transistors (Q ₁ , Q ₂ ) and a ground level,
A semiconductor memory device characterized in that the first and second transistors (Q ₁ , Q ₂ ) constitute an operational amplifier circuit. 3. The semiconductor memory device according to claim 2, wherein when a write signal (W) is supplied to the third and fourth transistors (Q ₃ , Q ₄ ), the seventh transistor (Q ₇ ) Is a signal (X) opposite in level to the write signal (W).
W) is supplied to the semiconductor memory device. 4. The semiconductor memory device according to claim 2, wherein the seventh transistor (Q ₇ ) is commonly connected to a plurality of column addresses. 5. A data bus (DB) and a data bus amplifier (36) for amplifying a signal of the data bus (DB).
In the semiconductor memory device including: and, the data bus amplifier (36) has a power supply voltage (V _CC ).
Is supplied, and the reset voltage of the data bus (DB) is the power supply voltage (V
_CC ), further level-shifted downward, and supplied to the input terminal of the data bus amplifier (36).
4, 46). 6. The semiconductor memory device according to claim 5, wherein the voltage change circuit (44, 46) includes a load section (44) for setting a reset voltage of the data bus (DB) to a power supply voltage (V _CC ). A level shift circuit (46) for shifting the voltage of the data bus (DB) downward, and the load unit (44) is connected between the power supply voltage (V _CC ) and the data bus (DB). has a pMOS transistor (Q _21, Q ₂₂₎ that, said level shift circuit (46), a data bus (DB)
The drain and gate are connected to the data bus amplifier (3
NMOS transistors (Q ₂₃ , Q ₂₄ ) whose sources are connected to the input terminal of 6) and pull-down elements (Q ₂₅ , Q ₂₆ ) for pulling down the voltage of the input terminal of the data bus amplifier (36) toward the ground level. A semiconductor memory device comprising: 7. The semiconductor memory device according to claim 6, wherein the pMOS transistors (Q ₂₁ , Q ₂₂ ) and the pull-down elements (Q ₂₅ , Q ₂₆ ) are cut off during writing. apparatus.