JPH0524226Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a digital signal generator used, for example, in testing semiconductor integrated circuits.

(Prior Art) For example, as a digital signal generator used for testing digital semiconductor integrated circuits, high level and low level can be set freely, and tri-state operation can provide high level output, low level output, and high impedance output. It is necessary to be able to obtain high-speed output, and to be able to protect the output.

FIG. 4 is a block diagram showing an example of such a conventional device. In Figure 4, V _H is a high level power supply terminal, V _L is a low level power supply terminal, and a switch circuit is connected between these power supply terminals V _H and V _L.
SWa and SWb are connected in series. Ta is an input terminal for a digital pattern signal represented by "1" and "0", and Tb is an input terminal for a control signal for controlling tri-state operation. input terminal
Ta is connected to one input terminal of the gate Ga via the inverter INV and directly connected to one input terminal of the gate Gb, and the input terminal Tb is directly connected to the other input terminal of the gate Ga and the gate Gb is connected to the other input terminal of The output signals of these gates Ga and Gb are the switch circuit
This is used as the opening/closing control signal for SWa and SWb, and the output signal of gate Ga is the switch circuit.
The output signal of gate Gb is applied to switch circuit SWa. switch circuit
A digital signal output terminal To of the device is connected to the connection point between SWa and SWb via an output resistor Ro.

In such a configuration, the switch circuit SWa
When switch circuit SWa is on and SWb is off, a high level signal is output, and when switch circuit SWa is off, SWb
When is on, a low level signal is output,
When both switch circuits SWa and SWb are off, the output becomes high impedance.

However, according to the configuration shown in FIG. 4, it is necessary to use high-speed elements with relatively high breakdown voltage as the switch circuits SWa and SWb, which increases the cost. Furthermore, in order to protect the output circuit, a separate protection circuit must be provided, which further increases costs.

Therefore, as a device to solve these drawbacks, current switches connected in series via digital signal output terminals are driven in accordance with an output level control signal, and output level control is connected via a diode to the connection point of these current switches. Some are configured to apply a configuration signal.

FIG. 5 is a block diagram showing an example of such a device. In Figure 5, HL is a high-level setting power supply that supplies a high-level signal to the DC level at terminal _VH , and IS ₁ is a high-level setting power supply that supplies a high-level signal to the DC level, and IS 1 is a power supply that can be set in three states, 0, I, and 2I, depending on the control signal applied from control circuit CL _1. The first current source IS 2 is composed of a current switch that outputs current, and IS ₂ is composed of a current switch that outputs current in three states of 0, -I, and -2I according to the control signal applied from control circuit CL ₂ . a second current source,
LL is a low level setting power supply that provides a low level signal at a DC level to the terminal _VL . D ₁ is a first diode whose anode is connected to the output terminal of the first current source IS ₁ and whose cathode is output to the output terminal of the high level setting power supply HL, and D ₂ is the first diode whose anode is connected to the output terminal of the first current source IS 1.
A second diode _D3 is connected to the output terminal of the current source IS ₁ and has its cathode connected to the digital signal output terminal To of the device;
The third diode connected to the output terminal of the current source IS ₂ , D ₄ has its anode set to the low level power supply LL
and a fourth diode whose cathode is connected to the second current source _IS2 . Furthermore, the diode
Pair diodes are used for D ₁ and D ₂ and D ₃ and D ₄ , respectively.

FIG. 6 is a circuit diagram showing a specific example of the main part of FIG. 5. The first current source IS ₁ includes transistors Q ₁ ,
The first current switch CSa consists of transistors Q ₂ and is controlled on and off by the control signal applied from the control circuit CL ₁ , and the first current switch CSa consists of transistors Q ₃ and Q ₄ and is turned on and off by the control signal applied from the control circuit CL ₁ . Second current switch CSb controlled off
and a cascode transistor _Q5 . On the other hand, the second current source _IS2 is a transistor
A third current switch CSc is turned on and off by a control signal applied from a control circuit CL ₂ consisting of Q 6 and Q ₇ , and a third current switch CSc is applied from a control circuit CL ₂ consisting of transistors Q _{8 and} Q ₉ . It consists of a fourth current switch CSd and a cascode transistor _Q10 , which are controlled on and off by a control signal. In addition, each current switch CSa to CSd
The circuits are configured so that currents Ia to Id having the same current value I are output from each of them.

In such a configuration, each control circuit CL ₁ ,
CL ₂ switches each current switch according to the state of the output.
A control signal is output to control CSa to CSd to be in the on/off state as shown in FIG. When the output is at a high level, current switches CSa and CSb are turned on, so the discharge side current becomes 2I, and current switch CSc is turned off and CSd is turned on, so the suction side current becomes I. The output level increases with these differences I. Then, when the output level approaches V _H , diode _D1 turns on,
The difference flows into the high level setting power supply HL through the diode _D1 . When there is no load, the currents flowing through the diodes D ₁ and D ₂ are equal, and since the characteristics of the diodes D ₁ and D ₂ are equal, the output level Vo becomes V _H. When the output is at low level, current switch CSa turns off and CSb turns on, so the discharge side current becomes I, and current switches Csc and CSd turn on, so the suction side current becomes 2I. The output level is reduced by these differences I. Then, when the output level approaches V _L , diode _D4 is turned on, and the difference is output from low level setting power supply LL via diode _D4 . If there is no load, the diode
The currents flowing through D ₃ and D ₄ are equal and the diode
Since the characteristics of D ₃ and D ₄ are equal, the output level Vo is
V _L , and the output level is set to V _L by diode _D4 .
It will be clamped to the level of In high impedance state, current switch CSa~CSd
Both are turned off and the output becomes high impedance.

This configuration provides a low-cost device that has high speed, small output offset, large amplitude and good linearity, and essentially has a current limiter function.

(Problem to be solved by the invention) However, according to such a configuration, when the difference between the high level signal V _H and the low level signal V _L becomes small,
The problem is that current flows through the diode _D1 or _D4 , which should normally be cut off, and as the amplitude decreases, the offset increases, making it impossible to obtain a pulse signal with a small amplitude (for example, 0.5Vpp or less). There is. Such an offset can be reduced if the parasitic resistance of the diode is small, but it cannot be completely eliminated.

The present invention was developed with attention to these points, and its purpose is to add a minute amplitude voltage to the high-level setting voltage and low-level setting voltage according to the output state, thereby increasing the cut-off side. It is an object of the present invention to provide a digital signal generator that can obtain a pulse signal with a small amplitude by eliminating the influence of the current flowing through the diode.

(Means for Solving the Problems) The present invention that solves the above-mentioned problems includes a high-level setting power supply, first and second current sources that can take three output current states, and a low-level setting power supply. a first diode connected between the high level setting power supply and the first current source; and a second diode connected between the first current source and the output terminal of the device.
a third diode connected between the second current source and the output terminal of the device, and a fourth diode connected between the low level setting power source and the second current source. , a first adding means connected between the high level setting power supply and the first diode and adding a minute amplitude voltage +ΔV to the output voltage from the high level setting power supply when outputting a low level; and the low level setting power supply; and second adding means connected between the fourth diode and adding a minute amplitude voltage -ΔV to the output voltage from the low level setting power supply when outputting a high level. .

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this figure, the same parts as in FIG. 4 are designated by the same reference numerals, and their explanation will be omitted.

In the device of this invention, the high level setting power supply
A first addition means AD ₁ is connected between HL and the first diode D ₁ , and a low level setting power supply is connected.
A second adding means _AD2 is connected between LL and the fourth diode _D4 .

The first addition means AD ₁ outputs a minute amplitude voltage ΔV of about 0.5Vpp in the low level output state.
and the output voltage V _H from the high level setting power supply HL are added. In addition, the second addition means AD ₂ outputs a minute amplitude voltage -ΔV of about -0.5Vpp output in the high level output state and a low level setting power supply LL.
Add the output voltage V _L from .

To explain the operation of the device configured in this way,
It is as follows. First, let us take the operation in a high level output state as an example. In this state, the minute amplitude voltage ΔV is not added to the high level setting voltage V _H , and the first, second, and third diodes D ₁ , D ₂ , D ₃
is conductive (see FIG. 7) and the currents flowing through the first and second diodes D ₁ and D ₂ are equal, the output level of the output terminal To is equal to V _H .

Here, when the difference between the high level setting voltage V _H and the low level setting voltage V _L becomes small, for example, 0.5 V or less, the fourth diode D ₄ which was in the cut-off state starts to conduct, and therefore the first diode The currents flowing through the second diodes D ₁ and D ₂ are no longer equal.
In the device of the present invention, in this state, the second addition means AD ₂ outputs a voltage (V _L −ΔV) obtained by adding the minute amplitude voltage −ΔV to the output voltage V _L of the low level setting power supply LL. 4th diode
The anode potential of D ₄ is lowered by ΔV to prevent this fourth diode D ₄ from starting to conduct.

In low level output state, minute amplitude voltage -ΔV
is not added to the low level setting voltage V _L ,
Assume that the second, third, and fourth diodes D ₂ , D ₃ , and D ₄ are conducting (see Figure 7), and the currents flowing through the third and fourth diodes D ₃ and D ₄ are equal. Then, the output level of the output terminal To is equal to V _L.

Here, when the difference between the high level setting voltage _VH and the low level setting voltage _VL becomes small, for example, 0.5V or less, the first diode _D1 , which has been in the cut-off state, begins to conduct. however,
In this state, the first addition means AD ₁ outputs a voltage (V _H +ΔV) obtained by adding the small amplitude voltage ΔV to the output voltage V _H of the high-level setting power supply H _L.
Therefore, the cathode potential of the first diode _D1 is increased by ΔV, which prevents the first diode _D1 from becoming conductive.

This operation eliminates the influence of the current flowing through the cut-off side diode, making it possible to output a pulse signal with a small amplitude.

FIG. 2 shows the addition means AD ₁ ,
FIG. 2 is a circuit diagram showing a specific example of AD ₂ . The minute amplitude voltage ±ΔV must be quickly added to the high level setting voltage V _H and the low level setting voltage V _L , but
The addition means does not necessarily have to be high speed. The reason is that the amplitude voltage added to the set voltage is small compared to the set voltage, and here,
It is constructed by combining known constant speed buffers. In FIG. 2, A is a buffer amplifier, R and _R1 are resistors, and C is a capacitor. Capacitor C is
A bypass circuit is configured and the minute amplitude voltage ΔV(−
ΔV) is directly applied to the output terminal _T1 . This achieves high-speed operation with respect to minute amplitude voltage ΔV (−ΔV). The resistor _R1 , together with the capacitor C, constitutes a low-pass filter, which supplies only the low frequency components from the buffer amplifier A and prevents the high frequency components produced by the capacitor C from entering the output of the buffer amplifier A.

FIG. 3 shows the adding means in the device shown in FIG.
Minute amplitude voltage ±ΔV applied to the input terminals of AD ₁ and AD ₂
FIG. 2 is a circuit diagram showing a specific example of a generating circuit. In this circuit, at the bases of transistors Q ₁₁ and Q ₁₂ ,
By applying a signal that changes depending on the high level and low level states, these transistors
Turn on and off Q ₁₁ , Q ₁₂ and each diode D ₁₁ ,
Through _D12 , minute amplitude voltages +ΔV and -ΔV are obtained alternately. Note that the resistor _R11 is made sufficiently small to lower the output impedance.

(Effect of the invention) As explained above, the present invention adds a minute amplitude voltage of +ΔV or -ΔV to the high-level setting voltage and the low-level setting voltage according to the output state in the circuit shown in FIG. This eliminates the influence of the current flowing through the diode on the cut-off side.It has a relatively simple configuration, has the characteristics necessary for testing digital semiconductor integrated circuits, and can output small amplitude pulse signals with good linearity. A digital signal generator can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the device according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the adding means used in the device shown in FIG. 1, and FIG.
4 and 5 are block diagrams showing an example of a conventional device. FIG. 6 is a circuit diagram showing a specific example of the main part of FIG. 5.
The figure is an explanatory diagram of the operating state of FIG. 6. HL...High level setting power supply, LL...Low level setting power supply, _D1 to _D4 ...1st to fourth diodes, _IS1 , _IS2 ...constant current source, To...output terminal,
AD ₁ , AD ₂ ...first and second addition means.

Claims (1)

[Scope of utility model registration request] A high level setting power supply, first and second current sources that can take three states as output current states, a low level setting power supply, and a power supply connected between the high level setting power supply and the first current source. a first diode, a second diode connected between the first current source and the output terminal of the device, and a third diode connected between the second current source and the output terminal of the device; a fourth diode connected between the low-level setting power source and the second current source; and a fourth diode connected between the high-level setting power source and the first diode, and a current source connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a fourth diode connected between the high-level setting power source and the first diode, and a current source connected between the high-level setting power source and the first diode. a first adding means for adding a minute amplitude voltage +ΔV to the output voltage of the power supply; and a first addition means connected between the low level setting power supply and the fourth diode, adding a minute amplitude voltage to the output voltage from the low level setting power supply when outputting a high level. - second addition means for adding ΔV.