JPH05241734A - Disk storage device - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines and cables set between a write/read control circuit and a write/read circuit for reduction of the size and the cost of each circuit and to improve the quality and the maintenance properties of both circuits. CONSTITUTION:The write/read control information and the write/read error information are transferred in a serial data form between a write/read control circuit 1 and a write/read circuit 2. Therefore the circuits 1 and 2 contain the write/read control information converters 3 and 6 and the write/read error information converters 4 and 7 respectively. Furthermore the data switch circuits 5 and 9 are added since the circuits 1 and 2 share a high speed serial data transfer signal and a signal line for transfer of the write/read data. Then the circuit 2 is provided with a write/read error signal generating circuit 8 which outputs an error signal to inform the circuit 1 of the occurrence of a write/read error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk storage device, and more particularly, it transfers write / read control information and write / read error information between a write / read control circuit and a write / read circuit by parallel data transfer. Disk storage device improvement.

[0002]

2. Description of the Related Art Conventionally, in this type of disk storage device,
Write / read control information and write / read error information are exchanged as parallel data between the write / read control circuit and the write / read circuit. Therefore, the number of signals between the write / read control circuit and the write / read circuit is large. In particular, in medium- and large-sized disk storage devices, since the write / read control circuit and the write / read circuit are often arranged separately, a cable is used for transmitting and receiving signals. Therefore, as the number of signals increases, the number of cables also increases, which raises the problems of high cost, large-sized equipment, and increased equipment failures due to cable failures.

A write / read circuit is often mounted around a head disk assembly (hereinafter referred to as HDA), and is connected to the write / read circuit during maintenance work of the HDA. The cable may be removed and the HDA may be removed from the disk storage device body. At this time, when the number of signals is large, that is, when the number of cables is large, the work time for maintenance work is increased and work mistakes at the time of attaching or detaching the cables are increased.

[0004]

The problem to be solved is that the number of signal lines between the write / read control circuit and the write / read circuit is large.

[0005]

The present invention is characterized in that write / read control information and write / read error information are transmitted / received by serial data between a write / read control circuit and a write / read circuit. ..

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a disk storage device according to the present invention. In FIG. 1, 1 is a write / read control circuit, 2 is a write / read circuit, and 3 and 6.
Are write / read control information conversion circuits, 4 and 7 are write / read error information conversion circuits, 5 and 9 are serial information switching circuits, and 8 is a write / read error signal generation circuit.

The write / read control information conversion circuit 3, the write / read error information conversion circuit 4, and the serial information switching circuit 5 are placed inside the write / read control circuit 1. Further, the write / read control information conversion circuit 6,
The write / read error information conversion circuit 7, the write / read error signal generation circuit 8, and the serial information switching circuit 9 are placed inside the write / read circuit 2. The write / read enable signal on the signal line 100 and the signal line 101
The above-mentioned write / read switching signal refers to a write / read control information conversion circuit 3, a serial information switching circuit 5, from a control circuit (not shown) inside the write / read control circuit 1.
It is output to the control circuit (not shown) inside the write / read control information conversion circuit 6, the serial information switching circuit 9, and the write / read circuit 2. The write / read enable signal on the signal line 100 is also output to the write / read error information conversion circuit 7.

In the write / read control information conversion circuit 3, the write / read enable signal on the signal line 100 is "L" and the write / read switching signal on the signal line 101 is changed from "L" to "H". When there is a change, the write / read control information on the signal line 108, which is parallel data, is converted into the write / read control information on the signal line 109, which is serial data, and is output to the serial information switching circuit 5.
The write / read error information conversion circuit 4 converts the write / read error information on the signal line 116, which is serial data, into the write / read error information on the signal line 117, which is parallel data. Further, when the write / read error signal reset signal on the signal line 119 is “L” and the write / read error signal on the signal line 103 changes from “L” to “H”, the signal line 118 is reset. The write / read error signal of is set to "H". On the other hand, when the write / read error signal reset signal on the signal line 119 is “H”, the write / read error signal on the signal line 118 is set to “L” and the write / read error information on the signal line 117 is written. The value is "0".

The serial information switching circuit 5 includes a signal line 100.
When the upper write / read enable signal is "H" and the write / read switching signal on the signal line 101 is "H", the write data on the signal line 104 is transferred to the signal line 102 as serial data. Output. When the write / read enable signal on the signal line 100 is “H” and the write / read switch signal on the signal line 101 is “L”, the serial information switching circuit 5 outputs the serial information on the signal line 102. The data is output onto the signal line 107 as read data.

The serial information switching circuit 5 includes a signal line 10
0 is the write / read enable signal is "L", the write / read error signal on the signal line 103 is "L", and the write / read switching signal on the signal line 101 is "H". To output, the write / read control information on the signal line 109 is output to the signal line 102 as serial data. In the serial information switching circuit 5, the write / read enable signal on the signal line 100 is “L” and the signal line 103
When the upper write / read error signal is "H", the serial data on the signal line 102 is output to the signal line 116 as write / read error information.

The write / read error information on the signal line 116 is output to the write / read error information conversion circuit 4, and the serial data on the signal line 102 is exchanged between the serial information switching circuits 5 and 9. In the write / read control information conversion circuit 6, the write / read enable signal 100 on the signal line 100 is “L” and the write / read switching signal on the signal line 101 is changed from “L” to “H”. In this case, the write / read control information on the signal line 110, which is serial data, is converted to the signal line 11 that is parallel data.
1 to write / read control information and output.

The write / read error signal generation circuit 8 is
When any one of the write / read error detection signals of the signal lines 112-1, 112-2, ... 112-n becomes “H”, the write / read error signal on the signal line 103 is output. The signal is set to “H” and output, and the write / read error information transfer signal on the signal line 115 changes from “H” to “L”.
When it changes to, the write / read error signal on the signal line 103 is set to "L" and output. In addition, the signal line 10
The write / read error detection signal (112) at the time when the write / read error signal on 3 changes from “L” to “H”
-1, 112-2, ..., 112-n) are held and output as write / read error information to the write / read error information conversion circuit 7 via the signal line 113. The write / read error signal on the signal line 103 is output to the write / read error information conversion circuit 7, the serial information switching circuit 9, the write / read error information conversion circuit 4, and the serial information switching circuit 5.

The write / read error information conversion circuit 7 is
When the write / read error signal on the signal line 103 is “H” and the write / read enable signal on the signal line 100 changes from “H” to “L”, the signal line 113 which is parallel data. Write / read error information above
The serial data is converted into write / read error information on the signal line 114, and output to the serial information switching circuit 9 is started. At this time, the write / read error information transfer signal on the signal line 115 is set to “H”, and after the conversion is completed, the write / read error information transfer signal on the signal line 115 is set to “L”. The write / read error information transfer signal on the signal line 115 is output to the write / read error signal generation circuit 8.

The serial information switching circuit 9 includes a signal line 10
The write / read enable signal on 0 is "H", and the write / read switching signal 101 on the signal line 101 is "H".
In this case, the serial data on the signal line 102 is output to the signal line 105 as write data. The serial information switching circuit 9 reads the signal line 106 when the write / read enable signal on the signal line 100 is “H” and the write / read switching signal on the signal line 101 is “L”. The data is output as serial data to the signal line 102.

The serial information switching circuit 9 outputs a signal when the write / read enable signal on the signal line 100 is "L" and the write / read error signal on the signal line 103 is "H". The write / read error information on the line 114 is output to the signal line 102 as serial data. On the other hand, the serial information switching circuit 9 uses the signal line 100
The upper write / read enable signal is "L", the write / read error signal on the signal line 103 is "L",
When the write / read switching signal on the signal line 101 is "H", the serial data on the signal line 102 is output on the signal line 110 as write / read control information.

Next, the overall operation will be described in the following four cases. That is, the first is the case where the write data on the signal line 104 is written in the HDA, and the second is the HDA.
A case where the read data is read on the signal line 106,
The third case is to transfer the write / read control information on the signal line 108 to the write / read circuit 2, and the fourth is the signal line 11
This is a case where the write / read information on 3 is read from the write / read circuit 2.

In the first case, the write / read enable signal on the signal line 100 and the write / read enable signal on the signal line 101.
When the read switching signals are both set to "H", the signal line 10
The write data on No. 4 is output to the write data signal line 105 through the serial data signal line 102. next,
In the second case, assuming that the write / read enable signal on the signal line 100 is “H” and the write / read switching signal on the signal line 101 is “L”, the read data on the signal line 106 is the serial data 102. It is output to the read data signal line 107 through the signal line.

Subsequently, as a third case, the signal line 10
The write / read enable signal on 0 is set to "L", and the signal line 1
01 write / read switching signal from "L" to "H"
The parallel data write / read control information on the signal line 108 is converted to serial data write / read control information inside the write / read control information conversion circuit 3, and the signal line 109 to the serial data signal line are changed. 1
02, and the signal line 11 as write / read control information.
Output to 0. Further, the write / read control information on the signal line 110 given in the form of serial data is converted into parallel data write / read control information inside the write / read control information conversion circuit 6, and the signal line 111.
Output above.

Finally, as a fourth case, write / read error detection signal lines 112-1, 112-2, ... 1
The signal level is "H" in any one of 12-n.
Then, ie an error is detected during writing and reading. At this time, the write / read error signal on the signal line 103 becomes "H", and the write / read on the signal line 113 is performed.
The content of the read error information is retained. At this time, the above state is held until the write / read error signal on the signal line 118 becomes “H” and the write / read error signal reset signal on the signal line 119 becomes “H”. At this time, the write / read enable signal on the signal line 100 is "H".

Subsequently, when the write / read enable signal on the signal line 100 becomes "L", the write / read error information on the signal line 113 given in the parallel data format is written to the write / read error information conversion circuit 7. It is internally converted into serial data write / read error information 114 and output to the signal line 114. At this time, the write / read error information transfer signal on the signal line 115 becomes "H". The converted write / read error information 114 is stored in the signal line 1
14 through the serial data signal line 102 to write / write
The read error information is output to the signal line 116. After the conversion by the write / read error information conversion circuit 7 is completed, the write / read error information transfer signal on the signal line 115 becomes “L” and the write / read error signal on the signal line 103 also becomes “L”. On the other hand, the serial data write / read error information transmitted to the signal line 116 is converted into parallel data write / read error information inside the write / read error information conversion circuit 4 and output to the signal line 117. It

Next, another embodiment of the disk storage device according to the present invention will be described. FIG. 2 is a block diagram showing a second embodiment of the disk storage device according to the present invention.
In FIG. 2, 10 is a write / read control circuit, 20 is a write / read circuit, 30 and 60 are write / read control information conversion circuits, and 40 and 70 are write / read control circuits.
A read error information conversion circuit, 50 and 90 are serial information switching circuits, respectively, and 80 is a write / read error signal generation circuit. 2 is different from the disk storage device shown in FIG. 2 in that the write / read error signal line 103, the write / read error signal line 118, and the write / read error signal reset signal line in FIG. 119 does not exist.

Regarding the operation, the first to third cases in the description of the operation of the disk storage device according to FIG. 1 are the same. In the fourth case, since the write / read error signal line 103 does not exist, it is necessary to read the write / read error information from the signal line 113 every time the write and read operations are executed. The actual operation will be described. When the level becomes “H” on any one of the write / read error detection signal lines 112-1, 112-2, ... 112-n, an error is detected during writing and reading. In this case, the write / read error detection signal at the time of detection is held on the signal lines 112-1, 112-2, ..., 112-n, and the signal line 11 is used as write / read error information.
3 is output. If no errors are detected,
The write / read error information on the signal line 113 is “0”.

When the write / read switching signal on the signal line 101 is "L" and the write / read enable signal on the signal line 100 changes from "H" to "L", the signal line 113 The parallel data writing / reading error information is converted into serial data writing / reading error information inside the writing / reading error information conversion circuit 7 and sent out on the signal line 114. At this time, the write / read error information transfer signal on the signal line 115 becomes "H".
The converted write / read error information is sent to the signal line 114.
Is output to the write / read error information line 116 through the serial data signal line 102. After the conversion by the write / read error information conversion circuit 7 is completed, the signal line 1
The write / read error information transfer signal on 15 becomes "L", and the write / read error information on the signal line 113 also becomes "0". On the other hand, the serial data write / read error information sent to the signal line 116 is converted into parallel data write / read error information 117 inside the write / read error information conversion circuit 4, and the signal line 11
7 is output.

[0024]

As described above, the present invention is capable of writing / writing.
Write / read between the read control circuit and the write / read circuit
When transmitting / receiving the read control information and the write / read error information, the method of transmitting / receiving by serial data is used, and the signal of write / read data also coexists with the serial data. There is an advantage that the number of signals between the circuit and the write / read circuit is small. That is, there is an advantage that the number of cables between the write / read control circuit and the write / read circuit is reduced.
For this reason, the cost can be reduced by reducing the number of cables, the device can be downsized by reducing the cable wiring space, the quality can be improved by reducing cable failures, and the maintenance work can be facilitated by reducing the amount of work when installing / removing cables. effective. Further, when data is transferred and received by serial transfer, the transfer time is usually long. However, in the present invention, the signal line for high speed serial transfer, which has been used for transfer of write / read data in the past, is also shared. There is an effect that data can be transferred by.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a disk storage device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the disk storage device according to the present invention.

[Explanation of symbols]

1,10 Write / read control circuit 2,20 Write / read circuit 3,6,30,60 Write / read control information conversion circuit 4,7,40,70 Write / read error information conversion circuit 5,9,50,90 Serial information switching circuit 8,80 Write / read error signal generation circuit 100 to 111, 112-1, 112-2, 112-
n, 113-119 signal line

Claims (4)

[Claims] 1. A write / read control signal and a write / read control signal.
A write / read control circuit for transmitting / receiving a read error signal and controlling write / read, and a write / read circuit for transmitting / receiving the write / read control signal and the write / read error signal and performing write / read And write / read control information for selecting a write / read head and correcting a write / read signal between the write / read control circuit and the write / read circuit, and the write / read circuit. A disk storage device comprising: a plurality of signal lines for transferring detected write / read error information in a serial data format. 2. A first write / read control information conversion circuit for performing parallel / serial conversion of the write / read control information to the write / read control circuit, and serial / parallel conversion of the write / read error information. And a second write / read control information conversion circuit for converting the write / read control information to the write / read circuit by serial / parallel conversion, and 2. The disk storage device according to claim 1, further comprising a second write / read error information conversion circuit for converting write / read error information into parallel / serial. 3. The first serial information for selecting the write / read control information, and / or the write / read error information, or the high-speed serial data in the write / read control circuit and transferring it in a serial format. A switching circuit, and a second serial information switching circuit for selecting the write / read control information, and / or the write / read error information, or the high-speed serial data for the write / read circuit and transferring the serial information. The disk storage device according to claim 1, further comprising: 4. The write / read circuit is configured to write / read only when a write / read error has occurred.
2. The disk storage device according to claim 1, further comprising a write / read error signal generation circuit for notifying a read control circuit.