JPH05236656A - Frequency-following method - Google Patents

Abstract

PURPOSE:To quicken an excessive response at the time of a sudden change of frequency by comparing the clock number of the inverter-driving frequency signal in one period of the frequency of integral times of the standard frequency of a three-phase AC power supply with that of the frequency of integral times of a frequency detected from the three-phase AC power supply, by detecting the difference between respective clock numbers and by feeding the difference forward to the inverter-driving frequency signal. CONSTITUTION:The clock number by the inverter-driving frequency signal fS; e.g. 614, 4KHz/300; in one period at the frequency, e.g. 300Hz, of integral times of the standard frequency of a three-phase AC power supply is 2048 and is previously set in up/down counters 8, 9. Then, the clock number is counted down in the counters 8, 9 by the clock number of the frequency signal fS in one period of the square-waved signal fCS of the frequency of integral times of the standard frequency detected and converted from the three-phase AC power supply. The difference between the counted- down number and the clock number 2048 and a polarity by the comparison of the two numbers are detected by logic circuits 11, 12 and the added or subtracted clock number based on a detected value is fed forward so that the frequency fS is addition- subtraction controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency follow-up method in an inverter control system which is interconnected with a commercial three-phase AC power supply.

[0002]

2. Description of the Related Art FIG. 4 is a block circuit diagram showing a structure of a phase difference detection circuit between a commercial three-phase AC power supply and an inverter driving frequency signal in an inverter which is interconnected with a commercial three-phase AC power supply according to the prior art. is there. In FIG. 4, a voltage signal 101 detected from a commercial three-phase AC power supply is converted into a zero-cross square wave 104 and input to a logic circuit 105. In addition, the sine wave signal 102 for driving the inverter is
It is converted into a square wave 103 having a 90 ° phase shift and input to the logic circuit 105. The logic circuit 105 is composed of two EX-NOR gates 117 and 118 and a NOT gate 119, inputs the square wave signals a and b shown in FIG. 5, and outputs a square wave d having opposite polarities. Output e. The two square waves d and e are input to the subtractor 106 via an integrator composed of a resistor 113 and a capacitor 115, and a resistor 114 and a capacitor 116, respectively. The subtractor 106 is an operational amplifier 109 and a resistor 1 connected to the non-inverting input terminal of the operational amplifier 109.
11 and 112 and a resistor 110 provided in the negative feedback circuit
The output signal f is an input signal d
And e. That is, when the phase difference between the zero-cross square wave a detected from the commercial three-phase AC power supply and the square wave b of the inverter driving sine wave signal is 90 °, the output signal f of the subtractor 106 becomes zero.

[0003]

Since the phase difference control circuit according to the prior art is composed of the above-mentioned phase difference detection circuit and the feedback circuit for the phase difference command, in order to improve the settling property, the phase difference compensation circuit is used. I couldn't increase the gain too much. Therefore, if the difference between the frequency on the inverter side and the frequency on the commercial power source side is large, there is a defect that tracking cannot be completed, and overshoot in tracking control easily occurs. In addition, since the feedback control method is used, the follow-up speed is unavoidably slow, and there is also the problem that the electric power supplied to the load from the inverter that is interconnected with the commercial power source fluctuates significantly when the frequency of the commercial power source fluctuates. It was The present invention has been made to solve the above-mentioned problems in the prior art, and an object of the present invention is to provide a frequency tracking method having a wide frequency tracking range and a fast transient response at the time of a sudden frequency change. Is.

[0004]

In order to achieve the above object, the frequency tracking method according to the present invention is an integral multiple of a standard frequency obtained by zero-cross conversion of a voltage signal detected from a three-phase AC power supply in which an inverter is interconnected. A square wave signal having a frequency of 1 is generated, and the number of clocks of the frequency signal for driving the inverter in one cycle of the frequency that is an integral multiple of the standard frequency of the three-phase AC power supply and the frequency detected from the three-phase AC power supply. Comparing with the number of clocks of the frequency signal for driving the inverter in one cycle of the frequency signal of an integral multiple,
The difference between two clock numbers and the polarity thereof (the polarity determined by the magnitude of the relative comparison) are detected, and the detected value is fed forward to the frequency signal for driving the inverter, and the frequency is added / subtracted to control.

[0005]

[Action] When the frequency of the three-phase AC power supply is reduced, one period of the frequency signals f _CS integer multiple of the standard frequency (e.g., 6 times) increases. Therefore, the frequency signal f _S (for example, 6
The number of clocks (14.4 KHz) is 1 of the frequency (for example, 300 Hz) that is an integral multiple (for example, 6 times) of the frequency of the three-phase AC power supply.
It is larger than the number of clocks in the cycle. Further, when the frequency of the three-phase AC power supply rises, the number of clocks counted in one cycle thereof decreases conversely. 1 at a frequency that is an integral multiple of the standard frequency of a three-phase AC power supply (for example, 300 Hz)
The number of clocks by the frequency signal f _S for driving the inverter of the cycle is set to 2,048 (614.4 KHz / 300) in the up / down counter in advance, and is an integral multiple of the standard frequency detected and converted from the three-phase AC power supply. (Eg 6
The up / down counter counts down by the number of clocks of the frequency signal f _S for driving the inverter in one cycle of the square wave signal f _{CS having} a frequency of double the frequency. The difference between this down count number and 2,048 set in advance and the polarity ("H" when the down count number is larger than 2,048, "L" when the down count number is smaller) are detected, and this detection is performed. Feed-forwarding the number of addition clocks or the number of subtraction clocks based on the value to add / subtract the frequency f _S for driving the inverter.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of a frequency tracking method according to the present invention. In FIG. 1, the voltage signal detected from the commercial three-phase AC power source is converted into f _CS (for example, 300 Hz ± 18 Hz) in the zero-crossing square wave generation circuit 1 and input to the shift register 3 and the shift register 4 via the shift register 3. To enter. The outputs of the two shift registers 3 and 4 are input to the flip-flops 5 and 6 via NOT gates 30 and 31, respectively, and to the two up / down counters 8 and 9 via the logic circuit 7. The logic circuit 7 is composed of six AND gates 32 to 37 and two NOT gates 38 and 39, and the output signals A and B of the shift registers 3 and 4 are the same as those of FIG. The waveform is as shown in the timing chart.

In FIG. 2, a signal M, which is the logical product of the signal A and the output signal E of the flip-flop 5, becomes the RESET signal of the up / down counter 9, and the logical product of the signal B and the output signal F of the flip-flop 5. Signal N is N
The signal becomes O through the OT gate 38 and becomes the LOAD signal of the up / down counter 9. Also, signal A and signal F
The signal I which is the logical product of R and R of the up / down counter 8
It becomes the ESET signal, and the signal J, which is the logical product of the signal B and the signal E, becomes the signal K through the NOT gate 39 and goes up.
It becomes the LOAD signal of the down counter 8. Further, a signal L which is a logical product of the signal C, the signal E and the output signal G of the flip-flop 4 is a latch output timing square wave and is input to the AND gate 14 in the output signal circuit of the up / down counter 9. At the same time, it is input to the AND gate 51 which controls the number of clocks of the signal f _S sent from the inverter driving frequency oscillation circuit 2 to the up / down counter 8 via the NOT gate 50. Signal C,
A signal P which is a logical product of the signal F and the output signal H of the flip-flop 4 is a latch output timing square wave, and is AND in the output signal circuit of the up / down counter 8.
It is input to the gate 13 and also to the AND gate 52, and the frequency oscillating circuit 2 for driving the inverter outputs NOT.
It controls the number of clocks of the signal f _S sent to the up / down counter 9 via the gate 50.

The two up / down counters 8 and 9 set the PRESET state to the count set value 2,048 by the LOAD signals K and O, respectively, and start down counting. When f _CS from the three-phase AC power supply is 300 Hz, the frequency signal f _S for driving the inverter (614.4K
Since the number of clocks counted in (Hz) is 2,048, the number of clocks output from the up / down counters 8 and 9 is 0. The logic circuit 11 is composed of two AND gates 41 and 42, an OR gate 43, and a NOT gate 40. The polarity of the output signal of the OR gate 43, which is the output signal of the logic circuit 11, has the polarity of the up / down counter 8. It changes depending on the combination of the polarities of the output terminals Q ₁ and Q ₃ . That is, Q ₁ is “H” and Q ₃ is “L”
(F _CS is higher than 300 Hz and the down count number by f _S is smaller than 2,048), or Q ₁ is “L” and Q ₃ is “H” (f _CS is lower than 300 Hz and the down count number by f _{S is} Is larger than 2,048), the output signal of the OR gate 43 in the logic circuit 11 becomes "H". Output terminals Q ₁ and Q of the logic circuit 12 and the up / down counter 9
The polarities of ₃ are exactly the same.

Next, a frequency square wave signal f _CS that is an integral multiple (for example, 6 times) of the standard frequency is input from the three-phase AC power supply, and the frequency f for driving the inverter is corresponding to this frequency.
A method of controlling _S will be described. When the frequency square wave signal f _{CS that} is an integral multiple (for example, 6 times) of the standard frequency is input to the shift register 3, the shift register 3 outputs the signal A, and the shift register 4 outputs the signal with one pulse delay. B is output. These two signals A and B are input to the logic circuit 7 through the flip-flops 5 and 6,
As shown in FIG. 5, signals K, I, L for controlling the up / down counter 8 and signals O, M, P for controlling the up / down counter 9 are output. Of the above signals, the signals L and P are both latch timing square waves, and are output with a delay of one cycle. This signal L is input to the AND gate 14 together with the output signal Q ₁ of the up / down counter 9 and the output signal (d) of the addition / subtraction clock generator 10, and the polarities of the output signals Q ₁ and Q ₃ of the up / down counter 9 are input. In response to this, an addition / subtraction clock is sent out via AND gates 17 and 18 and OR gates 19 and 20. Further, as the signal L, a frequency signal f _S for driving an inverter (for example, 614.4 KHz) is inputted to the up / down counter 8 via the AND gate 51, and f _{S is produced} only during the pulse width period of the signal L by the LOAD signal K. To count down. That is, the signal L counts down the up / down counter 8 and outputs the down-count result in the up / down counter 9. The signal P is a latch output timing square wave that is output one cycle later than the signal L, and causes the up / down counter 9 to down-count and outputs the down-count result in the up / down counter 8.

The up / down counter 8 or 9
Of the output signal Q ₁ of "H" and Q ₃ of "L"
The addition / subtraction clock output from the D gate 21 or 14 is supplied to the OR gate 19 via the AND gate 15 or 17.
To output the addition clock. Also, the output signal Q ₁
Is "L" and Q ₃ is "H", the addition / subtraction clock output via the AND gate 21 or 14 outputs the subtraction clock from the OR gate 20 via the AND gate 16 or 18.

As described above, since the up / down counters 8 and 9 alternately output the results of down-counting and down-counting, as shown in FIG. 3, a frequency signal that is an integral multiple of the frequency of the three-phase AC power supply is used. f _CS (eg 300 ± 1
8) The feedforward control is _{performed so} that the period T _1NV of the frequency f _1NV for driving the inverter follows with a delay of one period from the period T _CS of Hz, and the frequency following response time is significantly shortened (for example, 150 ms) according to the conventional technique (for example, 150 ms). 5-
6 ms).

[0013]

As described above, in the frequency tracking method according to the present invention, in one cycle of a square wave signal having a frequency that is an integral multiple (for example, 6 times) of the frequency converted from the three-phase AC power supply in which the inverter is interconnected. The number of clocks by the frequency signal for driving the inverter is compared with the number of clocks by the frequency for driving the inverter in one cycle of a frequency that is an integral multiple (for example, 6 times) of the frequency of the three-phase AC power supply, and the difference is detected. Then, the signal is forwarded to the frequency signal for driving the inverter. Therefore, not only the transient response at the time of sudden frequency change becomes faster, but also the frequency variable width becomes wider and the power control of the inverter becomes more stable.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a digital frequency value tracking method according to the present invention.

FIG. 2 is a timing chart of signal waveforms in the frequency tracking method according to the present invention.

FIG. 3 is a timing chart showing frequency response time.

FIG. 4 is a block circuit diagram of a phase difference detection circuit according to a conventional technique.

FIG. 5 is a timing chart of signal waveforms in a phase difference detection circuit according to the related art.

[Explanation of symbols]

 1 Zero Cross Square Wave Generation Circuit 2 Inverter Frequency Oscillation Circuit 3, 4 Shift Register 5, 6 Flip Flop 7, 11, 12, 13 Logic Circuit 8, 9 Up / Down Counter 10 Addition / Subtraction Clock Generation Unit

Claims (1)

[Claims] 1. A frequency tracking method in an inverter control system for interconnecting an inverter by causing a frequency to follow a three-phase AC power supply, wherein a voltage signal detected from the three-phase AC power supply is zero-crossed and then an integer of a standard frequency. A square wave signal having a doubled frequency is generated in advance, and the number of clocks counted by the inverter drive frequency signal in one cycle of the frequency signal that is an integral multiple of the standard frequency of the three-phase AC power supply and the three-phase AC power supply are detected. The number of clocks counted by the inverter drive frequency signal in one cycle of the frequency signal that is an integer multiple of the standard frequency is compared, and the difference (absolute value) between the two clocks and its polarity (clock number as a reference, "H" is detected when it is greater than the clock, and "L" when it is less than the clock, and addition based on this detection signal is performed. Frequency tracking wherein the feedforward number number of locks or subtracting clock to the inverter driving frequency signal.