JPH05236399A - Field double-speed converter circuit - Google Patents

Abstract

PURPOSE:To provide the field double-speed converter circuit for reducing the large-area field flicker of a television receiver. CONSTITUTION:An interpolating field-generating circuit 20 generates a scanning signal which interpolates the scanning signals of a real field interlaced at 2:1 from the scanning signal of the real field. Then, a signal density doubling circuit 30 generates a 4:1 interlaced scanning signal with a combination of the real field and interpolating field, and shortens the scanning time and doubles the scanning speed. Further, the number of fields constituting one frame of an input signal and the number of scans are doubled, so the large-area field flicker is reduced without decreasing the vertical resolution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing of a television receiver, and more particularly to a field double speed conversion circuit for reducing large area flicker in a field.

[0002]

2. Description of the Related Art FIG. 6 shows the principle of interlaced scanning. Generally, in a television receiver, one screen (one frame) is divided into two fields and displayed by 2: 1 interlace scanning. In the figure, the horizontal axis and the vertical axis respectively represent the horizontal and vertical directions of the television screen. First, in the first field at the beginning, scanning is performed in the order of A1 → A2 → A3 → A4 → as shown by the solid line,
In the next second field, B1 → B2 as indicated by the broken line
The scanning is performed in the order of → B3 → B4 → B5 → so as to fill the space between the previous field scans.

FIG. 7 shows the vertical spatial position of the scanning signal in each field when the field period (time) is taken on the horizontal axis. The odd (first and third) fields and the even (second) field are shown. , 4) field, the scanning signals are in an offset relationship with each other as shown in FIG.

By the way, the PAL television transmission system uses 2: 1 interlaced scanning and has 625 scanning lines.
The field frequency is defined as 50 Hz. On the other hand, the television transmission system of NTSC is the same interlaced scanning as the PAL system, and the number of scanning lines is 525 and the field frequency is 60 Hz. Comparing the two television transmission systems, PAL has a field frequency lower than that of NTSC by only 10 Hz, so that a large area flicker of the field occurs in the reproduced video.

As a specific measure for reducing such flicker, it has been proposed to double the number of fields of an input video signal for display.

This processing is called field doubling, and generally a circuit configuration as shown in FIG. 8 is adopted. In the figure, first, the composite PAL signal is converted into an ADC (Analog to D
igitalConverter) 80 to convert to a digital signal. The digitized composite PAL signal is input to the YC separation circuit 81 and separated into a luminance signal Y and a carrier color signal C. Of these signals, the C signal is further input to the demodulation circuit 82 and demodulated into baseband color difference signals (u, v). Next, the separated Y signal and the demodulated u signal and v signal are input to the field double speed conversion circuit 83.

In this case, first, the number of fields is doubled, so that fields are interpolated in order to compensate for the insufficient fields. Secondly, while writing the input field signal and the interpolation field signal in the field memory,
The scanning time of the signal written in the field memory is 1 /
Compress for 2 hours. Thirdly, the data is read from the field memory at a scanning speed twice as high as the writing speed. Through the above processing, double speed signals Y ', u', v'are obtained. Since the field double speed conversion process is different between a still image and a moving image, the motion detection circuit 84 obtains motion information and switches signal processing.

Thereafter, the doubled Y ', u', and v'signals are converted into a DAC (Digital to Analog Converter).
At 85, it is converted back to an analog signal, and the matrix circuit 86
To R, green G and blue B output signals. As a matter of course, as the speed of the video signal is increased, the horizontal and vertical synchronization signals also need to be doubled.

The field doubling process in the above-mentioned signal processing is a system in which a virtual field is provided between fields of an input video signal and the number of fields is doubled and displayed. If the added virtual (interpolation) field image is not appropriate, the image quality is degraded. Therefore, the field interpolation processing is important in the field double speed conversion.

A technique related to the field doubling process is described in the document SMP IT; Journal, Volume 92, No. 5 (May 1983), page 552.
From page 561 (SMPTE, Journal, Vol.92, N
o. 5 (May 1983), pp, 552-561). Next, the processing algorithm of the field double speed technology described in the above document will be described.

According to the description, the processing algorithm differs depending on whether the video to be handled is a still image or a moving image. FIG. 9 shows a method for generating a field double speed signal in a still image, and shows a temporal and spatial positional relationship between an input field scan signal and an output field double speed scan signal. In order to obtain such a double-speed field output format, the input field signal is temporarily stored in the field memory, the scanning time is compressed to 1/2, and
The same signal is output twice from the field memory at a double scanning speed with a time shift. For example, in the figure, the input field signal (B2 →
B3 → B4 →) is the field number 4 (b2 → b3 → b
4 →) and field number 6 (b2 ′ → b3 ′ → b4 ′)
→) form two output field signals corresponding to
However, the signal speed output from the field memory is
It is twice the scanning speed of the input signal. By performing the above field double speed conversion, the number of fields is doubled (10
0 Hz), so that large area flicker is reduced.

On the other hand, when the above-mentioned speed-up processing algorithm is applied to a moving image, an output field (time axis) inversion phenomenon occurs. For example, in FIG. 9, the signal of the field number 6 is output later than the signal of the field number 5 in time, but the signal of the field number 6 is exactly the same as the signal of the field number 4, so that the displayed time is Contradiction occurs.

Therefore, in the case of a moving image, field double speed processing as shown in FIG. 10 is performed. That is, two continuous field scan signals having an interlace relationship are generated from one input field scan signal.
For example, an output (double speed) scanning signal of field numbers 1 and 2 is formed from an input scanning signal of field number 1, and an output scanning signal of field numbers 3 and 4 is generated from an input scanning signal of field number 3. In the same manner, the output double speed scanning signal is generated. Further, as shown in the figure, the output double speed scanning signal generated is synthesized by giving a specific gravity of 3: 1 from two continuous scanning signals. In the field doubling process for such a moving image, the time axis inversion phenomenon does not occur unlike the field doubling process for a still image.

Therefore, if the motion information of the image is detected from the televised television signal and the field double speed processing is switched for the moving part and the stationary part,
Appropriate signal processing is performed on still images and moving images to reduce large area flicker in the field.

[0015]

The above-mentioned two field doubling processings, that is, the field doubling processings for a still image and a moving image, are different in processing algorithm for generating a signal of an interpolated field. This requires a processing circuit (hardware), resulting in an increase in circuit scale.

In the field doubling process, since the position of the center of gravity of the scanning signal is different between the still region and the moving region of the image, when the field doubling process is switched according to the motion information of the image, the still region and the moving region are switched. The image becomes unnatural at the border of.

Since the field doubling process is switched according to the motion information of the image, there is a risk that the image quality will be broken if an error occurs in the motion detection.

Since the vertical resolution in the moving area of the image is lower than the vertical resolution before the field doubling process, the difference in image quality between the still area and the moving area is large, and when the moving area exists, the entire image deteriorates. Give the impression that

An object of the present invention is to provide a field double speed conversion circuit capable of further improving the image quality in the field double speed processing for reducing the large area flicker of the field.

[0020]

In order to solve the above-mentioned problems, the present invention uses a 2: 1 interlaced scan in which an image of one frame is composed of a first real field signal and a second real field signal. By adding the first interpolation field signal and the second interpolation field signal to the input signal, one frame is composed of four fields 4:
1 interlaced scanning field double speed signal is converted. Here, the scan signal of the first interpolation field is scanned so as to fill the middle of the scan signal of the first real field and the scan signal of the second real field that are continuous. The scanning signal of the second interpolation field scans so as to fill the middle of the scanning signal of the second actual field and the scanning signal of the first actual field that are continuous.

The processing circuits for obtaining the first and second interpolated field scanning signals are performed by the same circuit regardless of the still image and the moving image. The scanning signal of the first interpolation field is generated by weighted addition of 3: 1 while selecting signals of two consecutive lines from the first real field signal, and the second interpolation field signal is generated by the second interpolation field signal. It is generated by weighted addition of 3: 1 while selecting signals of two consecutive lines from two real field signals.

The image constitutes one frame in the order of the first real field → the first interpolation field → the second real field → the second interpolation field, and the scanning time of each field is halved. And the display is performed at the field double speed which is double the scanning speed.

[0023]

The two (first and second) real field images are scanned so that the one frame image formed by the 2: 1 interlaced scanning is further filled in the middle (first and second). ) Add interpolated field image,
The number of scanning lines is doubled by performing field doubling for interlaced display of 1 frame at 4: 1 and at least the vertical resolution of the input scanning signal is preserved, so that the vertical resolution of the moving image is lowered. There is no. As a result, there is no great gap in the image quality difference between the still image and the moving image.

The scanning signals of the first and second interpolation fields are generated by the same signal processing from the immediately preceding first and second actual field scanning signals, regardless of the moving image and the still image. No motion detection circuit is required, and the center of gravity does not deviate depending on the type of image. The circuit scale is also reduced because the same circuit is used.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an embodiment showing a field double speed conversion circuit according to the present invention. To explain this, further refer to FIGS. 2, 3, 4 and 5, together with the algorithm of the present invention. The details will be described.

First, in FIG. 1, the signal applied to the input terminal 10 is Y, separated from the composite signal.
These are u and v signals, both of which are 2: 1 interlaced signals described in the prior art (FIGS. 6 and 7). Here, the field formed by scanning the input signal will be referred to as "actual field".

As shown in FIG. 2, in order to double the number of fields, the actual field images (A, B, C,
...) is provided with an interpolated field image (a, b, c, ...) Filling the middle thereof, and the scanning time of the image signal of the real field and the image signal of the interpolated field is time-compressed to 1/2 and doubled This can be achieved by converting the scanning speed to.

However, if an interpolated field image is simply inserted between real field images satisfying the 2: 1 interlaced scanning relationship, the 2: 1 interlaced relationship will be broken. In order to satisfy the 2: 1 interlace relationship, not only the interpolated field image but also the actual field image need to be signal-processed according to the motion, which causes a problem as in the prior art.

Therefore, as shown in FIG. 3, if an interpolated field image signal that becomes a 4: 1 interlaced scanning signal in which one frame is composed of four fields is obtained and inserted, the input real field image is time-compressed. However, by doubling the scanning speed, the actual field image can be used as it is, and the input information is not damaged.

Next, a method of generating an interpolated field image signal to form the 4: 1 interlaced scan will be described. FIG. 4 is a diagram showing a method of generating a scanning signal of an interpolation field. In the figure, the circles and the squares show the scanning signals of the actual field, and the circles and the squares filled with diagonal lines show the scanning signals of the interpolation field. Now, paying attention to the case where the scanning signal of the field number 2 is generated, the scanning signals an forming this field are all scanning signals An and An + of the immediately preceding actual field (field number 1) regardless of the motion information of the image.
1 (n represents the scan number of the scan signal forming the field). For example, the scanning signal a
1 is obtained by giving a specific gravity of 3: 1 to two consecutive scanning signals A1 and A2 in the previous field and adding them. That is, a1 = (3 · A1 + A2) / 4 (1) Hereinafter, similarly, the scanning signal an of the interpolation field
Is calculated by an = (3 · An + An + 1) / 4 (2). Here, regarding the center of gravity of the scanning signal, since the scanning signal an of the interpolation field obtained by the equation (2) is formed by weighted addition of 3: 1, as shown in FIG. Scanning signal An
On the other hand, it can be seen that the center of gravity shifts to the position offset by H / 1250 (H: image height) in the vertical scanning direction.

Next, paying attention to the case where the scanning signal bn of the field number 4 (interpolation field) is generated, the scanning signal bn of the interpolation field is the same as the case where the scanning signal an of the field number 2 is obtained. All are formed from the scan signal of the immediately preceding real field signal (field number 3) regardless of the motion information. In other words, it is obtained by giving a specific gravity of 3: 1 to two continuous scanning signals Bn and Bn + 1 and adding them.
That is, bn = (3 · Bn + Bn + 1) / 4 (3) Here, regarding the center of gravity of the scanning signal, since the scanning signal bn of the interpolation field obtained by the equation (3) is formed by weighted addition of 3: 1, as shown in FIG. Scanning signal Bn
On the other hand, it can be seen that the center of gravity shifts to the position offset by H / 1250 (H: image height) in the vertical scanning direction.

On the other hand, since the scanning signal An of the field number 1 and the scanning signal Bn of the field number 3 have a 2: 1 interlace relationship, the center of gravity of the scanning signal Bn is H / in the vertical scanning direction with respect to the scanning signal An. The position is offset by 625 (H: image height).

From the above, the image information between the scanning signals An and An + 1 of the field number 1 is 3 of the scanning signal an of the field number 2, the scanning signal Bn of the field number 3 and the scanning signal bn of the field number 4. It is supplemented by the field scan signal. This means that one frame is composed of 4 fields, and the 4: 1 interlace relationship is satisfied. Further, regarding the number of scanning lines, the scanning signals an and bn of the interpolation field
Scans so as to fill the middle of the scan signals An and Bn of the actual field which is originally interlaced 2: 1. Therefore, the number of scanning lines composing one frame is inevitably twice as many as the input signal (1250 lines).

FIG. 1 shows the configuration of a processing circuit that implements the algorithm described above. That is, the signal applied to the input terminal 10 is stored in the first field memory 31 of the signal doubling circuit 30 as the scanning signal R of the actual field. At the same time, part of the input signal R for generating the scanning signal of the interpolation field is input to the interpolation field generation circuit 20. The interpolation field generation circuit 20 is composed of a 312 line delay circuit 21, a 1 line delay circuit 22, coefficient units 23 and 24, and an adder 25.

In order to obtain the image signal of the interpolated field according to the above-mentioned algorithm, first, the input signal R is passed through the 312 line delay circuit 21 to be delayed by 312 lines. The delayed signal is Rd1. A part of the delay signal Rd1 is added to the 1-line delay circuit 22,
Further, it is delayed by one line. As a result, the delay circuit 2
At the output of 2, a signal Rd2 obtained by delaying the input signal R by 313 lines is obtained. Next, the delayed signal Rd1 is passed through the coefficient unit 23 to be multiplied by 1/4, and the delayed signal Rd2 is passed through the coefficient unit 24 to be multiplied by 3/4. Here, in order to form the scan signal I of the target interpolation field, the two delay signals output from the coefficient units 23 and 24 may be combined by the adder 25. That is, I = (3 · Rd2 + Rd1) / 4 (4) Here, the expression (4) corresponds to the expressions (2) and (3). The interpolation field signal I generated by the interpolation field generation circuit 20 in this manner is stored in the second field memory 32 of the signal doubling circuit 30.

The signal doubling circuit 30 doubles the number of fields by supplementing the scanning signal R of the real field with the scanning signal I of the interpolating field to increase the scanning time by one.
It is a circuit for obtaining the field double speed signal X by time-compressing to / 2 and further converting the scanning speed of the time-compressed scanning signal to double. The signal doubling circuit 30 is composed of two field memories 31 and 32, a selector 33 for switching the outputs of the field memories, and a memory control circuit 34 for controlling these.

The field double speed signal X is a writing speed WCLK when storing the actual field scanning signal R and the interpolating field scanning signal I in the corresponding field memories 31 and 32, and a reading speed when outputting from the field memory. It can be obtained by controlling RCLK and the timing of writing and reading. Now, the writing speed when the scanning signal is stored in the field memories 31 and 32 is set to the sampling speed of the input signal, for example, 4 fsc (fsc
When the signals are read from the field memories 31 and 32, they are read at a speed of 8 fsc in order to double the number of fields. That is, writing to the real field memory and the interpolation field memory is started at the same time and completed in 0.02 seconds, and reading from the field memory reads all the real field memory signals R ′ in the first 0.01 seconds. In the next 0.01 seconds, all the memory signals I'in the interpolation field are read out. These field memory output signals are guided to the output terminal 40 by switching the selector 33 by the control signal CTRL of the memory control circuit 34.

FIG. 5 shows a manner of field densification by the time compression and the double speed reading described above. In the figure, the R signal is a real field signal before time compression, the single rectangle A shows the first real field signal, and the double rectangle B shows the second real field signal. The I signal is the interpolated field signal before time compression, the hatched rectangle a is the first interpolated field signal, and the grid rectangle b is the second.
2 shows the interpolated field signal of On the other hand, the X signal is a field double speed signal, which is a signal obtained by combining the R and I signals after time compression. Here, the time-compressed real field signals A '(first) and B' (second) and the interpolated field signals are shown by a '(first) and b' (second). The time-compressed field signal is A ′ → a ′ →
B ′ → b ′ → are output in this order, and this is repeated. Naturally, one frame is composed of four fields of A ', a', B ', and b', and each field has a 4: 1 interlace relationship as described with reference to FIG.

The processing circuit described above can form a field-doubled signal in which the number of fields of the input signal is doubled. Therefore, by displaying this, field flicker of a large area can be reduced.

Since there are three component signals, Y, u, and v, the above-mentioned field doubling processing circuit is provided in three systems.

In this embodiment, only the PAL signal has been described, but it is possible to increase the number of fields from 60 to 120 for the NTSC signal as well by the same algorithm as PAL.

[0042]

According to the present invention, the number of fields is doubled for signal display while successively adding images for two fields to one frame of an input video signal by interpolation processing. Large area field flicker is reduced. Further, since the signal of the interpolation field is generated without using the motion information of the image (still image and moving image are generated by the same algorithm), the motion detection circuit is not required and the circuit scale can be reduced. Further, since the number of scans forming one frame is twice as many as the input signal and the image is displayed with 4: 1 interlace, the difference in image quality between the still image and the moving image is alleviated from the viewpoint of vertical resolution.

[Brief description of drawings]

FIG. 1 is a block diagram of a field double speed conversion circuit according to the present invention.

FIG. 2 is a principle diagram of field double speed.

FIG. 3 is a principle diagram of 4: 1 interlaced scanning.

FIG. 4 is an explanatory diagram showing a method of generating an interpolation field signal.

FIG. 5 is an explanatory diagram showing a 4: 1 interlaced field double speed output method by time compression.

FIG. 6 is a principle diagram of 2: 1 interlaced scanning.

FIG. 7 is an explanatory diagram showing a vertical spatial position of a 2: 1 interlaced scanning signal.

FIG. 8 is a block diagram of a circuit capable of reducing flicker.

FIG. 9 is an explanatory diagram showing a conventional method for generating a field-doubled signal in a still image.

FIG. 10 is an explanatory diagram showing a conventional method for generating a field-doubled signal in a moving image.

[Explanation of symbols]

10 ... Input terminal, 20 ... Interpolation field generation circuit, 21
... 312 line delay circuit, 22 ... 1 line delay circuit, 2
3, 24 ... Coefficient unit, 31, 32 ... Field memory, 3
3 ... Selector, 34 ... Memory control circuit, 40 ... Output terminal, 80 ... Analog-digital converter.

Claims (2)

[Claims] 1. A system for doubling the number of fields of a video signal which is interlaced scanned at a ratio of 2: 1,
To obtain the scanning signals of the first and second interpolation fields for scanning the scanning signals of the first and second actual fields which are interlaced scanned at 2: 1 and further to fill the middle of the scanning. To form one frame from a total of four fields, and the output of the four fields is the first real field, the first interpolation field, and the second field.
Are repeated in the order of the real field and the second interpolation field, and the scanning time of the first and second real fields and the first and second interpolation fields is compressed by 1/2 to input scan. A field double speed conversion circuit characterized by displaying at twice the scanning speed of the above. 2. A first delay means for delaying an input signal by a scanning period of 312 lines, and a second delay means for delaying an output signal of the first delay means by a scanning period of 1 line. A delay unit, wherein the output signal of the first delay unit is multiplied by a coefficient of 1/4, and the output signal of the second delay unit is multiplied by a coefficient of 3/4 to obtain the first and second delay units. And adding the delay signals of 1 to 2 to generate the scanning signals of the first and second interpolation fields.