JPH0523551B2 - - Google Patents

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Publication number
JPH0523551B2
JPH0523551B2 JP60104338A JP10433885A JPH0523551B2 JP H0523551 B2 JPH0523551 B2 JP H0523551B2 JP 60104338 A JP60104338 A JP 60104338A JP 10433885 A JP10433885 A JP 10433885A JP H0523551 B2 JPH0523551 B2 JP H0523551B2
Authority
JP
Japan
Prior art keywords
signal
circuit
output
pixel
absolute value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60104338A
Other languages
Japanese (ja)
Other versions
JPS61260772A (en
Inventor
Hiroaki Sugiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60104338A priority Critical patent/JPS61260772A/en
Publication of JPS61260772A publication Critical patent/JPS61260772A/en
Publication of JPH0523551B2 publication Critical patent/JPH0523551B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、画像中の欠陥を有する画素信号を
補償する画像欠陥補償装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image defect compensation device that compensates for pixel signals having defects in an image.

[従来の技術] この種の従来装置は、テレビジヨン学会技術報
告VOL.7,No.14の19ページから24ページに示さ
れるものがあり、これを第3図に示す。この第3
図に従来装置の全体回路ブロツク図を示し、同図
において画像欠陥補償装置は、撮像素子の画像欠
陥補償装置であり、1は対象物を映像として入力
し、該映像を信号に変換する撮像部、2は該撮像
部1にて出力される信号を保持するクランプ回
路、3は乗算回路、4は加算回路、5は反転回
路、6は遅延回路、7は乗算回路、8は欠陥補償
信号発生回路である。3A,3Bは乗算回路3の
入力端子を示し、7A,7Bは乗算回路7の入力
端子を示す。
[Prior Art] A conventional device of this type is shown on pages 19 to 24 of the Technical Report of the Television Society of Japan, Vol. 7, No. 14, and is shown in FIG. This third
The figure shows an overall circuit block diagram of a conventional device. In the figure, the image defect compensating device is an image defect compensating device of an image sensor, and 1 is an image capturing unit that inputs an object as an image and converts the image into a signal. , 2 is a clamp circuit that holds the signal output from the imaging unit 1, 3 is a multiplication circuit, 4 is an addition circuit, 5 is an inversion circuit, 6 is a delay circuit, 7 is a multiplication circuit, and 8 is a defect compensation signal generation It is a circuit. 3A and 3B indicate input terminals of the multiplication circuit 3, and 7A and 7B indicate input terminals of the multiplication circuit 7.

上記構成に基づく従来装置の動作について、上
記第3図及び第4図の動作の説明用線図に基づい
て説明する。撮像部1の信号出力の0レベルがク
ランプ回路2により電位Eにクランプされる。こ
れを第4図に示す。第4図はフイルタの配列
を示すもので、Wは全色透過フイルタ、Gは緑色
透過フイルタを示す。第4図に示す信号は第4
図に示すフイルタ配列に対応するものである。
第4図に示す信号が遅延回路6に入力されると
第4図に示す信号が出力される。乗算回路3は
入力端子3Aがローレベルの状態ではクランプ電
位Eが出力され、ハイレベルの状態では入力端子
3Bの信号を出力するように動作する。乗算回路
7は入力端子7Aがローレベルの状態ではクラン
プ電位Eが出力され、ハイレベルの状態では入力
端子7Bの信号を出力するように動作する。第4
図に示す如くn番目の信号が欠陥画素による信
号であるとする。またそれに対応して欠陥補償信
号発生回路8の出力である欠陥補償信号を第4図
に示す。
The operation of the conventional device based on the above configuration will be explained based on the diagrams for explaining the operation shown in FIGS. 3 and 4. The 0 level of the signal output from the imaging section 1 is clamped to the potential E by the clamp circuit 2. This is shown in FIG. FIG. 4 shows the arrangement of filters, where W indicates an all-color transmitting filter and G indicates a green transmitting filter. The signal shown in Figure 4 is
This corresponds to the filter arrangement shown in the figure.
When the signal shown in FIG. 4 is input to the delay circuit 6, the signal shown in FIG. 4 is output. The multiplier circuit 3 operates to output the clamp potential E when the input terminal 3A is at a low level, and outputs the signal from the input terminal 3B when the input terminal 3A is at a high level. The multiplier circuit 7 operates so that the clamp potential E is output when the input terminal 7A is at a low level, and the signal from the input terminal 7B is output when the input terminal 7A is at a high level. Fourth
As shown in the figure, it is assumed that the nth signal is a signal due to a defective pixel. Correspondingly, a defect compensation signal output from the defect compensation signal generation circuit 8 is shown in FIG.

ところで乗算回路3の入力端子3Aには反転回
路5により第4図に示す欠陥補償信号の反転が
入力されるのでその出力は、第4図に示す信号
になる。乗算回路7の入力端子7Aには第4図
に示す欠陥補償信号が入力されるのでその出力
は、第4図に示す信号になる。加算回路4の出
力は欠陥補償信号がローレベルの状態では第4図
に示すクランプ回路2の出力信号を出力し、ハ
イレベルの状態では第4図に示す遅延回路6の
出力信号を出力する。以上の動作により第4図
に示すようにn番目の欠陥画素による信号がn−
2番目の画素の信号に置換される。この画像欠陥
補償装置は、画像の相関性により接近した画素の
信号はほぼ同じ値であるという原理に基づいてい
る。
Incidentally, since the inversion of the defect compensation signal shown in FIG. 4 is input by the inversion circuit 5 to the input terminal 3A of the multiplication circuit 3, the output becomes the signal shown in FIG. Since the defect compensation signal shown in FIG. 4 is input to the input terminal 7A of the multiplication circuit 7, the output thereof becomes the signal shown in FIG. When the defect compensation signal is at a low level, the adder circuit 4 outputs the output signal of the clamp circuit 2 shown in FIG. 4, and when the defect compensation signal is at a high level, it outputs the output signal of the delay circuit 6 shown in FIG. As a result of the above operations, the signal from the n-th defective pixel is changed to n- as shown in FIG.
It is replaced with the signal of the second pixel. This image defect compensation device is based on the principle that signals of pixels that are close to each other have approximately the same value due to the correlation of images.

なお、欠陥補償信号発生回路8内には記憶装置
が含まれ欠陥画素の位置を予め記憶しておりそれ
に基づき欠陥補償信号を発生するものである。
The defect compensation signal generation circuit 8 includes a storage device, stores the position of a defective pixel in advance, and generates a defect compensation signal based on the position of the defective pixel.

[発明が解決しようとする問題点] 従来の画像欠陥補償装置は以上のように構成さ
れているので画像が急俊に変化している場合、そ
の変化の方向によつては補償誤差が大きくなり、
有効に欠陥画素を補償ができないという問題点が
あつた。
[Problems to be Solved by the Invention] Since the conventional image defect compensation device is configured as described above, when the image changes rapidly, the compensation error becomes large depending on the direction of the change. ,
There was a problem that defective pixels could not be effectively compensated for.

この発明は、上記のような問題点を解決するた
めになされたもので、画像欠陥補償装置におい
て、補償誤差を小さくすることにより、より高精
度に欠陥画素信号を補償することを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to compensate for defective pixel signals with higher accuracy by reducing compensation errors in an image defect compensation device.

[問題点を解決するための手段] この発明に係る画像欠陥補償装置は、正方格子
状に配設された複数の撮像素子から出力される画
素信号の中から、欠陥画像信号を垂直方向、水平
方向および斜め方向にそれぞれ挟む2つの画素信
号間ごとの差の絶対値を演算し、絶対値信号を出
力する絶対値演算手段と、絶対値信号の中で最も
小さい値を与える2つの画素信号を検出する最小
差検出手段と、最小差検出手段により検出された
2つの画素信号について平均値演算を行ない、平
均値信号を出力する平均値演算手段と、欠陥画素
信号を平均値信号で置換する置換手段とを含む。
[Means for Solving the Problems] The image defect compensation device according to the present invention converts defective image signals vertically and horizontally from pixel signals output from a plurality of image sensors arranged in a square grid. Absolute value calculation means for calculating the absolute value of the difference between two pixel signals sandwiched in the direction and the diagonal direction and outputting an absolute value signal, and two pixel signals that give the smallest value among the absolute value signals. A minimum difference detection means for detecting, an average value calculation means for performing an average value calculation on two pixel signals detected by the minimum difference detection means and outputting an average value signal, and a replacement for replacing a defective pixel signal with an average value signal. means.

[作用] この発明における画像欠陥補償装置では、絶対
値演算手段が、欠陥画素信号を垂直方向、水平方
向および斜め方向にそれぞれ挟む2つの画素信号
間ごとに差の絶対値が演算され、得られた絶対値
信号の中で最も小さい値を与える2つの画素信号
が最小差検出手段により検出される。2つの画素
信号についての平均値信号が平均値演算手段によ
り演算され、置換手段が欠陥画素信号を平均値信
号で置換する。最小差検出手段により、画素信号
レベルの差が最も小さい2つの画素信号が検出さ
れ、その平均値を用いて欠陥画素信号が置換され
るので、高精度に欠陥画素信号を補償できる。ま
た、欠陥画素の斜め方向についても考慮がなされ
ているので、より高精度に欠陥画素信号を補償で
きる。
[Function] In the image defect compensation device according to the present invention, the absolute value calculation means calculates and obtains the absolute value of the difference between two pixel signals that sandwich the defective pixel signal in the vertical direction, horizontal direction, and diagonal direction. Two pixel signals giving the smallest value among the absolute value signals are detected by the minimum difference detection means. An average value signal for the two pixel signals is calculated by the average value calculation means, and a replacement means replaces the defective pixel signal with the average value signal. The minimum difference detection means detects two pixel signals with the smallest difference in pixel signal level, and the average value thereof is used to replace the defective pixel signal, so that the defective pixel signal can be compensated with high precision. Furthermore, since the diagonal direction of the defective pixel is also taken into consideration, the defective pixel signal can be compensated for with higher accuracy.

[実施例] 以下この発明の一実施例を第1図及び第2図に
基づいて説明する。説明を簡略化するためにTV
信号などのように一行毎に順次走査していくこと
により画像をあらわす信号を画像欠陥補償の対象
とする場合を例にとつて説明する。第1図におい
て9は遅延回路、9a〜9iは遅延回路1の出力
端子、10は該出力端子9a〜9dと出力端子9
f〜9iとの各出力の差を求める引き算回路10
a〜10dにて構成される引き算手段、11は該
引き算手段10の各引き算回路10a〜10dか
ら各々出力される値の絶対値をとる絶対値回路1
1a〜11dにて構成される絶対値手段、12は
該絶対値手段11を構成する各絶対値回路11a
〜11dの各値を比較する比較回路、13は上記
遅延回路9の各出力端子9a〜9dと出力端子9
f〜9iとの各出力の平均値を演算する平均回路
13a〜13dにて構成される平均値演算手段、
14は該平均値演算手段13の各平均回路13a
〜13dの各出力値のいずれかを選択する選択回
路、15は欠陥画素を補償する信号を出力する欠
陥補償信号発生回路、16は上記遅延回路9の出
力端子9eの出力、比較回路12の出力及び選択
回路14の出力が各々入力され欠陥画素の信号を
補償することにより置換して出力する置換回路を
示す。なお、上記欠陥補償信号発生回路15には
記憶装置が含まれ欠陥画素の位置を予め記憶して
おりそれに基づき欠陥補償信号を発生する構成で
ある。
[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. TV to simplify explanation
An example will be described in which a signal representing an image is subjected to image defect compensation by sequentially scanning line by line, such as a signal. In FIG. 1, 9 is a delay circuit, 9a to 9i are output terminals of the delay circuit 1, and 10 is the output terminal 9a to 9d and the output terminal 9.
Subtraction circuit 10 that calculates the difference between each output from f to 9i
Subtraction means constituted by a to 10d; reference numeral 11 denotes an absolute value circuit 1 that takes the absolute value of the value output from each subtraction circuit 10a to 10d of the subtraction means 10;
Absolute value means constituted by 1a to 11d; 12 denotes each absolute value circuit 11a constituting the absolute value means 11;
A comparison circuit 13 compares each value of the output terminals 9a to 9d of the delay circuit 9 and the output terminal 9.
an average value calculation means constituted by average circuits 13a to 13d that calculate the average value of each output of f to 9i;
14 is each average circuit 13a of the average value calculation means 13;
15 is a defect compensation signal generation circuit that outputs a signal to compensate for the defective pixel, 16 is the output of the output terminal 9e of the delay circuit 9, and the output of the comparison circuit 12. A replacement circuit is shown in which the outputs of the selection circuit 14 and the selection circuit 14 are respectively input, and the signal of the defective pixel is replaced by compensating for the signal and outputted. The defect compensation signal generating circuit 15 includes a storage device, stores the position of a defective pixel in advance, and generates a defect compensation signal based on the position of the defective pixel.

次に本実施例に係る画像欠陥補償装置の動作を
説明する。第2図Aは水平方向(行方向)、垂直
方向(列方向)に並べられた画素配列の一部を示
した図である(第2図Aに示された画素配列の態
様を「正方格子状」と呼ぶ)。同図においてm行、
n列の信号をS(m,n)であらわすことにする。
まるm行n列の画素の信号に欠陥がある場合につ
いて説明する。第2図B,C,D,Eは各々欠陥
画素周辺の絵柄を示す図である。
Next, the operation of the image defect compensation apparatus according to this embodiment will be explained. FIG. 2A is a diagram showing a part of a pixel array arranged in the horizontal direction (row direction) and vertical direction (column direction). ). In the same figure, m rows,
Let the n-column signals be expressed as S(m, n).
A case will be described in which there is a defect in the signal of a pixel of m rows and n columns. FIGS. 2B, C, D, and E each show a pattern around a defective pixel.

まず、第1図において遅延回路9は、出力端子
9eに信号S(m,n)が出力されている時に、
出力端子9aに信号S(m+1,n+1)、出力端
子9bに信号S(m+1,n)、出力端子9cに信
号S(m+1,n−1)、出力端子9dに信号S
(m,n+1)、出力端子9fに信号S(m,n−
1)、出力端子9gに信号S(m−1,n+1)、
出力端子9hに信号S(m−1,n)、出力端子9
iに信号S(m−1,n−1)を各々出力する。
なおこの遅延回路9は例えばCCDやLCデイレイ
ーイコライザなどにより構成することができる。
First, in FIG. 1, the delay circuit 9, when the signal S (m, n) is output to the output terminal 9e,
Signal S (m+1, n+1) to output terminal 9a, signal S (m+1, n) to output terminal 9b, signal S (m+1, n-1) to output terminal 9c, signal S to output terminal 9d.
(m, n+1), and the signal S(m, n-
1), signal S (m-1, n+1) to output terminal 9g,
Signal S (m-1, n) to output terminal 9h, output terminal 9
A signal S (m-1, n-1) is output to each terminal i.
Note that this delay circuit 9 can be constructed of, for example, a CCD or LC delay equalizer.

次に、上記各出力端子9a〜9d,9f〜9i
から出力される信号は、各引き算回路10a〜1
0dに入力されそれぞれ差が求められ、この各引
き算回路10a〜10dの各出力が各絶対値回路
11a〜11dにて絶対値が得られ、さらにこの
各絶対値回路11a〜11dの出力が比較回路に
より以下に示す2画素間の信号差の大小関係とし
て比較する。
Next, each of the above output terminals 9a to 9d, 9f to 9i
The signal output from each subtraction circuit 10a to 1
0d and the difference is calculated, and the absolute value of each output of each subtraction circuit 10a to 10d is obtained by each absolute value circuit 11a to 11d, and further, the output of each of these absolute value circuits 11a to 11d is sent to a comparison circuit. The signal difference between two pixels is compared as shown below.

上記2画素間の信号差は、 |S(m−1,n)−S(m+1,n)| |S(m,n−1)−S(m,n+1)| |S(m−1,n−1)−S(m+1,n+1)| |S(m−1,n+1)−S(m+1,n−1)| である。 The signal difference between the two pixels above is |S(m-1,n)-S(m+1,n)| |S(m,n-1)-S(m,n+1)| |S(m-1,n-1)-S(m+1,n+1)| |S(m-1,n+1)-S(m+1,n-1)| It is.

さらに、平均値回路13a〜13d、選択回路
14、置換回路16、により、|S(m−1,n)
−S(m+1,n)|が最小の場合には
S(m−1,n)+S(m+1,n)/2をS(m,n
) のかわりとし、|S(m,n−1)−S(m,n+
1)|が最小の場合には
S(m,n−1)+S(m,n+1)/2をS(m,n
) のかわりとし、|S(m−1,n−1)−S(m+
1,n+1)|が最小の場合には
S(m−1,n−1)+S(m+1,n+1)/2をS (m,n)のかわりとし、|S(m−1,n+1)−
S(m+1,n−1)|が最小の場合には
S(m−1,n+1)+S(m+1,n−1)/2をS (m,n)のかわりとする。この4つ場合はそれ
ぞれ第2図B,C,D,Eに各々対応している。
欠陥補償信号発生回路15には記憶装置が含まれ
欠陥画素の位置をあらかじめ記憶されていること
から、出力端子1eに欠陥画素による信号があら
われた時にのみ置換回路16を上述の如く動作さ
せる。
Furthermore, the average value circuits 13a to 13d, the selection circuit 14, and the replacement circuit 16 calculate |S(m-1,n)
-S(m+1,n)| is the minimum, S(m-1,n)+S(m+1,n)/2 is S(m,n
) instead of |S(m,n-1)-S(m,n+
1) If | is the minimum, then S(m, n-1)+S(m, n+1)/2 is
) instead of |S(m-1,n-1)-S(m+
1, n+1) | is the minimum, use S (m-1, n-1) + S (m+1, n+1)/2 instead of S (m, n), and |S (m-1, n+1)-
When S(m+1,n-1)| is the minimum, S(m-1,n+1)+S(m+1,n-1)/2 is used instead of S(m,n). These four cases correspond to FIG. 2, B, C, D, and E, respectively.
Since the defect compensation signal generation circuit 15 includes a storage device and stores the position of the defective pixel in advance, the replacement circuit 16 is operated as described above only when a signal from the defective pixel appears at the output terminal 1e.

なお、上記実施例では遅延回路を用いて構成し
た場合を示したがメモリを用いても同様の機能を
有する回路を構成できる。
Note that although the above embodiment shows a configuration using a delay circuit, a circuit having the same function can also be configured using a memory.

[発明の効果] 以上のように、この発明によれば、欠陥画素信
号の斜め方向をも考慮に入れて演算された絶対値
信号の中で最も小さい値を与える2つの画素信号
を検出する最小差検出手段が設けられたので、欠
陥画素信号をより高精度に補償できる画像欠陥補
償装置が得られた。
[Effects of the Invention] As described above, according to the present invention, the minimum value for detecting two pixel signals that give the smallest value among the absolute value signals calculated taking into account the diagonal direction of the defective pixel signal is Since the difference detection means is provided, an image defect compensation device capable of compensating for defective pixel signals with higher precision is obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例に係る画像欠陥補
償装置の全体回路ブロツク図、第2図は第1図に
示す実施例装置の動作を説明するための図、第2
図Aは画素の配列図、第2図B,C,D,Eは
各々欠陥画素周辺の絵柄を変化させた場合の画素
配列図、第3図は従来の画像欠陥補償装置の全体
回路ブロツク図、第4図は従来の画像欠陥補償装
置の動作の説明用線図である。 図において、9は遅延回路、10は引き算手
段、11は絶対値手段、12は比較回路、13は
平均値演算手段、14は選択回路、15は欠陥補
償信号発生回路、16は置換回路。なお、各図
中、同一符号は同一又は相当部分を示す。
FIG. 1 is an overall circuit block diagram of an image defect compensation device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the embodiment device shown in FIG. 1, and FIG.
Figure A is a pixel arrangement diagram, Figures 2B, C, D, and E are pixel array diagrams when the pattern around the defective pixel is changed, and Figure 3 is an overall circuit block diagram of a conventional image defect compensation device. , FIG. 4 is a diagram for explaining the operation of a conventional image defect compensation device. In the figure, 9 is a delay circuit, 10 is a subtraction means, 11 is an absolute value means, 12 is a comparison circuit, 13 is an average value calculation means, 14 is a selection circuit, 15 is a defect compensation signal generation circuit, and 16 is a replacement circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】 1 行方向および列方向に正方格子状に配設され
た複数の撮像素子から出力される画素信号S(m
−1,n−1)ないしS(m+1,n+1)に含
まれる欠陥画素信号S(m,n)を補償する画像
欠陥補償装置であつて、 前記欠陥画素信号を垂直方向、水平方向および
斜め方向にそれぞれ挟む2つの画素信号間ごとの
差の絶対値を演算し、絶対値信号|S(m−1,
n)−S(m+1,n)|,|S(m,n−1)−S
(m,n+1)|,|S(m−1,n−1)−S(m+
1,n+1)|および|S(m−1,n+1)−S
(m+1,n−1)|を出力する絶対値演算手段
と、 前記絶対値信号の中で最も小さい値を与える2
つの画素信号を検出する最小差検出手段と、 前記最小差検出手段により検出された2つの画
素信号について平均値演算を行ない、平均値信号
を出力する平均値演算手段と、 前記欠陥画素信号を前記平均値信号で置換する
置換手段とを含む、画像欠陥補償装置。
[Claims] 1. Pixel signals S(m
-1, n-1) to S(m+1, n+1), the image defect compensation device compensates for a defective pixel signal S(m,n) included in S(m+1,n+1), wherein the defective pixel signal is transmitted vertically, horizontally, and diagonally. The absolute value of the difference between the two pixel signals sandwiched between the two pixel signals is calculated, and the absolute value signal |S(m-1,
n)-S(m+1,n)|,|S(m,n-1)-S
(m, n+1) |, |S(m-1,n-1)-S(m+
1,n+1) | and |S(m-1,n+1)-S
(m+1,n-1)|; and 2 which gives the smallest value among the absolute value signals.
minimum difference detection means for detecting one pixel signal; average value calculation means for performing an average value calculation on the two pixel signals detected by the minimum difference detection means and outputting the average value signal; and replacement means for replacing with an average value signal.
JP60104338A 1985-05-14 1985-05-14 Picture defect compensation device Granted JPS61260772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60104338A JPS61260772A (en) 1985-05-14 1985-05-14 Picture defect compensation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60104338A JPS61260772A (en) 1985-05-14 1985-05-14 Picture defect compensation device

Publications (2)

Publication Number Publication Date
JPS61260772A JPS61260772A (en) 1986-11-18
JPH0523551B2 true JPH0523551B2 (en) 1993-04-05

Family

ID=14378137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60104338A Granted JPS61260772A (en) 1985-05-14 1985-05-14 Picture defect compensation device

Country Status (1)

Country Link
JP (1) JPS61260772A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989002730A1 (en) * 1987-09-28 1989-04-06 Terumo Kabushiki Kaisha Separate storage container

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2808813B2 (en) * 1990-04-13 1998-10-08 ソニー株式会社 Video information interpolation circuit
EP1297687A1 (en) * 2000-06-23 2003-04-02 Koninklijke Philips Electronics N.V. Image sensor signal defect correction
JP2003078821A (en) 2001-08-31 2003-03-14 Hitachi Kokusai Electric Inc Imaging apparatus
JP4850730B2 (en) 2006-03-16 2012-01-11 キヤノン株式会社 Imaging apparatus, processing method thereof, and program

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5114844A (en) * 1974-07-29 1976-02-05 Mitsubishi Heavy Ind Ltd SUMINIKUYO SETSUHO
JPS5956768A (en) * 1982-09-24 1984-04-02 Mitsubishi Electric Corp Device of correcting defect of solid-state image pick up sensor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5114844A (en) * 1974-07-29 1976-02-05 Mitsubishi Heavy Ind Ltd SUMINIKUYO SETSUHO
JPS5956768A (en) * 1982-09-24 1984-04-02 Mitsubishi Electric Corp Device of correcting defect of solid-state image pick up sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989002730A1 (en) * 1987-09-28 1989-04-06 Terumo Kabushiki Kaisha Separate storage container

Also Published As

Publication number Publication date
JPS61260772A (en) 1986-11-18

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