JPH05233566A - Routing method for array processor - Google Patents

Abstract

PURPOSE:To set a routing path by a program and at the same time to attain the simultaneous transfer to plural processors in a packet routing method for array processors which can connect the unit processors together in en optional constitution. CONSTITUTION:Four communication ports end arithmetic processor ports are connected to each other at each processor node 10 via a mutual connection network. Then a routing table is provided to designate the transfer control among those ports. This table can be read and written by an arithmetic processor so that a packet transfer path can be set and the simultaneous transfer is possible to plural addressed processors. Thus it is possible to connect the processors together with reliance on an application, to control the traffic of the network, and to set a communication path of high efficiency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array processor routing method for performing interprocessor communication by link-linking processors.

[0002]

2. Description of the Related Art Conventionally, as a method of realizing communication between processors of an array processor, there are 1) a method of performing communication only between adjacent processors and 2) a method of realizing communication between remote processors using a router.

Among these, in the method of performing communication only between adjacent processors, the amount of hardware required for processor communication is relatively small, but when performing communication between remote processors,
Since communication between adjacent processors is repeated between the processors on the path from the sending processor to the receiving processor, the communication time and the load on each processor on the communication path become problems. For an array processor that performs communication only between adjacent processors, see S. Y. Kun
g, "Wavefront Array Procedures"
sors-Concepts to Implement me
station ”, IEEE Computer, pp
18-33, July 1987. In addition, P. Wilson, "Thirty two
bit micro supports multip
processing ”, Computer Design
n, pp 143-150, June 1984. Then, a unit processor for constructing an array processor having a configuration and a combination form according to the purpose is described.

On the other hand, in the method using the router, the amount of hardware required for interprocessor communication becomes large,
Since communication is performed from the sending processor to the receiving processor via the router, the communication time is relatively short and the load on other processors is not a problem.

The routing method in the method using the router is determined depending on the coupling form of the processors. For example, in the two-dimensional mesh connection method, the number of steps in the east-west direction (hop count) and the number of steps in the north-south direction (hop count)
Routing is performed by specifying. W. J. D
ally, "A VLSI Architecture
for Concurrent Data Strru
Ctures ”, Kluwer Academic P
Section 5.3.3 of less, 1987 describes the routing system described above.

[0006]

However, since the processor configuration of the array processor using the conventional router is fixed, some processors may not be effectively used depending on the processing purpose. Also, in the routing method, since the route used is fixed, the traffic increases to one route depending on the application,
There may be a communication bottleneck, which hinders parallel processing. In addition, when data is broadcast to a plurality of processors, communication must be performed for each destination processor.

An object of the present invention is to combine a plurality of unit processors into a structure suitable for a processing purpose by a connection link, and to freely set a routing in a network formed by the connection by a program. Another object of the present invention is to provide an array processor routing method capable of realizing data broadcasting to one processor by a single message communication.

[0008]

SUMMARY OF THE INVENTION According to the present invention, in a routing method of an array processor for performing inter-processor communication by link-linking between processors, each unit processor is connected to an arithmetic processor and is generated or connected to the arithmetic processor. A means for transferring a message packet sent from one of the plurality of connection links to one or more designated destinations from the plurality of connection links or the arithmetic processor, and a message packet from the address information in the message packet. A unit or a plurality of links to be transferred or a routing information storage unit for designating an arithmetic processor is provided, and by setting the routing information storage unit by the arithmetic processor, a unit processor is arbitrarily connected by a connection link according to a processing purpose. Conclusion And, wherein the sending a message packet on any paths for combined each one or a plurality of specified destination processor from the processor.

[0009]

The principle of the present invention will be described below. According to the array processor routing method of the present invention, a unit processor having a plurality of connection links is provided with a routing table serving as routing information storage means, whereby message transfer according to the processor configuration can be realized. With respect to the message packet sent from the unit processor, the destination address information added in the message packet is used to access the routing table to obtain the transfer destination information. Since the routing table is assigned with a bit for setting whether or not to transfer to all possible transfer destinations (connection link and processor), transfer to a plurality of links or arithmetic processors is possible.

Further, since the routing table can be rewritten by the arithmetic processor, it is possible to set and change the route of message transfer by the program before or during the execution of the program. As a result, the communication path depending on the application can be set.
When sending one message packet to a plurality of unit processors, one for each group of processors.
This is possible by allocating one address and setting a value that realizes a message transfer route to each processor in the corresponding address in the routing table of each unit processor.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is an embodiment of the present invention and shows an array processor in which a plurality of unit processor nodes 10 connected to four links are connected. FIG. 2 shows the configuration of the unit processor node 10. The unit processor includes an arithmetic processor 21, a processor port 22, and a first communication port 2
3, a second communication port 24, a third communication port 25, a fourth communication port 26, a control circuit 27, and a routing table 28.

The first communication port 23, the second communication port 24, the third communication port 25, and the fourth communication port 26.
Receives a message packet sent from another connected unit processor node, extracts the destination address information in the message packet, and sends it to the control circuit 2
Send to 7. The processor port 22 is the arithmetic processor 21.
The destination address information of the message packet written from is extracted and sent to the control circuit 27.

The control circuit 27 looks up the routing table 28 according to the destination address sent to the first address to be transferred.
The message transfer control signal is sent to any one of the communication port 23, the second communication port 24, the third communication port 25, and the fourth communication port 26, or the processor port 22. At this time, the routing table shows that the first communication port 23, the second communication port 24, the third communication port 25, the fourth communication port 26, and the processor port 22.
5 bits assigned 1 bit to 5 destinations of 1
Each address word is composed of a readable / writable memory having an address space obtained by adding a certain number of additional numbers to the number of processors. Also routing table 2
8 can be set and changed by the arithmetic processor 21.

The first communication port 23, the second communication port 24, the third communication port 25, and the fourth communication port 26.
Also, upon receiving the message transfer control signal, sends out the sent message packet to the connected adjacent unit processor node. When the processor port 22 receives the message transfer control signal, the processor port 22 receives and stores the sent message so that the arithmetic processor 21 can read it.

FIG. 3 shows an example of routing in the processor configuration of FIG. In FIG. 3, P in each unit processor indicates an arithmetic processor. The array processor shown in FIG. 3 includes a first unit processor 31, a second unit processor 32, a third unit processor 33, a fourth unit processor 34, a fifth unit processor 35, a sixth unit processor 36, and a sixth unit processor 36. 7 unit processors 37 and an eighth unit processor 38. This routing shows the case where the destination is the seventh unit processor.

FIG. 4 shows a routing table of each processor corresponding to FIG. In FIG. 4, the column of P is a processor, the column of N is upward, the column of E is rightward, the column of S is downward, and the column of W is a bit that specifies transfer to the left. (A) is a routing table for the first unit processor 31, (b) is a routing table for the second unit processor 32, and (c) is a third unit processor 3.
3 shows a routing table for the third unit processor 37, and (d) shows a routing table for the seventh unit processor 37.

The message packet sent from the arithmetic processor of the first unit processor 31 is sent to the second unit processor 32 by the value E of the address 7 in the routing table of the first unit processor 31, and is sent to the second unit processor 32. In 32, the value E of the address 7 in the routing table of the second unit processor 32 is sent to the third unit processor 33, and the third unit processor 33
Then, according to the value S of the address 7 in the routing table of the third unit processor 33, the seventh unit processor 37
Is sent to the seventh unit processor 37, which is the destination processor, by the value P of the address 7 in the routing table of the seventh unit processor 7.
Written to 7 processor ports. The path of such message transfer is determined by the setting of the routing table of each unit processor shown in FIG.

FIG. 5 shows another example of routing in the processor configuration of FIG. In FIG. 5, P in each unit processor indicates an arithmetic processor. Further, FIG. 6 shows a routing table corresponding to FIG. (A) is a routing table for the first unit processor 31, (b) is a second and third unit processor 3
2 and 33 show the routing tables, the (c) shows the routing table for the fourth and sixth unit processors 34, 36, and the (d) shows the routing table for the fifth unit processor 35.

When one message packet is sent from the first unit processor 31 to the fourth unit processor 34, the fifth unit processor 35, and the sixth unit processor 36, the fourth unit processor 34, the fifth unit processor 34. One address 17 is assigned to the group of the unit processors 35 and the sixth unit processors 36, and the route of the message transfer to each processor is assigned to the address 17 corresponding to the routing table of each unit processor as shown in FIG. Set the value that realizes.

The message packet sent from the arithmetic processor of the first unit processor 31 has the address 17 in the routing table of the first unit processor 31.
Is sent to the second unit processor 32 and the fifth unit processor 35 by the value ES of
In 2, the value E of the address 17 in the routing table of the second unit processor 32 is sent to the third unit processor 33. In the third unit processor 33, the address 17 of the routing table of the third unit processor 33 is sent. Sent to the fourth unit processor 34 by the value E,
In the fourth unit processor 34, the value of the address P in the routing table of the fourth unit processor 34 is written in the processor port of the fourth unit processor 34 which is the destination processor.

At the same time, in the fifth unit processor 35, the value PE of the address 17 in the routing table of the fifth unit processor 35 is written in the processor port of the fifth unit processor 35 which is the destination processor. At the same time, it is sent to the sixth unit processor 36,
In the sixth unit processor 36, the value P of the address 17 in the routing table of the sixth unit processor 36 is written to the processor port of the sixth unit processor 36 which is the destination processor.

As described above, the first unit processor 31 to the fourth unit processor 34 and the fifth unit processor 3 are set by setting the routing table shown in FIG.
5, are transferred to the sixth unit processor 36 at the same time.

[0024]

As described above, according to the present invention, by rewriting the routing table in an array processor combined in any form, it is possible to send a message packet of any route, and the unit processor It is possible to send message packets to multiple unit processors simultaneously.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a first invention.

FIG. 2 is a diagram showing a configuration of a unit processor.

FIG. 3 is a diagram showing an example of message transfer.

FIG. 4 is a diagram showing a routing table of each unit processor in the example of FIG.

FIG. 5 is a diagram showing another example of message transfer.

FIG. 6 is a diagram showing a routing table of each unit processor in the example of FIG.

[Explanation of symbols]

 10 unit processor node 21 arithmetic processor 22 processor port 23 first communication port 24 second communication port 25 third communication port 26 fourth communication port 27 control circuit 28 routing table 31 first unit processor 32 second Unit processor 33 Third unit processor 34 Fourth unit processor 35 Fifth unit processor 36 Sixth unit processor 37 Seventh unit processor 38 Eighth unit processor

Claims (1)

[Claims] 1. A routing method of an array processor for performing inter-processor communication by link-linking processors, wherein each unit processor has one of a plurality of operation processors and a plurality of connection links generated or connected from the operation processors. Means for transferring a message packet sent from a plurality of connection links or destinations specified by a plurality of connection processors, and a single or a plurality of links for transferring a message packet from address information in the message packet, or A routing information storage means for designating an arithmetic processor is provided, and by setting the routing information storage means by the arithmetic processor, the unit processors are arbitrarily coupled by a connection link according to the processing purpose, and each of the coupled processors is connected. The Array processor routing method characterized by sending a message packet by any route with respect to one or a plurality of specified destination processor from processor.