JPH05233115A - Digital signal input device - Google Patents

Abstract

PURPOSE:To simplify the filtering processing of an input signal and to speed up a processing. CONSTITUTION:The exclusive OR in changes before and behind input data which are sequentially stored in a sampling data file 3 is taken to be stored in an exclusive OR file 4. The exclusive OR of the head value of the file 4 and a work file 8 is obtained and the file 8 is updated. The AND of the head value of the file 4 and the inverse values of succeeding values is calculated to be stored in a first register 6. Furthermore, the AND of the file 8 and the register 6 is obtained and stored in a second register 9. Then, the exclusive OR of the value of the register 9 and the value of the file 8 is obtained and the file 8 is updated. The exclusive OR of the value of the register 9 and the value of a filtering result file 7 is obtained, and the file 7 is updated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal input device, and more particularly to a digital signal input device having a filtering function for removing noise such as chattering contained in a signal input from a contact such as a switch.

[0002]

2. Description of the Related Art Filtering processing in a conventional digital signal input device is performed as shown in FIG. That is, the values of the input 0 to N channel digital signals are sampled at regular intervals and sequentially stored in the sampling data file 1. In the figure, it is determined whether or not the values of the M times of data stored for each of 0 to N channels match, and if they match, the value is extracted,
Write to filtering result file 2. It should be noted that A _{1 to} A _N surrounded by broken lines in the figure represent a process of determining whether or not the values of all bits match for each channel, and B represents a file operation for storing the filtering result.

[0003]

However, in the conventional filtering process, the bit value is discriminated M times for each channel, and the file operation is performed only when all have the same value. Since this processing is performed from 0 channel to N channel, there is a problem that the processing becomes complicated and it is difficult to speed up the filtering processing. The present invention has been made to solve the above problems, and an object of the present invention is to provide a digital signal input device that simplifies processing and enables high speed processing.

[0004]

In order to achieve the above object, the present invention provides means for sampling the value of a signal input for each channel at regular intervals and sequentially storing the sampled data file in a sampling data file, and for each channel. , Means for calling the latest m values stored in the sampling data file to obtain an exclusive OR of successive values, and storing the obtained m-1 sets of values in the exclusive OR file, A means for leaving the value of the oldest set in the logical OR file as it is, inverting the values of the remaining m-2 sets and storing them together in the calculation file, and m stored in the calculation file.
-1 means for obtaining the logical product of a set of values for each channel and storing it in the first register, the value of the exclusive OR of the oldest set in the exclusive OR file, and the value in the work file A means for obtaining the exclusive OR for each channel and updating the value in the work file by the value, and a logical product of the value of the first register and the value of the work file for each channel to obtain the second register To store the value of the second register and the value of the work file for each channel, and means for updating the value in the work file by the value, and the value of the second register And a means for obtaining the exclusive OR of the previous filtering result stored in the filtering result file for each channel and updating the value in the filtering result file with the value. And it features.

[0005]

In the present invention, the value of the signal input for each channel is sampled at regular intervals and sequentially stored in the sampling data file. Then, the latest m values stored in the sampling data file are called, and the exclusive OR with the successive values is obtained for each channel, and the obtained m-1 sets of values are transferred to the exclusive OR file. Is stored. The values of the oldest set in the exclusive OR file are left unchanged, the values of the remaining m-2 sets are inverted, and they are both stored in the calculation file.

A logical product of m-1 sets of values stored in the calculation file is obtained for each channel and stored in the first register. Exclusive OR of the value of the oldest set in the exclusive OR file and the value in the work file is calculated for each channel, and the value in the work file is updated by the obtained value. It The logical product of the value of the first register and the value of the work file is obtained for each channel and stored in the second register.

The exclusive OR of the value of the second register and the value of the work file is obtained for each channel, and the value in the work file is updated with the obtained value. The exclusive OR of the value of the second register and the previous filtering result stored in the filtering result file is obtained for each channel, and the value in the filtering result file is updated with the obtained value. The value of this filtering result file becomes the digital signal input value.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing an outline of the filtering process of the digital signal input device according to the present invention, and shows that signals of four channels are input as sampling data six times and the filtering process is performed five times. The input data is represented as 4 channels, that is, 4 bits, and is stored 6 times in order from the beginning of the sampling data file 3. As for these data, new data is added to the lowermost stage for each sampling and shifted to the upper stage for each stage. The uppermost data is deleted at the next sampling.

Next, the exclusive OR of each of the data taken in the file 3 and the preceding and succeeding data is obtained for each channel and stored in the exclusive OR file 4. Both C and D in the figure indicate the processing for obtaining the exclusive OR. Here, the value located at the head of the five sets of exclusive ORs stored in the file 4 is transferred as it is to the calculation file 5 (process E). At the same time, the second and subsequent four values of file 4 are inverted and written to file 5 (process F). In addition, file 5 of 5 written
The logical product of the set of values is obtained for each channel and stored in the first register 6 (process G).

Then, the exclusive OR of the value of the register 6 and the value 7a stored in the filtering result file 7 is obtained for each channel, and the file 7 is updated with the value 7b (process H). In this way, the result of the filtering process is sequentially updated in the filtering result file 7. The value of the file 7 thus sequentially updated is read into another apparatus body or the like by another process.

In the data shown in the figure, the upper 2 bits are inverted from "00" to "11" when the first sampling is changed to the second sampling in the file 3, and the value is held thereafter. There is. As a result, it is considered that the input value of the upper 2 bits has changed, and the upper 2 bits of the file 7 are changed to "11". That is, when the input signal changes, it is detected as a change in the input signal only after being sampled five times in succession.

By the way, in the filtering process described above, even if the input signal changes, if the change is less than 5 times, it is not detected as a change in the input signal. However, in that case, the sampling data at the end of the change is in file 3
If it moves to the uppermost row of 5 and the next and subsequent data has a value different from that of the uppermost row for 5 times in succession, the corresponding bit of the file 7 is erroneously assumed to have been changed because the input signal has changed. Defect occurs. This will be described with reference to the figure. It is assumed that "1100" is past 5 times or more in the upper part of the file 3 as past sampling data in the illustrated state. In that case, the value 7a before the update of the file 7 is "1100", and when it is exclusive ORed with the value "1100" of the register 6,
It will be erroneously updated to "0000".

Therefore, in consideration of these points, filtering as shown in FIG. 2 will be carried out so as to withstand practical use. That is, the data storage location of the file 3 is further increased upward as the 0th time, and at the same time, the storage location of the file 4 is further increased upward. Thus, the value of the exclusive OR of the 0th sampling data and the 1st sampling data is stored at the beginning of the file 4. The exclusive OR of the value of this exclusive OR and the initial value 8a already stored in the work file 8 is obtained, and the work file 8a is updated to 8b by the value (process J).

Further, the first stored in the file 4
The exclusive OR of the value of the exclusive OR of the second and second sampling data and the updated value 8b of the work file 8 is calculated, and the value 8c is used to determine the work file 8
Is updated (process K). A logical product of the updated value 8c of the work file 8 thus obtained and the value of the first register 6 is obtained and stored in the second register 9 (process L). At the same time, the value of register 9 and the updated value 8c of work file 8
Then, the exclusive OR of is calculated and the file 8 is updated again (process P). Further, the exclusive OR of the value of the register 9 and the value 7a stored in the filtering result file 7 is obtained, and the file 7 is updated with the value 7b (process H).

In this illustrated example, the changes in the sampling data stored in the file 3 from the first time onward are exactly the same as those in the example of FIG. 1, but since the previous 0th time has a different value, this first time is different. It shows that the first change is a one-time change. That is, when the sampling data changes once or in a short period of time, the logical product with the work file 8 is taken to prevent erroneous detection as a change of the input signal. In this way, by providing the work file 8 to store sporadic changes in sampling data, it is possible to prevent input data from being erroneously inverted.

FIG. 3 is a flowchart showing the filtering process of the present invention. The filtering process will be systematically described below based on this flowchart. First, with the number of times of filtering set to m, it is determined whether or not the process of calculating the exclusive OR between the preceding and following data in the sampling data file 3 has been completed (m-1) times (S1).

If not completed (S1 NO), the exclusive OR of the previous value and the current value of the sampling data file 3 is calculated and stored in the corresponding address of the exclusive OR file 4 (S2). Then, the corresponding address of the exclusive OR file 4 in which the exclusive OR is stored is incremented and the processing of one cycle is finished (S3). Also,
If the calculation processing of the exclusive OR is completed (m-1) times in S1 (YES in S1), the exclusive OR of the previous value and the current value of the sampling data file 3 is obtained, and the exclusive OR is obtained. The file is stored in the final address of file 4 (S4).

Next, an exclusive OR of the value stored at the head of the exclusive OR file 4 and the value of the work file 8 is obtained, and the work file 8 is updated with the obtained value (S5 ). Further, the values at the beginning of the exclusive OR file 4 are left as they are, the values after that are inverted and transferred to the calculation file 5, and then the logical product of these values is calculated to obtain the first register 6 Store to (S
6).

Next, the logical product of the value of the first register 6 and the work file 8 is obtained and stored in the second register 9 (S7). Further, the exclusive OR of the value stored in the second register 9 and the value of the work file 8 is obtained, and the work file 8 is updated again with the obtained value (S8). At the same time, the exclusive OR of the value stored in the second register 9 and the value of the filtering result file 7 is obtained, and the filtering result file 7 is updated with the obtained value (S9).

Next, each value of the exclusive OR file 4 is shifted upward by one block (S10), and the filtering process for one cycle is completed. By these processes, the value of the filtering result file 7 that is sequentially updated becomes the value of the result of filtering the input digital signal. The input signal thus filtered becomes a stable digital signal value by removing noise such as chattering contained in the first sampling input signal.

Further, in these filterings, there is no branch point as in the conventional example, and the processing process becomes relatively simple. Further, since the filtering of the present invention is realized by software, the number of sampling data, the number of channels, and the sampling interval can be arbitrarily set, and the change on the way is easy.

[0022]

As described above, according to the present invention, the values of the signals input for each channel are sampled at regular intervals, and the values are subjected to processing such as exclusive OR and logical product. Filtering removes noise from the input signal. Thereby, it is possible to obtain a digital signal input device having a simple structure and capable of high-speed processing. Moreover, since the present invention is realized by software,
It is easy to change the number of input channels, and moreover,
It is easy to change the settings of the number of times of filtering and the sampling interval, and it is convenient.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an outline of a filtering process according to the present invention.

FIG. 2 is an explanatory diagram showing the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of FIG.

FIG. 4 is an explanatory diagram showing a conventional filtering process.

[Explanation of symbols]

 3 Sampling data file 4 Exclusive OR file 5 Calculation file 6 First register 7 Filtering result file 7a Initial value of filtering result file 7b Updated value of filtering result file 8 Work file 8a Initial value of work file 8b Work file Update value 8c Update value of work file 9 Second register

Claims (1)

[Claims] 1. A means for sampling the value of a signal input to each channel at regular intervals and sequentially storing it in a sampling data file, and calling up the latest m values stored in the sampling data file for each channel. Means for obtaining the exclusive OR of successive values and storing the obtained m-1 set of values in the exclusive OR file, and leaving the value of the oldest set in the exclusive OR file unchanged Means for inverting the m-2 sets of values and storing them in the calculation file together, and obtaining the logical product of the m-1 sets of values stored in the calculation file for each channel, and storing them in the first register. Means to store, the exclusive OR of the value of the oldest set in the exclusive OR file and the value in the work file is calculated for each channel, and the value is used in the work file. A means for updating the value, a means for obtaining a logical product of the value of the first register and the value of the work file for each channel and storing the logical product in the second register, a value of the second register, and a value of the work file. A method of obtaining the exclusive OR of the value for each channel and updating the value in the work file with the value, the value of the second register, and the previous filtering result stored in the filtering result file A digital signal input device comprising: means for obtaining a logical OR for each channel and updating the value in the filtering result file with the value.