JPH05227519A - Encoder and decoder for picture data - Google Patents

Abstract

PURPOSE:To provide an encoder which encodes a large amount of picture data in a short processing time by operating a parallel processing, and a decoder of the picture data. CONSTITUTION:The parallel processing is operated by plural encoding circuits 2 and 3 including plural orthogonal transformation circuits 21 and 31 which operate an orthogonal transformation to the picture data divided into plural blocks by each block, plural quantizing circuits 22 and 32 which quantize the orthogonal-transformed outputs by each frequency component, and plural variable length encoding circuits 23 and 33 which variable length-encode the quantized outputs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device and a decoding device for highly compressing and coding image data.

[0002]

2. Description of the Related Art When an image signal is stored as a digital data in a storage device such as a memory card, a magnetic disk or a magnetic tape, or when the image signal is transmitted and received by an image communication device, the amount of the data. Therefore, in order to record or transmit / receive many frame images in a limited storage capacity range, some high-efficiency compression is applied to the obtained image signal data. It is necessary to do it.

Further, in a digital electronic still camera or the like, it is necessary that the time required for recording / reproducing data is short. In addition, digital VTR (video tape recorder)
The same applies when a moving image is recorded in a digital moving image file or the like. That is, even if it is a still image,
Even for moving images, the time required for the data recording / reproducing process must be short.

As a highly efficient compression method of image data, an encoding method combining orthogonal transform encoding and variable length encoding is widely known. As a typical example, there is a method being studied in the international standardization of still image coding.
An outline of this method will be described below.

First, the image data is divided into blocks of a predetermined size, and two-dimensional DCT (discrete cosine transform) is performed as an orthogonal transform for each of the divided blocks. Next, linear quantization is performed according to each frequency component, and Huffman coding is performed on this quantized value as variable length coding.
At this time, with respect to the DC component, the difference value from the DC component of the neighboring block is Huffman coded. The AC component is scanned from a low frequency component to a high frequency component called a zigzag scan, and two-dimensional Huffman coding is performed from the number of consecutive invalid (value 0) components and the value of the effective component that follows. ..

The above operation will be specifically described with reference to FIG. 8. First, as shown in FIG. 8A, image data of one frame is divided into blocks of a predetermined size (for example, 8 ×). Divided into blocks A, B, C, ... Of 8 pixels, (b)
As shown in, the two-dimensional DCT (discrete cosine transform) is performed as an orthogonal transform for each of the divided blocks.
Sequentially store on a × 8 matrix.

Looking at the image data in a two-dimensional plane,
It has a spatial frequency that is frequency information based on the distribution of grayscale information. Therefore, by performing the above DCT,
The image data is converted into DC component AC and AC component AC,
On the 8 × 8 matrix, there is data indicating the value of the DC component DC at the origin position (0,0 position), and (0,7).
Data indicating the maximum frequency value of the AC component AC in the horizontal axis direction is provided at the position, and data indicating the maximum frequency value of the AC component AC in the vertical axis direction is further provided at the (7,0) position. ,
At the (7, 7) position, the data indicating the maximum frequency value of the AC component AC in the oblique direction is stored, and at the intermediate position, the frequency data in the direction associated with each coordinate position is from the origin side. Sequentially higher frequencies will be stored as they appear.

Next, the storage data of each coordinate position in this matrix is divided by the quantization width for each frequency component to perform linear quantization according to each frequency component (c), and this quantization is performed. Huffman coding is performed as variable-length coding on the values. At this time, regarding the DC component DC, the difference value from the DC component of the neighboring block is expressed by a group number (number of additional bits) and additional bits, and the group number is Huffman-encoded to obtain a code word. The additional bits are combined to form the encoded data (d1, d2, e1, e
2).

Coefficients effective for the AC component AC (values not "0") are represented by a group number and additional bits. Therefore, the AC component AC scans from a low frequency component to a high frequency component called a zigzag scan, and a continuous number (zero run number) of invalid (value “0”) components and a subsequent valid component. Value group
Two-dimensional Huffman coding is performed based on the code number and the obtained codeword and additional bits are combined to obtain coding data.

In Huffman coding, the peak of the frequency of occurrence in the data distribution of each of the DC component DC and the AC component AC per frame image is the center, and the more the center, the more data bits. Is performed to obtain a code word by encoding data in a form in which bits are assigned so that the number of bits is increased toward the periphery. The above is the basic part of this method.

Since the Huffman coding, which is a variable length coding, is used only in this basic part, the code amount is not constant for each image. Therefore, the present inventors have proposed the following method as a method of controlling the code amount in Japanese Patent Application No. 2-13.
Proposed in No. 7222.

That is, in a compression system combining orthogonal transformation and variable length coding, the image signal stored in the memory is divided into blocks in order to control the amount of generated codes, and each divided block is orthogonal. After performing the conversion, after quantizing this conversion output with the provisional quantization width,
This quantized output is variable-length coded, the generated code amount for each block and the total generated code amount of the entire image are calculated, and then the provisional quantization width, the total generated code amount, and the purpose and A new quantization width is predicted from the total code amount to be performed (first pass). Then, the image signal of the image memory is subjected to block division, orthogonal transformation, quantization, and variable length coding using the new quantization width, and the generated code amount and total generated code amount for each block in the first pass are calculated. , Calculate the allocated code amount for each block from the target total code amount, and if the generated code amount of each block exceeds the allocated code amount of each block, terminate the variable length coding in the middle, The process of the block is repeated (second pass). Thus, the code amount is controlled so that the total generated code amount of the entire image does not exceed the target set code amount.

[0013]

As described above, in applications such as image recording and transmission / reception,
It is desirable to be able to compress image data with high efficiency.
There is the above-mentioned international standard draft method as a compression method that satisfies such a demand. In this method, the method of combining the orthogonal transform for each block and the variable length coding as shown in the above example can improve the compression of the image data. Although it can be performed efficiently, it has a drawback that the processing time becomes long because the compression processing procedure is complicated. Generally, since the processing time of data compression is proportional to the number of image elements, the method proposed in the above-mentioned Japanese Patent Application No. 2-137222 for obtaining a particularly high resolution is difficult to make the code amount constant. Although a good result is obtained, there is a drawback that the processing time is further lengthened because two passes are used for encoding. In the image recording apparatus and the electric transmission apparatus, the processing time for data compression needs to be as short as possible in terms of operability and power consumption.

Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to perform parallel processing to encode a large amount of image data in a short processing time. An object of the present invention is to provide a coding device and a decoding device for image data that can be performed.

[0015]

In order to solve the above-mentioned problems, an encoding apparatus as a first configuration of the present invention comprises a plurality of blocking circuits for dividing image data into blocks,
A plurality of orthogonal transformation circuits that perform orthogonal transformation for each of the divided blocks, a plurality of quantization circuits that quantize the orthogonal transformation output for each frequency component, and a plurality of variable circuits that perform variable length coding on the quantized outputs. It comprises a long coding circuit, a buffer circuit for arranging the outputs of the plurality of variable length coding circuits in a series of bit strings, and an output circuit for outputting the output of the buffer circuit for each byte.

Further, the encoding device as the second configuration of the present invention comprises a plurality of block forming circuits for dividing the image data into blocks, and a plurality of orthogonal transforms for carrying out orthogonal transform for each of the divided blocks. A circuit, a plurality of quantization circuits for quantizing the orthogonal transform output for each frequency component, a plurality of variable length coding circuits for variable length coding the quantized output, and a code amount generated in coding A plurality of code amount calculation circuits, a quantization width prediction circuit that predicts an optimum quantization width from the code amounts calculated by the plurality of code amount calculation circuits, and a series of outputs of the plurality of variable length coding circuits. And a buffer circuit for arranging them in a bit string and an output circuit for outputting the output of the buffer circuit for each byte.

Further, the decoding device as the third configuration of the present invention comprises a plurality of variable length code decoding circuits for decoding the quantized values of the variable length coded DC component and AC component, and this decoding. A plurality of dequantization circuits that dequantize the DC component and the AC component that have been subjected to a block determination circuit that obtains a block to be dequantized in each dequantization circuit from the decoded DC component and the AC component; And a plurality of inverse orthogonal transform means for performing inverse orthogonal transform for each block on the inversely quantized DC component and AC component.

[0018]

That is, according to the present invention, the variable length coding processing of the image data is processed in parallel by the plurality of coding circuits, and the obtained data is output in a predetermined format. The processing speed can be improved, and since the encoding is performed by two passes, the data can be kept within a certain code amount. Further, since the processing after the inverse quantization is processed in parallel by the plurality of decoding circuits, the processing speed in decoding can be improved.

[0019]

First, the basic concept of the present invention will be described. The basic idea of the present invention is to improve the processing speed by combining a plurality of encoding devices that function independently and operating them in parallel. For example, the coding circuit may be configured as an integrated circuit (IC), and the number of coding circuits may be appropriately used according to the configuration of a device that requires the coding device. A small-scale device that prioritizes low cost uses only one coding circuit, and a large-scale device or a device that emphasizes performance uses a large number of coding circuit ICs.

When using a plurality of encoding circuits, the following problems arise. That is, in the compression method of the international standard proposal, variable-length codes for the quantized DC or AC components are sequentially arranged without a gap, and this is re-divided every 8 bits (1 byte) to encode data. And
That is, variable length codes are arranged in the delimited bytes without any gap, and some codes are divided and incorporated in the next byte (see FIG. 4 (a)).

On the other hand, if a plurality of encoding circuits encode each of the divided images and the outputted data for each byte is connected as it is, the byte delimiters do not coincide with the end of the code. In that case, as shown in FIG. 4B, extra bits will be generated. If it is left as it is, an extra bit string is interpreted as a wrong code at the time of decoding, and normal encoding cannot be performed. Further, even in the compression method of the international standard proposal, a special code for delimiting the encoded data is inserted as a means for enabling such division.
However, the special code to indicate this break is
It is a redundant code that is not directly related to the image. In addition, in order to be able to recognize the existence of this special code, it is necessary to separate the data in units of bytes, so a more redundant code must be used.

In consideration of the above points, the present invention outputs the encoded data output from each encoding circuit as a serial bit string, connects them, and then separates each byte. As a result, the correct code data with no waste is generated.
Data can be obtained by parallel processing.

A first embodiment of the present invention will be described below with reference to the drawings. This embodiment is an example of parallel processing by two sets of encoding circuits, and a circuit configuration diagram for implementing this is shown in FIG. In the figure, the encoding device of the present invention comprises an image memory 1 constituted by a random access memory RAM, an encoding circuit 2, an encoding circuit 3, a code memory 4, a code memory 5 and a code output circuit 6. Encoding circuit 2 is DC
A T circuit 21, a quantization circuit 22, and a Huffman coding circuit 23 are provided. The coding circuit 3 has the same configuration as the coding circuit 2, and includes a DCT 31, a quantization circuit 32, and a Huffman coding circuit 33. The code memories 4 and 5 are composed of first-in first-out (FIFO) memories.

Next, the operation timing at the time of encoding will be described with reference to FIG. The image memory 1 is divided into areas A and B, and areas corresponding to the left half A and the right half B of the divided image shown in FIG. 3 are recorded. These memory areas are configured so that signals can be read out independently.

At the start of encoding, the area A of the image memory 1
From the area B, the signal B1 of the first to eighth lines is read from the area B, and is input to the encoding circuits 2 and 3, respectively. At this time, signals are sequentially read out for each block of 8 × 8 pixels by memory address control at the time of reading.

The read signal A1 is converted into DCT coefficients by the DCT circuit 21. The converted coefficient is linearly quantized in the quantization circuit 22 with a quantization width determined for each corresponding frequency component. The quantized value is then input to the Huffman coding circuit 23. Here, the DC component is represented by the difference value of the DC component of the preceding block by a group number and additional bits, and the group number is Huffman coded. The AC component is subjected to zigzag scanning, and two-dimensional Huffman coding is performed from the number of consecutive ineffective components (zero run) and the group number of the effective component value that follows. The obtained codeword and additional bits for both DC and AC components are combined to form encoded data. The obtained encoded data is written into the code memory 4 from the encoding circuit 2 as a continuous serial signal in bit units. here
An end-of-block (EOB) code is added to the block in which the 64th (AC maximum frequency) coefficient value does not exist.

On the other hand, also for the signal B1, the encoding circuit 3
In the same process as above, the DCT circuit 31,
The data obtained by the encoding in the quantizing circuit 32 and the Huffman encoding circuit 33 is written in the code memory 5.

The data recorded in the code memories 4 and 5 is read by the code output circuit 6, and at this time, the reading is alternately performed, and the reading of the code memory 4 is first performed. After this reading is completed, the code memory 5 is read. In the code output circuit 6, these coded data are connected and processed as a series of bit strings. That is, it is sequentially divided into 8 bits (1 byte), and if necessary, a marker code (control code) is inserted, bit stuffing (bit 1 is placed in the extra position), and byte stuffing ( When a certain byte becomes "FF", "00" is inserted next, and the like processing is performed and output as code data.

At this time, in the code output circuit 6, the code relating to the DC component at the boundary between the areas A and B is replaced with the code corresponding to the difference value between the DC component of the previous block and the difference from 0. As can be seen from FIG. 2, B1
While the coded data of 1 is waiting to be read from the code memory 5, the signal of the signal A2 (9th to 16th lines of the area A) is read from the image memory 1 in a block-sequential manner, and the coding circuit 2 Is input to and the encoding process as described above is performed. The coded data of A2 is written when the vacancy is generated in the coded memory 4. Similarly, the coding of the signal B2 is also processed in the coding circuit 3 according to the vacancy of the coding memory 5, and the data is written in the coding memory 5. In this way, the coding processing of the signals of the areas A and B is sequentially performed in parallel, and a large amount of data can be efficiently processed at high speed.
Data encoding is performed.

Next, a second embodiment of the present invention will be described. In this embodiment, the code amount control is performed in addition to the parallel processing as shown in the first embodiment. The code decoding process will also be described.

FIG. 5 shows a block diagram of the encoding (decoding) device in this embodiment. Here, 1 is an image memory, 4 and 5 are code memories, respectively, and 6 is a code output circuit, which has the same function as the constituent elements in the previous embodiment given the same numbers.
Reference numerals 7 and 8 are encoding (decoding) circuits, and 9 is a control circuit. Encoding circuits 7 and 8 are DCT circuits 71 and 81, quantizing circuits 72 and 82, Huffman encoding circuit 73,
83, truncation circuits 74, 87, Huffman decoding circuits 75, 85, block counting circuits 76, 86, inverse quantization circuits 77, 84, IDCT
It has (inverse DCT) circuits 78 and 88.

The encoding operation timing in the above configuration will be described with reference to FIG. First, in the first pass, signals in the area A and the area B are simultaneously and sequentially read from the image memory 1 for each block and input to the encoding circuit 7 and the encoding circuit 8 shown in FIG. 5, respectively. The input signal A1 is converted into DCT coefficients by the DCT circuit 71. The transformed coefficient is quantized in the quantization circuit 72 with a provisional quantization width. The quantized value is then used by the Huffman coding circuit.
It is input to 73, and the DC component and the AC component are Huffman coded. The generated code amount value for each block is obtained and output to the control circuit 9.

The control circuit 9 obtains the code amount of each block and the total code amount of each block and stores them. On the other hand, the same processing is performed on the signal B1 in the encoding circuit 8. The code amount for each block obtained as a result is output to the control circuit 9, and the code amount for each block and the cumulative code amount are stored. Here, the values of both A and B are summed as the cumulative code amount. The above operation is sequentially performed in parallel with signals A2, B2, A3, B3 ... And A and B. When the above process is completed for all images, the control circuit 9 predicts the optimum value of the quantization width from the obtained total code amount and the target code amount value. That is, since there is a statistically strong correlation between the quantization width and the code amount, based on this, the quantization width is corrected to bring the code amount closer to the target value. The calculated quantization width correction coefficient is output from the control circuit 9 to the encoding circuits 7 and 8.

Subsequently, the second pass of encoding is performed. The signal A1 is read again from the image memory 1 and input to the encoding circuit 7. The input signal is converted into DCT coefficients in the DCT circuit 71. The transformed coefficient is linearly quantized in the quantization circuit 72, and the quantization width corrected at this time by the correction coefficient given from the control circuit 9 is used. The quantized DCT coefficient is input to the Huffman coding circuit 73. Here, the DC component is expressed by a group number and an additional bit as a difference value of the DC component of the preceding block, and the group number is Huffman coded. The AC component is subjected to zigzag scanning, and the zero run value and the group number of the effective component value are two-dimensionally Huffman encoded. The obtained encoded data together with the additional bits are input to the code truncation circuit 74, and the allocated code amount of the block is controlled. Here, the allocated code amount for a block is obtained by multiplying the stored code amount generated in the block in the first pass by the ratio of the target code amount and the total code amount in the first pass in the control circuit 9. Required by. The calculated block allocation code amount is supplied to the code truncation circuit 74 and compared with the code amount of the coding data of the block. When the actual code amount is within the assigned code amount, the EOB code is added to the encoded data as it is and output to the code memory 4. However, if the 64th coefficient value is not 0, EOB is excluded.

On the other hand, when the actual code amount exceeds the assigned code amount, the high frequency component is truncated so that the code amount falls within the assigned amount. That is, the encoded data (Huffman code and additional bits) up to the assigned code amount is output to the code memory 4 and EOB is added. The coded data after that is discarded without being output.

While the above operation is being performed, the same encoding operation is performed on the signal B1 in the encoding circuit 8 and the encoding data is written in the code memory 5. The signal reading from the code memories 4 and 5 is performed by the signal A from the code memory 4 as described in the first embodiment.
Readout of 1 has priority. Then, in the same process, B
1, A2, B2, ...
The data is read and the processing such as marker code insertion, bit stuffing and byte stuffing is performed to obtain the final encoded data. At this time, similarly to the first embodiment, in the code output circuit 6, the code relating to the DC component at the boundary between the areas A and B corresponds to the difference value between the difference from 0 and the DC component of the previous block. Is replaced by.

As described above, even when the code amount control consisting of two passes is performed, the first pass is executed in parallel, and the second pass is also executed in parallel, waiting for the reading of the code memories 4 and 5. This enables high-speed encoding.

The coding circuit 7 described in this embodiment is
8 of course, by stopping the function of truncation of encoding,
It is possible to use it for the operation without the code amount control as shown in the first embodiment without any problem.

Next, the decoding operation in the coding (decoding) device of FIG. 5 will be described with reference to FIG. The input encoded data is Huffman decoding circuits 75 and 85 at the same time.
Entered in. In the decoding circuit 7, the Huffman decoding circuit 75
Then, the Huffman code is sequentially decoded from the beginning of the data, and the quantized difference value of the DC component and the AC component,
Furthermore, by the EOB code or the 64th non-zero coefficient value,
The end of the block can be detected. Here, each time the end of a block appears, the number of blocks is counted in the block counting circuit 76, and the number of blocks from the beginning of the decoded data is obtained. Here, according to the image division shown in FIG. 3, the decoding circuit 7 outputs the data corresponding to the area A.
Data is sent to the subsequent dequantization circuit 77. Here, the DC component is restored and the DC / AC components are inversely quantized (converted to a representative value). The representative value is further sent to the IDCT circuit 78, converted into an image signal, and written in the area A of the image memory 1. After that, the data corresponding to the area B is discarded without being sent to the inverse quantization circuit 77. Therefore, the processing for the data of the area B is only the decoding of the Huffman code,
The processing time can be shortened as compared with the case of performing inverse quantization / IDCT thereafter.

On the other hand, also in the decoding circuit 8, Huffman decoding is similarly performed in the Huffman decoding circuit 85, and only the data corresponding to the area B is counted and selected in the block counting circuit 86. After that, DC component restoration and representative value conversion in the inverse quantization circuit 87 and conversion in the IDCT circuit 88 are performed,
It is written in the area B of the image memory 1. When the above process is performed for all screens, the decoding process for all screens ends. In this way, by performing the decoding process in parallel during the decoding, it is possible to perform the process at high speed.

As described above, the present invention has a remarkable effect in improving the speed of the image data compression processing by combining a plurality of encoding circuits and operating them in parallel.

Although the parallel operation of two sets of encoding circuits has been described in the embodiment, the present invention is not limited to this, and three or more encoding circuits can be operated in parallel according to the principle of the present invention. Is possible. Further, the orthogonal transformation may be DCT, Fourier transformation, Hadamard transformation, or the like. As variable-length coding, arithmetic coding may be used in addition to Huffman coding.

[0043]

As described above in detail, according to the present invention, an image data encoding apparatus and an image data encoding apparatus capable of encoding a large amount of image data in a short processing time. A device can be provided.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an encoding device according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the encoding device shown in FIG.

FIG. 3 is a diagram showing an array of encoded image data.

FIG. 4A and FIG. 4B are diagrams showing the configuration of code data.

FIG. 5 is a circuit configuration diagram of an encoding / decoding device according to a second embodiment of the present invention.

6 is an operation timing chart of the encoding device shown in FIG.

7 is an operation timing chart at the time of decoding by the decoding device shown in FIG.

FIG. 8 is an operation transition diagram of a conventional compression method.

[Explanation of symbols]

1 ... Image memory, 2, 3 ... Encoding circuit, 4, 5 ... Encoding memory, 6 ... Encoding output circuit, 7 ... Encoding (decoding) circuit,
21, 31 ... DCT, 22, 32 ... Quantization circuit, 23,
33 ... Huffman coding circuit.

Claims (3)

[Claims] 1. A plurality of block forming circuits for dividing image data into blocks, a plurality of orthogonal transform circuits for performing orthogonal transform for each of the divided blocks, and a quantizing output of the orthogonal transform for each frequency component. A plurality of quantization circuits, a plurality of variable-length coding circuits that perform variable-length coding on the quantized outputs, a buffer circuit that arranges the outputs of the plurality of variable-length coding circuits into a series of bit strings, and the buffer circuit Image data encoding device comprising an output circuit for outputting the output of each byte. 2. A plurality of block forming circuits for dividing the image data into blocks, a plurality of orthogonal transform circuits for performing an orthogonal transform for each of the divided blocks, and a quantizing output of the orthogonal transform for each frequency component. A plurality of quantization circuits, a plurality of variable length coding circuits that perform variable length coding on the quantized output, a plurality of code amount calculation circuits that calculate the code amount generated in the coding, and a plurality of code amounts A quantization width prediction circuit that predicts an optimum quantization width from the code amount calculated by the calculation circuit, a buffer circuit that arranges the outputs of the plurality of variable length coding circuits in a series of bit strings, and an output of this buffer circuit An image data encoding device having an output circuit for outputting each byte. 3. A plurality of variable length code decoding circuits for decoding the quantized values of the variable length coded DC and AC components, and a plurality of dequantized DC and AC components for the decoded DC and AC components. An inverse quantization circuit, a block determination circuit that obtains a block to be inversely quantized by each inverse quantization circuit from the decoded DC component and AC component, and each block for the inversely quantized DC component and AC component An image data decoding apparatus comprising a plurality of inverse orthogonal transformation means for performing inverse orthogonal transformation.