JPH05226987A - Data detector - Google Patents

Abstract

PURPOSE:To detect data without being affected of jitter of a partial response channel reproduction signal. CONSTITUTION:The detector is provided with computers 15, 16 obtaining positive and negative threshold levels +Ath, -Ath and phases DELTAP+k, DELTAP-k at a cross point of a signal waveform respectively based on two samples Sk, Sk-1 of a channel reproduction signal, phase comparators 17,18 comparing the quantity of the phase at data existing point data Pk with phases DELTAP+k, DELTAP-k at a cross point of a signal waveform respectively, comparators 11, 12, 13 and 14 comparing the quantity of the two samples Sk, Sk-1 and the positive and negative threshold levels +Ath, -Ath and a logic circuit 19 discriminating which of +1, 0, -1 the data of the reproduction signal corresponds based on the outputs of the 6 comparators.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a partial response (hereinafter
The present invention relates to a data detection device for detecting data of a reproduction signal of a channel (referred to as PRS).

[0002]

2. Description of the Related Art FIG. 24 shows an example of a conventional data detection device by analog signal processing. Level comparator 201
Compares the amplitude of the equalized analog reproduction signal S (t) with a positive fixed threshold value + A _th, and outputs a binary signal d ⁺ (t) indicating the comparison result. The level comparator 202 compares the amplitude of the equalized analog reproduction signal S (t) with the negative fixed threshold −A _th, and the binary signal d indicating the comparison result.
^-Output (t). d ⁺ (t) = 1 indicates that the ternary data is +1 at time t, and d ⁻ (t) = 1
Indicates that the ternary data is -1, and d ⁺ (t) =
d ^- (t) = 0 indicates that the 3-value data is 0.
Ignoring the sign of ternary data, that is, modulo 2
The calculated value is the binary record information. In the example of FIG. 24, the outputs of the level comparators 201 and 202 are passed through the OR gate 203 to perform the modulo 2 operation,
Binary record information data is restored. OR gate 204
Is supplied to the D input of the D flip-flop 204.

On the other hand, the equalized analog reproduction signal S
From (t), the analog phase lock loop (hereinafter referred to as “PL
The bit sync clock is regenerated by circuit 205 (referred to as "L"). This synchronous clock is supplied to the clock input of the D-type flip-flop 204, and the restored binary data in synchronization with the synchronous clock is obtained from the output of the D-type flip-flop 204.

[0004]

However, in the above-mentioned conventional data detection device, the phase of the restored data fluctuates due to the jitter of the input PRS channel reproduction signal,
A digital circuit such as a decoder in the subsequent stage is forced to operate according to this fluctuation. Therefore, there are problems that it is particularly difficult to design a circuit that operates at high speed, and that it is difficult to test an LSI circuit.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data detection device capable of detecting the data of a PRS reproduction signal without being affected by the jitter of the PRS channel reproduction signal. To do.

[0006]

A data detecting apparatus according to claim 1 is a data detecting apparatus for detecting data of a PRS channel reproduction signal, wherein (a) is based on amplitude values of two samples of the reproduction signal. Positive crossing phase derivation means (for example, the positive crossing phase ΔP _{+ k} calculator 15 of the embodiment) for obtaining the positive crossing phase which is the phase at the intersection of the signal waveform of the reproduction signal and the positive threshold value, and (b) reproduction Negative crossing phase derivation means (for example, the negative crossing phase ΔP _{-k of the} embodiment) that finds the negative crossing phase that is the phase at the crossing point between the signal waveform of the reproduction signal and the negative threshold value based on the amplitude values of the two samples of the signal. Calculator 16),
(C) A positive cross phase comparison means (for example, the positive cross phase comparator 17 of the embodiment) that compares the positive cross phase with the phase of the data existence point of the reproduction signal and outputs the comparison result, and (d).
Negative crossing phase comparison means (for example, negative crossing phase comparator 18 of the embodiment) that compares the negative crossing phase with the phase of the data existence point of the reproduction signal and outputs the comparison result, and (e) two samples (F) of two samples and a first amplitude comparison means (for example, the first amplitude comparator 11 of the embodiment) that compares the amplitude value of one of the samples with a positive threshold value and outputs the comparison result. Second amplitude comparing means (for example, the second amplitude comparator 12 of the embodiment) that compares the amplitude value of one of the samples with a negative threshold value and outputs the comparison result, and (g) of the two samples. Third amplitude comparison means (for example, the third amplitude comparator 13 of the embodiment) that compares the amplitude value of the other sample of the two with a positive threshold value and outputs the comparison result, and (h) of the two samples Compare the amplitude value of the other sample with a negative threshold, and compare The fourth amplitude comparing means (for example, the fourth amplitude comparator 14 of the embodiment) for outputting, and (i) the positive and negative cross phase comparing means, and the first, second, third and fourth amplitude comparing means. Logic means for judging whether the data of the reproduced signal is +1, 0, or -1 based on the output (for example, the data judgment combinational logic circuit 1 of the embodiment).
9 inverters 21 to 34, OR gates 35 and 3
6 and AND gates 37 to 44)).

A data detecting apparatus according to a second aspect of the present invention is a restoration means for performing a modulo-2 operation on the output of the logic means to restore binary information of a reproduced signal (for example, the O of the embodiment).
An R gate 45) is further provided.

According to another aspect of the data detecting apparatus of the present invention, the positive crossing phase deriving means performs linear interpolation on the basis of the amplitude values of two samples of the reproduced signal to perform an intersection between the signal waveform of the reproduced signal and a positive threshold value. And the negative crossing phase derivation means is the phase at the intersection of the signal waveform of the reproduction signal and the negative threshold value by linear interpolation based on the amplitude values of the two samples of the reproduction signal. The feature is that a negative cross phase is obtained.

[0009]

In the data detector having the structure of claim 1,
The positive crossing phase deriving means obtains the positive crossing phase which is the phase at the intersection of the signal waveform of the reproducing signal and the positive threshold value based on the amplitude values of the two samples of the reproducing signal, and the negative crossing phase deriving means reproduces the signal. Based on the amplitude values of two samples of the signal,
The negative crossing phase, which is the phase of the crossing point between the signal waveform of the reproduction signal and the negative threshold value, is obtained, and the positive crossing phase comparison means compares the positive crossing phase with the phase of the data existence point of the reproduction signal, and the comparison result And the negative cross phase comparison means outputs the negative cross phase,
The phase of the data existence point of the reproduction signal is compared, the comparison result is output, and the first amplitude comparison means compares the amplitude value of one of the two samples with the positive threshold value, and the comparison is made. The second amplitude comparison means outputs a result, the second amplitude comparison means compares the amplitude value of one of the two samples with a negative threshold value, outputs the comparison result, and the third amplitude comparison means outputs the two samples. The amplitude value of the other sample of the two is compared with a positive threshold value, and the comparison result is output.
The amplitude value of the other sample of the one sample is compared with a negative threshold value and a comparison result is output, and the logic means includes positive and negative cross phase comparison means, and first, second and third
Then, based on the output of the fourth amplitude comparison means, it is determined whether the data of the reproduction signal is +1, 0, or -1. Therefore, since all the constituent blocks in the data detection device can be realized by the digital signal processing circuit which operates synchronously with the same fixed clock, the data of the PRS reproduction signal is detected without being affected by the jitter of the PRS channel reproduction signal. it can.

In the data detecting apparatus having the structure of the second aspect, the binary information of the reproduced signal is restored by performing modulo-2 operation on the output of the logic means. Therefore, PR is easy
Binary information of the S channel reproduction signal can be restored.

According to another aspect of the data detecting apparatus of the present invention, the positive crossing, which is the phase of the crossing point between the signal waveform of the reproduced signal and the positive threshold value, is linearly interpolated based on the amplitude values of the two samples of the reproduced signal. The phase is obtained, and based on the amplitude values of the two samples of the reproduction signal, the negative cross phase that is the phase at the intersection of the signal waveform of the reproduction signal and the negative threshold value is obtained by linear interpolation. Therefore, the positive crossing phase and the negative crossing phase can be easily obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the data detecting apparatus of the present invention. Before going into the description of this embodiment, a digital magnetic disk recording / reproducing apparatus which can utilize the present invention will be described.

FIG. 4 is a block diagram showing a digital magnetic disk recording / reproducing apparatus viewed from the flow of data. From the host computer 60 to the hard disk drive (H
DD) When data is recorded in the subsystem 70,
First, data is sent from the host computer 60 to the controller 71 inside the HDD subsystem 70 via the bus interface, and the controller 71 applies this data to a format that can be recorded on a magnetic disk,
Furthermore, by applying modulation that is compatible with the magnetic recording / reproducing channel,
It is sent to the recording amplifier 72. The recording amplifier 72 applies a recording current to the magnetic head inside the head disk assembly 73 to record data. The head disk assembly 73 is a mechanical block including a magnetic disk for recording data, a recording / reproducing head, a head moving mechanism, a spindle motor, and the like.

When reproducing data, in the head disk assembly 73, the recording magnetization pattern on the magnetic disk is read by the magnetic reproducing head, and the reproducing amplifier 7 is used.
4 is amplified as a reproduction signal by the data detection device 75
At, it is converted back to digital data. This digital data is further demodulated by the controller 71 for channel modulation and deformatted, and sent to the host computer 60 via the bus interface.

The present invention can be used in the data detection device 75 of the magnetic recording / reproducing device of FIG.

PR in a digital magnetic recording / reproducing apparatus
The purpose of adopting S (1, 0, -1) is to effectively use the band in the magnetic recording / reproducing channel which is the band limiting channel, and to record / reproduce data at the fastest speed for the same bandwidth ( That is, if it is expressed by the distance in the longitudinal direction on the recording medium, the linear recording density should be increased). PRS (1, 0, -1) positively uses intersymbol interference (interference between isolated reproduced waveforms) that occurs in a band-limited channel.

A data detector 75 that can utilize the present invention.
Is, for example, as shown in FIG.
4 and an analog AGC amplifier 80 which outputs a signal having a constant envelope level and an A / D converter 82 which converts the output signal of the amplifier 80 into a digital signal.
A transversal type equalizer (FIR filter) 82 for equalizing the output signal of the converter 82, and the equalizer 8
The 0 ° phase clock is extracted by receiving the output S _k of 2 and
The digital PLL circuit 83 that outputs the phase data, that is, the phase P _k of the data existing point, and the output of the equalizer 82 and the output of the digital PLL circuit 83, detect the data of the reproduction signal and detect the detected data d _k . And a data detector 84 for outputting.

In the data detection device 75, all circuits after the A / D converter 80 perform digital signal processing.
In addition, the operation speed of data detection is usually 10 Mbits /
It is faster than sec. Therefore, in order to reduce the circuit scale, it is common to use a fixed-point representation of the signal data of each part inside the device, and it is necessary to keep the signal word length to a necessary minimum. However, if the signal word length is shortened, the dynamic range of the signal that can be expressed by each part of the device becomes small, and if there is a large fluctuation in the reproduced signal level, overflow will occur. The analog AGC amplifier 80 keeps the reproduction signal level substantially constant and prevents an overflow inside the data detection device 75.

The A / D converter 81 samples the analog reproduction signal from the AGC amplifier 80 at a sampling frequency f _s that is a constant multiple of the channel bit rate and quantizes it into a predetermined signal word length. A flash A / D converter or the like is used because high-speed operation is required. The example is the simplest case where the sampling frequency f _s is twice the channel bit rate.

The equalizer 82 controls the intersymbol interference due to the band limiting characteristic of the magnetic recording channel, etc., and properly adapts the channel characteristic to PRS (1,0, -1). For example, it can be realized by a digital signal processing circuit using a linear equalizer of transversal type or the like.

The digital PLL circuit 83 is a circuit that synchronizes with the phase P _k of the data existing point based on the signal sample value S _k sampled with a fixed clock. Regarding the digital PLL circuit 83, Japanese Patent Application No. 3-306
No. 643 is disclosed in detail.
The schematic configuration is shown in and only briefly explained.

The instantaneous phase calculator 90 will be described with reference to FIG. The instantaneous phase calculator 90 receives as input the sample value S _k of the PRS channel reproduction signal at the time t = kT _s . The instantaneous phase calculator 90 calculates the signal sample S based on two consecutive signal sample values sampled at a fixed clock asynchronously with the input signal data.
retroactively from the presence time t = kT _s of _k the signal waveform zero cross point in the k-th time slot (candidate of zero-degree phase)
The instantaneous phase ΔP _k which is the time until is output. Units,
It is the number of quantization phases.

The instantaneous phase ΔP _k is the distance from the 0 ° phase having the phase value 0 to the time kT _s , and at the same time t =
It represents which value kT _s has on the phase. Here, on the phase, 360 ° corresponds to a digital value of 2 ^NPLL . Moreover, the time T _s of one time slot width is 18 in phase.
It corresponds to 0 °, and corresponds to 2 ^NPLL-1 when the quantization phase number is a unit.

The instantaneous phase ΔP _k is calculated using (Equation 1), assuming that the signal waveform between two consecutive signal sample values S _k and S _k-1 can be linearly approximated (see FIG. 11). ..

[0025]

[Equation 1]

However, 2 ^NPLL-1 is a phase quantization number for one sample interval. When S _k-1 = S _k , the problem that the denominator becomes 0 occurs, but in reality there is no zero crossing and P
There is no need to calculate ΔP _k because no LL phase update is done.

The instantaneous phase ΔP _k is input to the digital signal processing type PLL circuit 93 via the AND gate 91 as NPLL (5 in the example of FIG. 11) phase data ΔP _k .

Next, the 0 ° phase corresponding instantaneous phase data selection section 92 will be described. The instantaneous phase ΔP _k is always calculated when the signal waveform crosses zero.
Therefore, depending on the channel coding method, it may be calculated at a point where the original data is not in the 0 ° phase. For example, in the case of channel coding showing an eye pattern as shown in FIG. 7, all zero-cross points correspond to 0 ° phase, but as shown in FIG. 8, PRS (1,0,1) showing an eye pattern is displayed. In some cases, other than the 0 ° phase, zero cross may occur in the opposite phase. Therefore,
By some means, only the instantaneous phase calculation output at the true 0 ° phase has to be sorted out. Therefore, for example, in the case of PRS (1, 0, 1), the ternary level predicting unit 92A detects temporary data, and the phase control signal generating unit 92B determines that the phase is 0 ° phase based on the temporary data. The phase control signal modify_P _k is output for the phase ΔP _k . As a result, only the selected instantaneous phase ΔP _k is transferred to the digital signal processing type P P via the AND gate 91.
It becomes possible to supply to LL93.

Next, the digital signal processing type PLL circuit 9
3 will be described. The PLL circuit 93 is a first-order phase locked loop realized by digital signal processing, and the internal phase data P is used to follow the input instantaneous 0 ° phase.
Update _k . Digital signal processing type PLL circuit 9
3 is a digital loop filter 95, an internal phase register 96 that delays the phase data P _k output from the filter 95 by one sampling time interval and outputs internal phase data P _k−1, and is output from this register 96. And the internal phase data P _k−1 that is supplied from the AND gate 91 and the instantaneous 0 ° phase that is supplied from the AND gate 91. The phase update rule is as shown in (Equation 2).

[0030]

[Equation 2]

As shown in FIG. 11, the k-th time slot ((k-1) T _s <t ≦ kT _s ) is 2
^NPLL-1 is virtually divided into one quantization phase. According course of time, each quantized phase value, incrementing modulo (2 ^{N PLL)} (i.e. modulo (2 ^NPLL)). The output phase P _k of the digital PLL circuit 83 is the phase at the sampling time t = kT _s (end time of the k-th time slot), and the phase value at the 0 ° phase time is 0. Therefore, P _k represents the time from the fixed sampling time t = kT _s to the 0 ° phase point (distance in quantized phase unit). By the way, since the sampling rate is twice as high as the channel data rate, 0 ° phase data exists only once every two time slots.
Therefore, the effective signal V _k indicating the presence or absence of 0 ° phase data is generated from the digital PLL circuit 83 according to the following (Equation 3).

[0032]

[Equation 3]

The phase data P _k and the valid signal V _k are the data indicating the position of the 0 ° phase data existing point in the time slot, and are output from the data detection device 75 together with the data detection result d _k .

Next, ternary level detection from the PRS channel reproduction signal waveform will be described by taking PRS (1, -1) as an example. Note that, for simplicity, the influence of noise mixed in the channel or the like is ignored. FIG. 9 shows PRS (1,-
A model of a digital magnetic recording / reproducing system using the method 1) is shown, and FIG. 10 shows an example of the recording / reproducing process. On the recording side, the binary information data a _k is stored in the precoder 10.
1 (the same as the NRZI encoder), the binary channel data b _k is encoded according to the following rule of (Equation 4). Note that addition of binary values is a modulo 2 (that is, modulo 2) operation.

[0035]

[Equation 4]

According to the binary channel data b _k , a recording current i (t) is passed through the magnetic recording medium 102 to record a magnetization pattern m (t). This magnetization pattern m (t)
Is reproduced by the electromagnetic induction reproducing head 103.
The reproducing head 103 has a differential characteristic. Further, in this recording / reproducing process, there is a high frequency loss characteristic of magnetic recording. The output voltage e (t) of the reproducing head 103 is first detected as ternary data c _k by the ternary data detector 104 including a sampler or the like. Then, modulo-2 arithmetic unit 105 performs a modulo 2 operation ignoring the sign of the ternary data c _k, to restore the binary information data a _k of the original.

The principle of ternary data detection is that the signal amplitude value S ₀ in the 0 ° phase is a positive threshold value +
It is to determine which of the three areas divided by A _th and the negative threshold value −A _th .

A data detector 84 according to an embodiment of the present invention.
Cannot obtain an amplitude value as a continuous signal. Therefore, two consecutive signal samples S _k-1 and S _k and the output phase P _k of the digital PLL circuit 83 are used to perform a three-value level comparison using the principle of linear interpolation, and the three-value data c
detect _k .

It is now assumed that the digital PLL circuit 83 knows that the 0 ° phase exists in the k-th time slot. (Actually, with or without 0 ° phase
Data detection is performed in all time slots, and the valid signal V _k output by the digital PLL circuit 83 indicates whether the data in the k-th time slot is meaningful (see Formula 3). )

(A) When both input signal samples S _k-1 and S _k at both ends of the time slot are on the same side of the threshold value (see FIG. 13), at the 0 ° phase point, that is, the data existing point. The input signal level S _{0k is} also on the same side.

(B) When S _k-1 and S _k are on the opposite sides of the threshold value (see FIG. 14), the signal waveform crossing phase (t
= Distance from kT _s to the signal waveform intersection) Δ
P _{+ k} (in case of positive threshold) or ΔP _-k (in case of negative threshold) is calculated by linear interpolation, and its value and phase P
_{The value of k} (distance traced from the time t = kT _s to the 0 ° phase point in the slot) is compared to obtain 0.
It is determined which side of the threshold value the signal S _0k at the phase point is. The determination is a simple level comparison as shown in (Equation 5).

[0042]

[Equation 5]

The signal waveform cross phase by the first-order linear interpolation is
It is calculated by (Equation 6) and (Equation 7) according to the principle of linear interpolation. Here, A _th is the absolute value of the threshold value for ternary level comparison.

[0044]

[Equation 6]

[0045]

[Equation 7]

The calculation principle is the same as that shown in (Equation 1). Positive crossing phase ΔP _{+ k} and negative crossing phase ΔP _-k
As the hardware for calculating, the subtracter and the divider are used to execute (Equation 6) and (Equation 7) as they are, and S _k and S _k-1 are used as address inputs (in this case, input 2's-compliment expression data of signal is regarded as an absolute binary address as it is), and corresponding Δ
This can be realized by preparing a ROM table that outputs P _k and performing table lookup. For example, in the example of FIG.
S _k-1 = 3, S _k = 10, A _th = 5, 2 _NPLL-1 = 16, and ΔP _{+ k} = 11 from (Equation 7). At this time, if the digital PLL circuit 83 gives an instruction that the 0 ° phase is P _k , the following (Equation 8) holds.

[0047]

[Equation 8]

Therefore, the following (formula 9) is established, and the ternary data c _k = + 1 is detected.

[0049]

[Equation 9]

Then, from the following (Equation 10), 1 is output as the original binary record information data.

[0051]

[Equation 10]

FIG. 15 shows the ternary data detection rule when both the sample values S _k-1 and S _k are larger than the positive threshold value + A _th , and FIG. 16 shows the sample value S _k-1 having the negative threshold value. −
Between A _th and the positive threshold value + A _th , and the sample value S
FIG. 17 shows the ternary data detection rule when _k is larger than the positive threshold value + A _th , and FIG. 17 shows that the sample value S _k-1 is the positive threshold value +
A threshold value −A that is larger than A _{t h} and has a negative sample value S _k
FIG. 18 shows a rule for detecting ternary data when it is between _th and a positive threshold value + A _th . FIG. 18 shows that the sample value S _k-1 is a negative threshold value −.
Between A _th and the positive threshold value + A _th , and the sample value S
FIG. 19 shows the ternary data detection rule when _k is between the negative threshold value −A _th and the positive threshold value + A _th .
_k−1 is smaller than the negative threshold −A _th , and the sample value S _k
20 shows the ternary data detection rule when is between the negative threshold value −A _th and the positive threshold value + A _th, and FIG.
_k−1 is between the negative threshold −A _th and the positive threshold + A _th ,
Further, FIG. 21 shows the ternary data detection rule when the sample value S _k is smaller than the negative threshold −A _th .
FIG. 22 shows the ternary data detection rule when both _k−1 and S _k are smaller than the negative threshold −A _th .
_k−1 is smaller than the negative threshold −A _th , and the sample value S _{k
Shows the} ternary data detection rule when is larger than the positive threshold value + A _th , and FIG. 23 shows that the sample value S _k-1 is the positive threshold value + A th.
a threshold value larger than _th and having a negative sample value S _k −A _th
The ternary data detection rule when it is smaller than is shown.

Next, returning to FIG. 1, an embodiment of the data detecting device of the present invention will be described. Input sample S
_k is 5-bit two's complement representation integer data, and
Amplitude comparator 11, second amplitude comparator 12, positive cross phase ΔP
It is supplied to the _{+ k} calculator 15 and the negative cross phase ΔP _−k calculator 16. The 5-bit wide shift register 10 delays the input sample S _k by one sample time to obtain a sample S _k-1.
To generate a third amplitude comparator 13, a fourth amplitude comparator 14,
Positive cross phase ΔP _{+ k} Calculator 15 and negative cross phase ΔP _−k
It is supplied to the calculator 16.

First amplitude comparator 11, second amplitude comparator 1
The second, third amplitude comparator 13 and fourth amplitude comparator 14 are digital magnitude comparators that operate according to the following (Equation 11) and output the comparison result as a 1-bit logical value.

[0055]

[Equation 11]

The first amplitude comparator 11 has an amplitude value of one of the two samples S _k and a positive threshold value + A _th.
Are compared and the comparison result E _{+ k} is output to the combination logic circuit 19 for data determination. The second amplitude comparator 12 compares the amplitude value of one sample S _k of the two samples with the negative threshold value −A _th, and outputs the comparison result E _−k to the data determination combinational logic circuit 19. To do. The third amplitude comparator 13 detects the amplitude value of the other sample S _k−1 of the two samples,
The positive threshold value + A _th is compared, and the comparison result E _{+ (k-1)} is output to the data determination combinational logic circuit 19. The fourth amplitude comparator 14 determines the other sample S _{k−1 of the} two samples.
And the negative threshold value −A _th are compared, and the comparison result E
_-(k-1) is output to the data determination combinational logic circuit 19.

The positive crossing phase ΔP _{+ k} calculator 15 calculates (Equation 6)
Is a ROM memory that stores data obtained according to the above. That is, the positive crossing phase ΔP _{+ k} calculator 15 is the phase at the crossing point of the signal waveform of the reproduced signal and the positive threshold value based on the amplitude values of the two samples S _k and S _k−1 of the reproduced signal. The cross phase ΔP _{+ k} is output. The negative crossing phase ΔP _−k calculator 16 is a ROM memory that stores data obtained according to (Equation 7). That is, the negative crossing phase ΔP
_{The -k} calculator 16 calculates a negative cross phase ΔP _-k , which is the phase at the intersection of the signal waveform of the reproduced signal and the negative threshold value, based on the amplitude values of the two samples S _k and S _k-1 of the reproduced signal. Output.

The positive cross phase comparator 17 and the negative cross phase comparator 18 operate according to (Equation 11), and the comparison result is 1
It is a digital magnitude comparator that outputs as a bit logical value.

The positive cross phase comparator 17 has a positive cross phase ΔP.
_{+ k} is compared with the 0 ° phase data P _k supplied from the digital PLL circuit 83, that is, the phase of the data existence point of the reproduction signal, and the comparison result L ₊ is output to the data determination combinational logic circuit 19. The negative cross phase comparator 18 compares the negative cross phase ΔP _−k with the 0 ° phase data P _k supplied from the digital PLL circuit 83, that is, the phase of the data existence point of the reproduction signal, and the comparison result L ₋ . The data is output to the combination logic circuit 19 for data determination.

The data determining combinational logic circuit 19 includes first, second, third and fourth amplitude comparators 11, 12, and 13.
And output E _{+ k} of _{14, E -k, E + (} k-1) and E _{- (k-1),} and outputs L ₊ and L of the positive and negative cross phase comparator 17 and 18 _- the receiving and , The following (Equation 12)
In accordance therewith, the binary record information data d _k is output. In addition,
In (Equation 12), “+” represents a logical sum, and “·”
Represents the logical product, and the bar above E represents the logical NOT of E.

[0061]

[Equation 12]

FIG. 2 shows a combinational logic circuit 19 for data judgment.
An example of the configuration will be shown. The output E _{+ k} of the first amplitude comparator 11 is
It is supplied to the AND gates 37, 38 and 43, supplied to the AND gate 39 via the inverter 23, and supplied to the AND gate 40 via the inverter 26.

The output E _-k of the second amplitude comparator 12 is AND
The signals are supplied to the gates 39 and 40, supplied to the AND gate 41 via the inverter 28A, supplied to the AND gate 42 via the inverter 30, and supplied to the AND gate 44 via the inverter 33.

The output E _{+ (k-1)} of the third amplitude comparator 13 is A
In addition to being supplied to the ND gates 37, 39 and 44, they are supplied to the AND gate 38 via the inverter 21 and to the AND gate 41 via the inverter 28.

The output E- _(k-1) of the fourth amplitude comparator 14 is A
It is supplied to the ND gates 38 and 41, supplied to the AND gate 40 via the inverter 25, supplied to the AND gate 42 via the inverter 29, and supplied to the AND gate 43 via the inverter 31.
It

The output L ₊ of the positive cross phase comparator 17 is supplied to the AND gate 38 via the inverter 22 and to the AND gate 39 via the inverter 24, and is ORed.
It is supplied to the AND gate 43 via the gate 35 and to the AND gate 44 via the inverter 34 and the OR gate 36.

The output L ₊ of the negative cross phase comparator 18 is AN
It is supplied to the D gate 41, is supplied to the AND gate 40 via the inverter 27, is supplied to the AND gate 43 via the inverter 32 and the OR gate 35, and is supplied to the AND gate 44 via the OR gate 36. ..

The outputs of the AND gates 37 to 44 are the ternary detection data c _k indicating whether the data of the reproduction signal is +1, 0 or -1.

The outputs of the AND gates 37 to 44 are OR
It is supplied to the gate 45. The OR gate 45 performs modulo 2 operation on the ternary detection data c _k to detect the original binary recording information data d _k .

The data detection apparatus shown in FIG. 1 receives 5-bit data S _k , S _k-1 and P _k as inputs,
It can be considered as a table for outputting 1-bit data d _k . Therefore, as shown in FIG. 3, the same shift register 10 as in FIG. 1, a memory 50 (RO having the samples S _k and S _k−1 , and 0 ° phase data P _k as an address input is used.
M, SRAM, or the like), a data detection device having the same function as in FIG. 1 can be configured. The required storage capacity is 2 ¹⁵ =
It is 32768 bits and can be sufficiently realized by the present semiconductor technology.

Although the above embodiment relates to PRS (1, -1), the present invention is not limited to this, and PRS (1) is not limited to this.
It can also be applied to (1, 0, -1).

Further, the present invention can be applied to various devices using a PRS channel such as a digital communication device as well as a digital magnetic recording / reproducing device.

[0073]

According to the data detecting apparatus of the first aspect, the positive crossing phase deriving means, based on the amplitude values of the two samples of the reproduced signal, the phase of the intersection of the signal waveform of the reproduced signal and the positive threshold value. And the negative crossing phase deriving means obtains the negative crossing phase which is the phase at the intersection of the signal waveform of the reproduction signal and the negative threshold value, based on the amplitude values of the two samples of the reproduction signal, The positive cross phase comparison means compares the positive cross phase with the phase of the data existence point of the reproduction signal and outputs a comparison result, and the negative cross phase comparison means compares the negative cross phase with the negative cross phase.
The phase of the data existence point of the reproduction signal is compared, the comparison result is output, and the first amplitude comparison means compares the amplitude value of one of the two samples with the positive threshold value, and the comparison is made. The second amplitude comparison means outputs a result, the second amplitude comparison means compares the amplitude value of one of the two samples with a negative threshold value, outputs the comparison result, and the third amplitude comparison means outputs the two samples. The amplitude value of the other sample of the two is compared with a positive threshold value, and the comparison result is output.
The amplitude value of the other sample of the one sample is compared with a negative threshold value and a comparison result is output, and the logic means includes positive and negative cross phase comparison means, and first, second and third
Since it is determined whether the data of the reproduced signal is +1, 0, or -1, based on the output of the fourth amplitude comparison means, all the constituent element blocks in the data detection device are the same. Since it can be realized by the digital signal processing circuit which operates synchronously with the fixed clock, the data of the PRS reproduction signal can be detected without being affected by the jitter of the PRS channel reproduction signal. Further, the data detection device, the ECC decoder, the controller, the interface circuit, etc., which are conventionally divided and arranged in different chips, can be easily formed on the same LSI chip. Therefore, downsizing and cost reduction of the entire device can be realized. In addition, designing and testing when implementing a large-scale LSI becomes easy. Furthermore, since analog external parts are not required, no adjustment is required and the secular change is small.

According to the data detecting apparatus of the second aspect, since the binary information of the reproduced signal is restored by performing the modulo-2 operation, the binary information of the PRS channel reproduced signal can be easily restored.

According to the data detecting apparatus of the third aspect, the positive crossing phase, which is the phase at the intersection of the signal waveform of the reproduced signal and the positive threshold value, is linearly interpolated based on the amplitude values of the two samples of the reproduced signal. Then, based on the amplitude values of the two samples of the reproduction signal, the negative crossing phase, which is the phase at the intersection of the signal waveform of the reproduction signal and the negative threshold value, is obtained by linear interpolation. Cross phase and negative cross phase can be determined.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data detection device of the present invention.

FIG. 2 is a block diagram showing a configuration example of a data determination combinational logic circuit 19 of FIG.

FIG. 3 is a block diagram showing a configuration example of another embodiment of the data detection device of the present invention.

FIG. 4 is a block diagram showing an example of a digital magnetic disk recording / reproducing apparatus in which the present invention can be used.

5 is a block diagram showing a configuration example of a data detection device 75 of FIG.

6 is a block diagram showing a configuration example of a digital phase lock loop circuit 83 shown in FIG.

FIG. 7 is a waveform diagram showing an example eye pattern in which the zero-cross point of the signal waveform always corresponds to the 0 ° phase. .

FIG. 8 is a waveform diagram showing an eye pattern of an example of a reproduced signal from a PRS (1, 0, -1) channel.

FIG. 9 is a block diagram showing a model of a PRS (1, -1) magnetic recording / reproducing channel.

FIG. 10 is a diagram showing a recording / reproducing example in a PRS (1, -1) magnetic recording / reproducing channel.

11 is a digital phase lock loop circuit 83 of FIG.
3 is an explanatory diagram showing the principle of instantaneous phase detection in FIG.

FIG. 12 is an explanatory diagram showing the principle of ternary data detection.

FIG. 13 is an explanatory diagram showing an example of ternary data detection by primary interpolation.

FIG. 14 is an explanatory diagram showing another example of ternary data detection by primary interpolation.

FIG. 15 is an explanatory diagram showing a ternary data detection rule when both sample values S _k-1 and S _k are larger than a positive threshold value + A _th .

FIG. 16 is a ternary data detection rule when the sample value S _k-1 is between the positive threshold value −A _th and the negative threshold value + A _th , and the sample value S _k is larger than the positive threshold value + A _th. FIG.

FIG. 17 is a ternary data detection rule when the sample value S _k-1 is larger than the positive threshold value + A _th and the sample value S _k is between the negative threshold value −A _th and the positive threshold value + A _th. FIG.

FIG. 18 shows that the sample value S _k−1 is between the negative threshold −A _th and the positive threshold + A _th , and the sample value S _k is between the negative threshold −A _th and the positive threshold + A _th. It is an explanatory view showing a ternary data detection rule when there is.

FIG. 19 shows three-valued data detection when the sample value S _k-1 is smaller than the negative threshold value −A _th and the sample value S _k is between the negative threshold value −A _th and the positive threshold value + A _th. It is explanatory drawing which shows a rule.

FIG. 20: Three-valued data detection when the sample value S _k-1 is between the negative threshold value −A _th and the positive threshold value + A _th , and the sample value S _k is smaller than the negative threshold value −A _th It is explanatory drawing which shows a rule.

FIG. 21 is an explanatory diagram showing a ternary data detection rule when both sample values S _k-1 and S _{k + 3} are smaller than a negative threshold value −A _th .

FIG. 22 is an explanatory diagram showing a ternary data detection rule when the sample value S _k-1 is smaller than the negative threshold value −A _th and the sample value S _k is larger than the positive threshold value + A _th .

FIG. 23 is an explanatory diagram showing a ternary data detection rule when the sample value S _k−1 is larger than the positive threshold value + A _th and the sample value S _k is smaller than the negative threshold value −A _th .

FIG. 24 is a block diagram showing an example of a conventional data detection device.

[Explanation of symbols]

 10 shift register 11 1st amplitude comparator 12 2nd amplitude comparator 13 3rd amplitude comparator 14 4th amplitude comparator 15 positive cross phase calculator 16 negative cross phase calculator 17 positive cross phase comparator 18 negative cross phase comparison Device 19 Combination logic circuit for data determination 21 to 34 Inverters 35, 36, 45 OR gate 37 to 44 AND gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H03L 7/091 H04L 25/497 8226-5K 27/00

Claims (3)

[Claims] 1. A data detection device for detecting data of a partial response channel reproduction signal, comprising: detecting a cross point of a signal waveform of the reproduction signal and a positive threshold value based on amplitude values of two samples of the reproduction signal. A positive crossing phase deriving means for obtaining a positive crossing phase which is a phase, and a negative crossing phase which is a phase at an intersection of the signal waveform of the reproduction signal and a negative threshold value based on the amplitude values of two samples of the reproduction signal. A negative crossing phase deriving means for obtaining, a positive crossing phase comparing means for comparing the positive crossing phase and the phase of the data existence point of the reproduction signal, and outputting a comparison result, the negative crossing phase, and the reproduction signal Of the data existence point, and outputs the comparison result, the negative cross phase comparing means compares the amplitude value of one of the two samples with the positive threshold value, and compares First to output the results
Second amplitude comparing means for comparing the amplitude value of the amplitude comparing means and the amplitude value of one of the two samples with the negative threshold value and outputting a comparison result; and the other sample of the two samples The amplitude value of the third threshold value is compared with the positive threshold value, and a comparison result is output.
A fourth aspect for comparing an amplitude value of the other sample of the two samples with the negative threshold value and outputting a comparison result.
Based on the outputs of the amplitude comparison means, the positive and negative cross phase comparison means, and the first, second, third and fourth amplitude comparison means, the data of the reproduction signal is +1, 0, -1. And a logic means for determining which of the two is a data detection device. 2. A modulo 2 for the output of the logic means.
The data detecting apparatus according to claim 1, further comprising a restoring unit that performs a calculation to restore the binary information of the reproduction signal. 3. The positive crossing phase deriving means is a positive crossing which is a phase at an intersection of a signal waveform of the reproduction signal and a positive threshold value by linear interpolation based on amplitude values of two samples of the reproduction signal. The negative crossing phase derivation means obtains a phase, and the negative crossing phase is a phase at an intersection of a signal waveform of the reproduction signal and a negative threshold value by linear interpolation based on amplitude values of two samples of the reproduction signal. Claim 1 or claim 2 characterized in that
The data detection device described.