JPH05226663A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a floating gate structure of a semiconductor storage device high in reliability of erasing property by removing unnecessary erasure. CONSTITUTION:The surface of the end, made over a drain region 22, of the floating gate 3 of polysilicon being made on a semiconductor substrate 1 such as silicon is flattened, and the surface of the end made over a source region 21 is roughened. Accordingly, the escape of unnecessary charge is prevented when voltage is applied to each area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a stacked gate type non-volatile memory cell, and more particularly to an electrically writable gate structure of a batch erase memory (Flash EEPROM) and its manufacture. It is about the method.

[0002]

2. Description of the Related Art A non-volatile memory is a mask ROM (Re-ROM) that stores data using a mask in the IC chip manufacturing process.
PROM that stores and erases data by voltage / current or ultraviolet rays after manufacturing IC chips
There is (Programmable ROM). Among these PROMs, EPROM (Erasable
and Programmable ROM) and electrically erasable EEPROM
M (Electrically Erasable and Programmable ROM)
Can retain the stored data semi-permanently, and
Since data can be erased and rewritten,
It is widely used in systems for which programs are constructed while considering matching with other systems that are expected to change data, or for firmware of systems in which changes in program specifications are actively incorporated. A conventional erasable EEPROM memory is shown in FIG.
Description will be made with reference to the EPROM. This memory erases all the memory data in the chip at once, and is often used as a program memory such as a microcomputer.

The characteristic of the cell of this type of memory is that a conductive layer such as polysilicon called a floating gate 3 is
It is provided between the control gate 4 and the channel between the source / drain regions 21 and 22 of the semiconductor substrate 1. The floating gate 3 is electrically floating and its periphery is insulated by a coating insulating film 5 such as a silicon oxide film. Therefore, if charges are injected into the floating gate 3 by some means, the charges remain semipermanently. Floating gate
The gate 3 is formed on the channel forming region between the source / drain regions of the semiconductor substrate 1 by thermal oxidation or the like and has a thickness of about 100 Å (hereinafter abbreviated as A). Gate insulating film). The floating gate 3 formed on the first gate insulating film 31 is formed of the first layer of polysilicon. A control gate 4 is formed on the floating gate 3 via a second gate insulating film 41 made of a silicon oxide film or the like. This control
The gate 4 is formed of the second layer of polysilicon. The semiconductor substrate 1 has an insulating film 6 such as a silicon oxide film on its surface.
And a source electrode (S) 7 and a drain electrode (D) 8 which are electrically connected to the source region 21 and the drain region 22, respectively, through the through holes of the insulating film 6. It is formed on the insulating film 6. A gate electrode G, which serves as a data writing electrode used as an electron injection gate, is connected to the control gate 4.

To write data in the memory having such a structure, electrons may be injected into the floating gate 3. The procedure is as follows. First, a high voltage of about 12.5 V is applied to the gate electrode G connected to the control gate 4, and at the same time, a high voltage of about 8 V is applied to the drain electrode 8 connected to the bit line. When biased in this way, some of the electrons accelerated in the pinch-off region near the drain become hot electrons, which are captured by the floating gate 3. The saturation amount of trapped electrons is determined by the potential of the floating gate 3. When the electrons are captured by the floating gate 3, the threshold voltage Vth of the transistor controlled by the control gate 4 rises, and the variation ΔVth of the threshold voltage.
The presence or absence of "1" corresponds to the level of 1 or 0 of data (information).

For reading from the memory cell, a voltage of about 5 V is applied to the gate electrode G, and at the same time, about 2 V is applied to the drain electrode 8. When biased in this way, the hot electrons do not enter the floating gate 3 due to the low voltage of 5 V, and the floating gate 3
The transistor in which no electrons are injected into the transistor turns on, and the read current flows. Data is erased by pulling out electrons from the floating gate 3. For example,
A high voltage of about 0 V is applied to the source electrode G and a high voltage of about 11 to 13 V is applied to the source electrode 7. At this time, due to the potential difference between the floating gate 3 and the source electrode 7, the first gate insulating film 31 is formed.
When the electric field applied to is increased, so-called tunnel current causes electrons to be extracted to the source side.

This memory cell is manufactured by the method shown in FIG. 12 as follows. For example, the insulating film 6 such as SiO ₂ is formed on the surface of the p-type semiconductor substrate 1 by thermal oxidation or the like, and the polycrystalline silicon film 3 is deposited on the surface by the CVD method or the like. On the surface of the polycrystalline silicon film 3, S
An insulating film 41 composed of a layer of iO ₂ , Si ₃ N ₄ or both is formed, and a polycrystalline silicon film 4 is further deposited on the surface thereof. Next, a resist film 9 is formed on the polycrystalline silicon film 4, and the polycrystalline silicon films 3 and 4 and the insulating film 6 are etched by, for example, RIE using the resist film 9 as a mask, and the floating gate 3 and the control gate 4, The floating gate 3 is connected to the insulating film 6.
The lower first gate insulating film 31 and the floating gate
A second gate insulating film 41 is formed between the gate 3 and the control gate 4. The floating gate 3 and the control gate 4 are formed, and the resist film 9 is removed. Then, ions are implanted into the semiconductor substrate through the insulating film 6 to form the source region 21 and the drain region 22,
Ion implantation is also performed under the floating gate 3 between these regions to form a channel region. Then, for example, 9
A coating insulating film 5 is formed on the side surfaces and side surfaces of both gates by high-temperature thermal oxidation at 50 ° C. or higher to cover them. In addition,
Although not shown in the drawing, a field insulating film is previously formed as an element isolation region on the semiconductor substrate. Further, an interlayer insulating film is deposited on the covering insulating film 5 on the control gate 4, and contacts for supplying voltage to the drain / source regions and each gate are opened, and on top of that, contacts are formed. For example, metal wiring made of aluminum is formed.

[0007]

Conventionally, the coating insulating film 5 which coats these gates and brings the floating gate 3 into a floating state is thermally oxidized at a high temperature of 950 ° C. or higher after the gate is formed. Therefore, for example, the unevenness on the surface of the end portion of the floating gate 3 on the source region 21 becomes small, which causes a problem that the erase operation is not performed or the erase operation is insufficient. As mentioned above,
A high voltage is applied to the scanning electrode 7 to cause electrons to flow to the floating gate.
When the electron is extracted from the source 3, the electrons mainly come from the source region 2.
1 from the surface portion of the floating gate end portion provided on top of the No. 1 into the source region. At that time, if the surface is uneven, it is easier to discharge, but if the surface is smooth, the above-mentioned problems occur. On the other hand, at the time of reading or writing, since a voltage is applied to the drain region 22, electrons may escape to the drain region 22 from the surface portion of the end portion of the floating gate 3 provided on the drain region 22. That is, unnecessary erasing may occur at that time, and if the surface portion of the end portion of the floating gate 3 provided on the drain region 22 has many irregularities, the erasing tendency becomes remarkable. The present invention has been made in view of the above circumstances, eliminates unnecessary erasure,
An object of the present invention is to provide a semiconductor memory device including a memory cell having a gate structure with improved reliability of erasing characteristics and a method for manufacturing the same.

[0008]

According to the present invention, a surface portion of a floating gate end portion provided on a drain region of a laminated gate type nonvolatile memory cell is flattened on a source region. The surface part of the end portion of the floating gate provided on the surface is roughened to form large unevenness. That is, the semiconductor memory device of the present invention comprises a semiconductor substrate having a source region and a drain region formed in its surface region, and a polysilicon film formed on this semiconductor substrate via a first gate insulating film. A floating gate, a control gate formed on the floating gate via a second gate insulating film, and the floating gate formed on the semiconductor substrate. And an insulating film formed so as to cover the control gate, and an end surface of the floating gate formed on the drain region is a flat surface. The end surface formed on the source region is characterized by being roughened. The control gate may be composed of a polysilicon film or a polysilicon film and a metal or metal silicide film formed thereon. The second gate insulating film may be formed of a silicon oxide film, or may be formed of a nitride film and a pair of oxide films sandwiching the nitride film. A region having a low impurity concentration can be formed in the source region. The first
The thickness of the gate insulating film at the end on the drain region side can be made larger than that at the end on the source region side.

Also, the method of manufacturing a semiconductor memory device of the present invention has a surface region having a source region and a drain region, and is made of polysilicon formed through a first gate insulating film. A gate and a control formed on the floating gate via a second gate insulating film.
A step of depositing an insulating film on the semiconductor substrate on which the gate and the floating gate are formed, and covering the floating gate and the control gate; Exposing an end surface formed on the source region of the floating gate, and heating the semiconductor substrate at a low temperature to at least expose the source region of the floating gate. A step of forming an insulating oxide film formed at a low temperature on the end surface formed above and roughening the end surface, and partially removing the insulating film not removed by etching, Exposing the end surface of the floating gate formed on the drain region, and heating at least the semiconductor substrate at a high temperature to expose the exposed substrate. A step of forming an insulating oxide film formed at a high temperature on the end surface formed on the drain region of the gate and forming the end surface flat. I am trying.

Further, a floating gate having a source region and a drain region in the surface region and formed of a polysilicon film formed through a first gate insulating film and the floating gate are formed on the floating gate. These floating gates are formed by heating the semiconductor substrate on which the control gate formed through the second gate insulating film is formed at a high temperature.
The control gate and the control gate with an insulating oxide film formed at a high temperature, and the insulating oxide film formed at a high temperature is partially etched to remove at least the source of the floating gate. Exposing the end surface formed on the region, and heating the semiconductor substrate at a low temperature to a low temperature on at least the end surface formed on the source region of the exposed floating gate. The second characteristic is that the insulating oxide film thus formed is formed and the end surface is roughened. The temperature of the high temperature heating is 950 ° C. or higher,
The temperature of the low temperature heating is 900 ° C. or lower.

[0011]

By flattening the surface portion of the end portion of the floating gate provided on the drain region, it is possible to reduce the escape of electrons from the floating gate during reading and writing, and The surface of the end portion of the floating gate provided on the surface is roughened to form large irregularities, thereby improving the reliability of the erasing characteristic.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are drawings for explaining a first embodiment of the present invention, FIG. 1 is a sectional view of a memory cell of a semiconductor memory device according to the present invention, and FIGS. 2 to 4 are manufacturing steps thereof. A sectional view and FIG. 5 are enlarged sectional views of an essential part of FIG. A p-type silicon semiconductor is used for the semiconductor substrate 1. Semiconductor substrate 1
N ⁺ diffusion layers 21 and 22 to be the source region and the drain region 2 are formed in the surface region of the. The floating gate 3 is a silicon oxide film 31 (first gate insulating film) having a thickness of about 100 A formed by thermal oxidation or the like on the channel forming region between the source / drain regions of the semiconductor substrate 1. Is formed through. This first gate insulating film 31
The floating gate 3 formed on the above is formed of the first layer of polysilicon. This floating gate
A control gate 4 is formed on the gate 3 via a second gate insulating film 41 made of a silicon oxide film or the like.
This control gate 4 is a second layer of polysilicon 4
2 and a silicide film 43 such as WSi ₂ or MoSi ₂ formed thereon. Polysilicon film 42
The reason why the silicide film 43 is overlapped with is that the control gate 4 is connected to the word line, and therefore it is necessary to have a low resistance in that part.

The surface of the semiconductor substrate 1 is covered with a surface insulating film 6 such as a silicon oxide film, and although not shown in the drawing, as shown in FIG.
A source electrode and a drain electrode electrically connected to the source region 21 and the drain region 22, respectively, are formed on the surface insulating film 6. A gate electrode, which serves as a data writing electrode used as an electron injection gate, is connected to the control gate 4. Here, looking at the surface states of both gates, both gates show that an insulating oxide film 51 formed at a low temperature (hereinafter referred to as a low temperature oxide film) 51 and an insulating oxide film formed at a high temperature (hereinafter referred to as a high temperature oxidation film). 52)
Is covered by. The insulating film covering these is formed by thermal oxidation, and the heat causes the gate material to
When the material is polysilicon, the exposed surface becomes flat at a high temperature of about 950 ° C or higher, but at a low temperature of about 900 ° C or less, the exposed surface is roughened. Form large irregularities. Therefore,
The surface portions of the end portions of the control gate 4 and the floating gate 3 provided on the drain region 22 are flat because they are subjected to thermal oxidation treatment at high temperature, and the source region 21 is flat.
Control gate 4 and floating gate provided above
Since the surface of the end portion of the grate 3 is subjected to the thermal oxidation treatment at a low temperature, as shown in the enlarged view of FIG. 5, the surface is roughened and large irregularities are formed. With such a structure, in this memory cell, unnecessary charges are eliminated from the floating gate at the time of reading or writing, and at the same time, the charges are rapidly discharged to the source region. The reliability of the erase characteristic is improved because the erase operation is not performed or the erase operation is not insufficient.

Next, the first method of manufacturing the semiconductor memory device of the first embodiment will be described with reference to FIGS. On the p-type silicon semiconductor substrate 1, a thick field oxide film or the like is formed in the well region or the surface of the semiconductor substrate in order to form a peripheral circuit or a memory cell portion of the semiconductor memory device. Since the invention has no direct relationship, it is omitted here. An insulating film 31 made of SiO ₂ and having a thickness of about 100 A is formed on the p-type silicon semiconductor substrate 1.
A polycrystalline silicon film 3 is deposited on it. An insulating film 41 made of SiO ₂ , Si ₃ N _4, or both is formed on the polycrystalline silicon 3, and a polycrystalline silicon film 42 is deposited thereon. On this polycrystalline silicon film 42,
Further, a silicide film 43 such as MoSi ₂ is laminated. A resist film 9 is formed on the silicide film 43, and using the mask as a mask, these stacked bodies are etched by, for example, the RIE method, and the control gate 4, the second gate insulating film 41, and the floating gate 3 are formed. , A first gate insulating film 31 is formed. Then, for example, an n ⁺ diffusion layer is formed by ion implantation and thermal diffusion to form the source region 21 and the drain region 22 (FIG. 2).

After removing the resist film 9, C which covers the floating gate 3 and the control gate 4 is removed.
VDSiO _2, PSG, covering insulating film of a material such as LPDSiO ₂ to precipitate silica supersaturated solution of hydrofluoric acid 5
Deposit. Then, the ends of the control gate 4 and the floating gate 3 provided on the drain region 22 are covered, and the other ends of these gates provided on the source region 21 are exposed. Thus, a resist film 91 is formed on the covering insulating film 5. Then, this resist film 9
Using 1 as a mask, the cover insulating film 5 on the control gate 4 and on the side surfaces of the stacked gates is removed by using, for example, NH ₄ F, and then the resist film 91 is removed. At this time, the surface of the insulating film 6 on the source region 21 which is not masked by the resist film 91 is slightly etched to be thinner than other portions (FIG. 3).

Next, at a low temperature of 900 ° C. or lower in an oxidizing atmosphere, for example, at a temperature of about 800 ° C. to 850 ° C., the surface of the portion where the coating insulating film 5 has been removed is thermally oxidized for about 40 minutes to perform low temperature oxidation. The film 51 is formed on the exposed upper surface and side surface of the laminated gate. At this time, as shown in FIG. 5, the end surfaces of the floating gate 3 and the control gate 4 which are thermally oxidized at a low temperature and located on the source region 21 are roughened to form large irregularities. In the case of this embodiment, the control gate 4 has a structure in which a silicide film 43 such as molybdenum silicide is formed on the polysilicon film 42, so that even if this surface is exposed during the heat treatment. No unevenness is formed. Of course, the thermal oxidation temperature at this time must be higher than the temperature (about 630 ° C.) at which the gate material polysilicon is deposited.

Further, since the end surfaces of the gates covered with the covering insulating film 5 and located on the drain region 22 are protected by the insulating film, they are not affected by the heat treatment. No large unevenness is formed. Then, a resist film 92 is newly formed on the low temperature oxide film 51 and the insulating film 6 on the source region 21. Then, the remaining portion of the covering insulating film 5 formed first is removed by etching with, for example, NH ₄ F using the resist film 92 as a mask. Then, the surface of the gate end portion disposed on the drain region 22 is exposed. At this time, the surface of the insulating film 6 covering the drain region 22 is also slightly etched and thinned (FIG. 4). In this state, a high temperature oxide film 52 is formed by thermally oxidizing the exposed gate surface, which is laminated at a high temperature of 950 ° C. or higher, for example, at about 950 ° C. for about 20 minutes in an oxidizing atmosphere (FIG. 1). ). At this time, since the vicinity of the end surface of the floating gate 3 on the source region 21 is covered with the low temperature oxide film, it is not affected by the high temperature.

Next, referring to FIG. 6 and FIG.
A second manufacturing method of the semiconductor memory device in the embodiment will be described. The source region 21 and the drain region 22 are provided in the surface region, and the first gate insulating film 31 and the floating gate made of polysilicon are provided on the p-type silicon semiconductor substrate 1 whose surface is covered with the insulating film 6. G3, second game
A control gate 4 composed of a gate insulating film 41, a polysilicon film 42 and a molybdenum silicide film 43 is sequentially laminated. The process up to this point is the same as in the first manufacturing method, but next, the semiconductor substrate 1 is heat-treated in an oxidizing atmosphere at a high temperature of 950 ° C. or higher for about 20 minutes to remove the high temperature oxide film 52 from the surface of the semiconductor substrate 1. And the floating gate 3 and the control gate 4 are coated. By this heat treatment, at least the end surface of the floating gate 3 arranged on the source region and the drain region is made flat. Then, a resist film 93 is formed on the semiconductor substrate 1.
To form. The portion of the laminated gate covered with the resist film 93 is the left half of the illustrated laminated gate including at least the end portion of the floating gate 3 disposed on the drain region 22, and the right side thereof. Half is exposed. Then, using the resist film 93 as a mask, the high temperature oxide film 52 on the control gate 4 and on the side surface of the stacked gates is removed by using, for example, NH ₄ F, and then the resist film 93 is removed. .. At this time, the resist film 93
Insulating film 6 on the source region 21 not masked by
The surface is slightly etched and thinner than other parts.

After removing the mask after the etching process, the temperature is kept at a low temperature of 900 ° C. or lower, for example, 80 in an oxidizing atmosphere.
At a temperature of about 0 ° C. to 850 ° C., the surface of the portion where the high temperature oxide film 52 is removed is thermally oxidized for about 40 minutes, and the low temperature oxide film 5 is formed.
1 is formed on the exposed upper and side surfaces of the laminated gate. At this time, as shown in FIG. 5, the end surfaces of the floating gate 3 and the control gate 4 which are thermally oxidized at a low temperature and located on the source region 21 are roughened to form large irregularities. .. In the case of this embodiment, the control gate 4 has a structure in which a silicide film 43 such as molybdenum silicide is formed on the polysilicon film 42, so that even if this surface is exposed during the heat treatment. No unevenness is formed. The thermal oxidation temperature at this time must be higher than the temperature (about 630 ° C.) at which the gate material polysilicon is deposited. Further, since the end surfaces of the gates, which are covered with the high-temperature oxide film 52 and are disposed on the drain region 22, are protected by this oxide film, they are not affected by the heat treatment, and large irregularities are not formed. Not formed.

Next, a second embodiment will be described with reference to FIG. A source region 21 and a drain region 22 are formed on a p-type silicon semiconductor substrate 1, a surface insulating film 6 is formed on the semiconductor substrate 1, and a floating gate 3 made of polysilicon covered with an insulating film is formed. And the control gate 4 are laminated. The insulating film is
The low temperature oxide film 51 covering the gate side and the high temperature oxide film 52 covering the entire gate are the same as in the first method of the first embodiment. Here, the difference from the previous embodiment is that the control gate 4 is made of a polysilicon film and is different from the previous laminated body of the polysilicon film and the silicide film. As described above, the control gate 4 of the present invention is not limited to the material of the above-mentioned embodiment and can be applied not only to the structure of this embodiment, but also to polysilicon. It is also possible to use a laminated body of a film and a refractory metal film such as molybdenum or tungsten. further,
Here, a low impurity concentration n ⁻ region 211 that relaxes the electric field of the source region 21 is formed outside the source region.
This is a so-called LDD (Lightly Doped Drain) structure, which originally relaxes the electric field in the drain region. In this device, a high voltage of about 12 V is applied to the source, so this region is especially provided. It was As a result, it became possible to apply a high voltage of about 13 V to this source region. Of course, it is possible to provide such an n ⁻ region also in the drain region to cope with a high voltage. In this embodiment, the source / drain region has an impurity concentration of, for example, about 6 × 10 ¹⁵ / cm ³ , and the n ⁻ low impurity concentration 211 has an impurity concentration of about 5 × 10 ¹³ / cm 3.
^{Is 3} .

Next, a third embodiment will be described with reference to FIG. The figure is a cross-sectional view of a laminated gate structure portion of a memory cell. The entire structure of the cell is shown in FIG. In the first embodiment shown in FIG. 1, the second gate insulating film 41 formed between the floating gate 3 and the control gate 4 is made of a silicon oxide film. In the embodiment, in order from the bottom, the silicon oxide film (SiO ₂ ) 41
1, a silicon nitride film (Si ₃ N ₄ ) 412, and a silicon oxide film 411. Floating gate
A capacitive division voltage is generated in the gate, and this voltage causes hot electrons to be injected into the floating gate.
In order to increase the voltage and enhance the injection efficiency, it is necessary to increase the capacitance between the floating gate and the control gate. In this embodiment, however, the insulating film 4 between the gates is required. A part of the above is replaced with a silicon oxide film and a silicon nitride film having a higher relative dielectric constant is used to increase the capacitance.

Next, a fourth embodiment will be described with reference to FIG. The figure is a cross-sectional view of a memory cell. The p-type semiconductor substrate 1 is provided with a source region 21, an n ⁻ region 211 and a drain region 22, and the surface of the semiconductor substrate covered with the surface insulating film 6 is covered by a first gate insulating film 31 with a flow. The control gate 4 is formed through the gate 3 and the second gate oxide film 41 on the gate 3, and these gates are covered with the coating insulating film 5. The thickness of the first gate insulating film 31 at the end on the drain region 22 is larger than that at the end on the source region 21. With the miniaturization of LSIs and the like, the gate insulating film is becoming thinner, and as a result, reliability deterioration due to holes generated near the drain is often seen. Can be made effective, and the speed of erasing data can be minimized.

In the present invention, the tendency of roughening formed on the surface of the floating gate also depends on the impurity concentration. For example, in the case of a polysilicon floating gate in which impurities such as phosphorus are diffused, even if heat treatment is performed under the same conditions, the higher the impurity concentration, the larger the unevenness. That is, the concentration of 2 × 10 ²⁰ / cm ³ furo - Tinguge - the concentration of 4~6 × 10 ²⁰ / cm ³ than preparative flow - Tinguge - significantly irregularities is roughened tendency towards bets surface is large Become. Therefore, the impurity concentration of the floating gate is preferably about 2 × 10 ²⁰ / cm ³ or more. However, if the impurity concentration is high, the floating gate is likely to be damaged, so that the concentration cannot be too high.

[0024]

As described above, according to the present invention, since the end surface on the drain region of the floating gate is roughened to form large unevenness, the erase characteristic is improved and it is difficult to erase during the erase operation. It is possible to provide a highly reliable semiconductor memory device in which the occurrence of a problem such as a loss or disappearance is remarkably reduced, and charge loss during writing and reading is reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a first manufacturing process of the semiconductor memory device of FIG.

FIG. 3 is a sectional view of a first manufacturing process of the semiconductor memory device of FIG.

FIG. 4 is a cross-sectional view of a first manufacturing process of the semiconductor memory device of FIG.

FIG. 5 is an enlarged sectional view of an essential part of a gate portion of the semiconductor memory device of the present invention.

6A and 6B are cross-sectional views of a second manufacturing process of the semiconductor memory device of FIG.

FIG. 7 is a sectional view of a second manufacturing step of the semiconductor memory device of FIG.

FIG. 8 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 11 is an explanatory cross-sectional view of a laminated gate type nonvolatile memory cell.

FIG. 12 is a sectional view of a manufacturing process of a conventional semiconductor memory device.

[Explanation of symbols]

1 Semiconductor Substrate 21 Source Region 211 n ^- Region 22 Drain Region 3 Floating Gate 31 First Gate Insulating Film 4 Control Gate 41 Second Gate Insulating Film 411 Silicon Oxide Film 412 Silicon nitride film 42 Polysilicon film 43 Silicide film 5 Covering insulating film 51 Low temperature oxide film 52 High temperature oxide film 6 Surface insulating film 7 Source electrode 8 Gate electrode 9 Resist film 91 Resist film 91 Resist film 92 Resist film 93 Resist film

Claims (8)

[Claims] 1. A floating gate comprising a semiconductor substrate having a source region and a drain region formed on its surface region, and a polysilicon film formed on the semiconductor substrate via a first gate insulating film. A control gate formed on the floating gate via a second gate insulating film, and the floating gate formed on the semiconductor substrate.
And an insulating film formed so as to cover the control gate, and an end surface of the floating gate formed on the drain region is a flat surface. A semiconductor memory device, wherein an end surface formed on the source region is roughened. 2. The semiconductor memory according to claim 1, wherein the control gate comprises a polysilicon film or a composite film of a polysilicon film and a metal or metal silicide film formed thereon. apparatus. 3. The semiconductor memory device according to claim 1, wherein the second gate insulating film comprises a nitride film and a pair of oxide films sandwiching the nitride film. 4. The semiconductor memory device according to claim 1, wherein a region having a low impurity concentration is formed in the source region. 5. The film thickness of the end portion of the first gate insulating film on the side of the drain region is larger than the film thickness of the end portion on the side of the source region. The semiconductor storage device described. 6. A floating gate formed of a polysilicon film having a source region and a drain region in the surface region and formed through a first gate insulating film, and the floating gate. -The insulating film is deposited on the semiconductor substrate on which the control gate formed through the second gate insulating film is formed, and the floating gate and the control gate are formed. A step of partially removing the insulating film by etching to expose at least an end surface of the floating gate formed on the source region, and the semiconductor substrate is cooled to a low temperature. By heating, an insulating oxide film formed at a low temperature is formed on at least the end surface formed on the source region of the exposed floating gate, and the end surface is roughened. Process and By partially etching away the insulating film that has not been removed to expose at least the end surface of the floating gate formed on the drain region; and heating the semiconductor substrate at a high temperature. At least forming an insulating oxide film formed at a high temperature on the end surface formed on the drain region of the exposed floating gate and flattening the end surface. A method of manufacturing a semiconductor device, comprising: 7. A floating gate having a source region and a drain region in the surface region and formed of a polysilicon film formed through a first gate insulating film, and the floating gate.
The floating gate and the control gate are heated by heating the semiconductor substrate on which the control gate formed on the gate and the second gate insulating film is formed at a high temperature. Covering with an insulating oxide film formed at a high temperature, and partially removing the insulating oxide film formed at a high temperature by etching to form an end portion formed at least on the source region of the floating gate. Exposing the surface, and forming an insulating oxide film formed at a low temperature on at least the end surface of the exposed floating gate by heating the semiconductor substrate at a low temperature. And a step of roughening the surface of the end portion. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the high temperature heating temperature is 950 ° C. or higher and the low temperature heating temperature is 900 ° C. or lower. ..