EP0431522B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
EP0431522B1
EP0431522B1 EP90123107A EP90123107A EP0431522B1 EP 0431522 B1 EP0431522 B1 EP 0431522B1 EP 90123107 A EP90123107 A EP 90123107A EP 90123107 A EP90123107 A EP 90123107A EP 0431522 B1 EP0431522 B1 EP 0431522B1
Authority
EP
European Patent Office
Prior art keywords
film
memory cell
region
logic region
volatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP90123107A
Other languages
German (de)
French (fr)
Other versions
EP0431522A2 (en
EP0431522A3 (en
Inventor
Kazuyoshi C/O Intellectual Property Div. Shinada
Masayuki C/O Intellectual Property Div. Yoshida
Takahide C/O Intellectual Property Div. Mizutani
Naoki C/O Intellectual Property Division Hanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0431522A2 publication Critical patent/EP0431522A2/en
Publication of EP0431522A3 publication Critical patent/EP0431522A3/en
Application granted granted Critical
Publication of EP0431522B1 publication Critical patent/EP0431522B1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/138—Roughened surface

Definitions

  • This invention relates to a method for manufacturing a semiconductor device having a non-volatile memory cell region and a logic region including MOS transistors.
  • a gate oxide film is formed over a semiconductor wafer or substrate by thermal oxidization, and then a polysilicon film is deposited on the oxide film.
  • predetermined portions of the memory cell region and logic region are subjected to self-align dry etching, thus forming a memory cell and MOS transistors constituting a logic circuit, respectively.
  • the method of manufacturing a semiconductor device having a non-volatile memory cell region and a logic region including MOS transistors comprises the steps of: forming in succession a first insulating film and a first electrode layer on a semiconductor substrate; removing the first insulating film and first electrode layer which are located in the logic region, without removing the first insulating film and first electrode layer which are located in the non-volatile memory cell region; forming a deposited sacrificial film for insulation over the entire surface in the memory cell region and logic region; and coating a resist film on the sacrificial film; forming an opening in a desired portion of the resist film, and implanting impurity ions into the semiconductor substrate located in the logic region through the opening; removing the resist film and sacrificial film, and forming in succession a second insulating film and a second electrode layer in the non-volatile memory cell region and logic region.
  • the resist film is coated after the sacrificial film is formed over the entire surface of the non-volatile memory cell region and logic region. Subsequently, impurity ions are implanted only into a desired channel region of the logic region, then the resist film and sacrificial film are removed, and a gate oxide film is formed.
  • the traps or the like will not formed in the gate insulating film of the MOS transistors, and also a fluctuation in the gate threshold voltage Vth of the transistor will not occur. Further, part of the resist film, acting as a pollutant, does not remain in the poly-poly insulating film and gate oxide film, which are important elements for the operation of the non-volatile memory cell and MOS transistors. As a result, these films are enhanced in reliability.
  • Figs. 1A - 1F show a semiconductor device having an EPROM and MOS transistors.
  • broken line 21 is a boundary which defines a non-volatile memory cell region 10 and a logic region 11.
  • a first gate oxide film 23 having a thickness of 250 A is formed on a P ⁇ type silicon semiconductor substrate 22 by thermal oxidization. Then, a first polysilicon film 24 is formed on the first gate oxide film 23 by CVD (Chemical Vapor Deposition). Subsequently, those portions of the oxide film 23 and polysilicon film 24 which located in the logic region 11 are removed by CDE (Chemical Dry Etching) or RIE (Reactive Ion Etching).
  • CVD Chemical Vapor Deposition
  • an oxide film 25 having a thickness of 250 ⁇ is deposited by CVD, over the first polysilicon film 24 in the memory cell region 10 and the P ⁇ silicon substrate 22 in the logic region, thereby protecting them from contamination caused by a resist film to be formed later, or ions to be implanted later.
  • the film 25 is a deposited sacrificial oxide film for insulation.
  • a resist film 26 is formed on the oxide film 25, and then an opening is formed in the resist film 26 at a desired location in the logic region 11, through the opening impurity ions are implanted, thereby forming a channel region 27.
  • the oxide film 25 is also removed by etching in NH4F solution, which prevents the material of the resist film from remaining in the semiconductor integrated circuit.
  • Heat process can be applied to the wafer in non-oxidizing atmosphere to electrically activate the impurity ions after removing the resist film 26. If the resist material remains in the circuit, the material is scattered therein during heating etc. performed later, which may deteriorate the quality of the device.
  • a second gate oxide film 28 is formed by thermal oxidization at 900 - 1000°C in the atmosphere of oxygen, and a second polysilicon film 29 having a thickness of 0.4 »m is deposited on the film 28.
  • a second polysilicon film 29 located in the non-volatile memory cell region 10 and the remaining first polysilicon film 24 are subjected to self align dry etching, thereby forming a non-volatile memory cell comprising a control gate 29a and a floating gate 24a.
  • that portion of the second polysilicon film 29 located in the logic region 11 is subjected to dry etching, thereby forming a gate electrode 29b.
  • impurity ions are implanted into the substrate, forming N+ type drain regions 33 and N+ type source regions 34 for the MOS transistors in the logic region 11, and for the EPROM in the non-volatile memory cell region 10, respectively. Thereafter, an oxide film 35 and a passivation film 36 are provided on the chip. Contact holes are formed in the films 35 and 36, through which A1 wiring 37 is formed.
  • the deposited sacrificial oxide film for protecting the first polysilicon film and P ⁇ type silicon semiconductor substrate is formed by CVD, in order that the surface of first polysilicon film 24, which serves as the floating gate 24a of the non-volatile memory cell, may not be oxidized.
  • the sacrificial layer is formed by thermal oxidization (usually performed at 800 - 1000°C)
  • the polysilicon film 24 must be subjected to high heat thermal oxidization twice, which may emphasize the asperity of the surface of the film 24, thereby decreasing the breakdown voltage of a cell and hence the reliability thereof. Consequently, it is more desirable to deposit the sacrificial oxide layer through a process performed at low temperature such that oxidation may be suppressed, than by thermal oxidization performed at high temperature.
  • the sacrificial oxide film is formed by CVD in the embodiment, it can be deposited by any other process, if the process is performed at low temperature. Further, this film can be an insulating film made of a material other than an oxide.
  • the embodiment employs N-channel MOSs, but it can employ P-channel MOSs or complementary MOSs.
  • the present invention can be applied to an EEPROM, a non-volatile memory cell of another type, or a flash EEPROM (which allows one-time erasure of the EEPROM).

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

  • This invention relates to a method for manufacturing a semiconductor device having a non-volatile memory cell region and a logic region including MOS transistors.
  • A conventional method for manufacturing a semiconductor device having a non-volatile memory cell region and a logic region including MOS transistors will now be explained.
  • First, to form a first insulating film and a first polysilicon film in the memory cell region, a gate oxide film is formed over a semiconductor wafer or substrate by thermal oxidization, and then a polysilicon film is deposited on the oxide film.
  • Subsequently, only those portions of the gate oxide film and polysilicon film which are located in the logic region are removed from the wafer. Then, another insulating film is formed all over the wafer by thermal oxidization. A resist film is directly coated on the insulating film. Thereafter, an opening is formed in a desired portion of the resist film, through which impurity ions are implanted into the substrate of the logic region, thereby forming the channel region of a MOS transistor. The resist film is then removed, and a second polysilicon film is deposited over the memory cell region and logic region.
  • Thereafter, predetermined portions of the memory cell region and logic region are subjected to self-align dry etching, thus forming a memory cell and MOS transistors constituting a logic circuit, respectively.
  • However, this method has the following disadvantages:
    • 1. Due to the process of implanting impurity ions into the logic region through the gate oxide film, the gate film is charged with part of the impurity ions, and traps are formed therein. Thus, the gate threshold voltage Vth of the MOSFET is unstable.
    • 2. To implant impurity ions into the channel region of the logic region, the resist film is directly formed on a poly-poly insulating film (an insulating film formed between a floating gate and a control gate) in the non-volatile memory cell region, and on the gate oxide film in the logic region. This causes part of the resist film to remain as a pollutant in the poly-poly insulating film and in the gate oxide film.
  • It is the object of the invention to provide a method for manufacturing a superior semiconductor device having a non-volatile memory cell of high quality, and MOS transistors of high reliability constituting a logic circuit.
  • To attain the object, the method of manufacturing a semiconductor device having a non-volatile memory cell region and a logic region including MOS transistors, comprises the steps of: forming in succession a first insulating film and a first electrode layer on a semiconductor substrate; removing the first insulating film and first electrode layer which are located in the logic region, without removing the first insulating film and first electrode layer which are located in the non-volatile memory cell region; forming a deposited sacrificial film for insulation over the entire surface in the memory cell region and logic region; and coating a resist film on the sacrificial film; forming an opening in a desired portion of the resist film, and implanting impurity ions into the semiconductor substrate located in the logic region through the opening; removing the resist film and sacrificial film, and forming in succession a second insulating film and a second electrode layer in the non-volatile memory cell region and logic region.
  • According to the method, the resist film is coated after the sacrificial film is formed over the entire surface of the non-volatile memory cell region and logic region. Subsequently, impurity ions are implanted only into a desired channel region of the logic region, then the resist film and sacrificial film are removed, and a gate oxide film is formed.
  • This being so, the traps or the like will not formed in the gate insulating film of the MOS transistors, and also a fluctuation in the gate threshold voltage Vth of the transistor will not occur. Further, part of the resist film, acting as a pollutant, does not remain in the poly-poly insulating film and gate oxide film, which are important elements for the operation of the non-volatile memory cell and MOS transistors. As a result, these films are enhanced in reliability.
  • This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
    • Figs. 1A through 1F show a flowchart, useful in explaining a manufacturing method of a semiconductor device according to an embodiment of the present invention.
  • The method of this invention will be explained in detail with reference to the accompanying drawings showing an embodiment thereof.
  • Figs. 1A - 1F show a semiconductor device having an EPROM and MOS transistors. In the figures, broken line 21 is a boundary which defines a non-volatile memory cell region 10 and a logic region 11.
  • Referring first to Fig. 1A, a first gate oxide film 23 having a thickness of 250 A is formed on a P⁻ type silicon semiconductor substrate 22 by thermal oxidization. Then, a first polysilicon film 24 is formed on the first gate oxide film 23 by CVD (Chemical Vapor Deposition). Subsequently, those portions of the oxide film 23 and polysilicon film 24 which located in the logic region 11 are removed by CDE (Chemical Dry Etching) or RIE (Reactive Ion Etching).
  • Thereafter, as is shown in Fig. 1B, an oxide film 25 having a thickness of 250 Å is deposited by CVD, over the first polysilicon film 24 in the memory cell region 10 and the P⁻ silicon substrate 22 in the logic region, thereby protecting them from contamination caused by a resist film to be formed later, or ions to be implanted later. The film 25 is a deposited sacrificial oxide film for insulation.
  • Referring to Fig. 1C, a resist film 26 is formed on the oxide film 25, and then an opening is formed in the resist film 26 at a desired location in the logic region 11, through the opening impurity ions are implanted, thereby forming a channel region 27. After removing the resist film 26, the oxide film 25 is also removed by etching in NH₄F solution, which prevents the material of the resist film from remaining in the semiconductor integrated circuit. Heat process can be applied to the wafer in non-oxidizing atmosphere to electrically activate the impurity ions after removing the resist film 26. If the resist material remains in the circuit, the material is scattered therein during heating etc. performed later, which may deteriorate the quality of the device.
  • Subsequently, as is shown in Fig. 1D, a second gate oxide film 28 is formed by thermal oxidization at 900 - 1000°C in the atmosphere of oxygen, and a second polysilicon film 29 having a thickness of 0.4 »m is deposited on the film 28. Then, as is shown in Fig. 1E, that portion of the second polysilicon film 29 located in the non-volatile memory cell region 10 and the remaining first polysilicon film 24 are subjected to self align dry etching, thereby forming a non-volatile memory cell comprising a control gate 29a and a floating gate 24a. On the other hand, that portion of the second polysilicon film 29 located in the logic region 11 is subjected to dry etching, thereby forming a gate electrode 29b.
  • Referring to Fig. 1F, impurity ions are implanted into the substrate, forming N⁺ type drain regions 33 and N⁺ type source regions 34 for the MOS transistors in the logic region 11, and for the EPROM in the non-volatile memory cell region 10, respectively. Thereafter, an oxide film 35 and a passivation film 36 are provided on the chip. Contact holes are formed in the films 35 and 36, through which A1 wiring 37 is formed.
  • As is described above, the deposited sacrificial oxide film for protecting the first polysilicon film and P⁻ type silicon semiconductor substrate, is formed by CVD, in order that the surface of first polysilicon film 24, which serves as the floating gate 24a of the non-volatile memory cell, may not be oxidized. If the sacrificial layer is formed by thermal oxidization (usually performed at 800 - 1000°C), the polysilicon film 24 must be subjected to high heat thermal oxidization twice, which may emphasize the asperity of the surface of the film 24, thereby decreasing the breakdown voltage of a cell and hence the reliability thereof. Consequently, it is more desirable to deposit the sacrificial oxide layer through a process performed at low temperature such that oxidation may be suppressed, than by thermal oxidization performed at high temperature.
  • Though the sacrificial oxide film is formed by CVD in the embodiment, it can be deposited by any other process, if the process is performed at low temperature. Further, this film can be an insulating film made of a material other than an oxide.
  • Moreover, the embodiment employs N-channel MOSs, but it can employ P-channel MOSs or complementary MOSs. The present invention can be applied to an EEPROM, a non-volatile memory cell of another type, or a flash EEPROM (which allows one-time erasure of the EEPROM).
  • Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims (2)

  1. A method of manufacturing a semiconductor device having a non-volatile memory cell region (10) and a logic region (11) including MOS transistors, characterized by comprising the steps of:
       forming in succession a first insulating film (23) and a first electrode layer (24) on a semiconductor substrate (22);
       removing the first insulating film (23) and first electrode layer (24) which are located in the logic region (11), without removing the first insulating film (23) and first electrode layer (24) which are located in the non-volatile memory cell region (10);
       forming a sacrificial film (25) for insulation over the entire surface in the memory cell region (10) and logic region (11); and coating a resist film (26) on the sacrificial film (25);
       forming an opening in a desired portion of the resist film (26), and implanting impurity ions into the semiconductor substrate (22) located in the logic region (11) through the opening; and
       removing the resist film (26) and sacrificial film (25), and forming in succession a second insulating film (28) and a second electrode layer (29) in the non-volatile memory cell region (10) and logic region (11).
  2. The method according to claim 1, characterized in that the sacrificial film (25) is an insulating film formed by chemical vapor deposition.
EP90123107A 1989-12-06 1990-12-03 Method for manufacturing semiconductor device Expired - Lifetime EP0431522B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP315156/89 1989-12-06
JP1315156A JP2509717B2 (en) 1989-12-06 1989-12-06 Method for manufacturing semiconductor device

Publications (3)

Publication Number Publication Date
EP0431522A2 EP0431522A2 (en) 1991-06-12
EP0431522A3 EP0431522A3 (en) 1991-11-06
EP0431522B1 true EP0431522B1 (en) 1995-02-15

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EP90123107A Expired - Lifetime EP0431522B1 (en) 1989-12-06 1990-12-03 Method for manufacturing semiconductor device

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US (1) US5094967A (en)
EP (1) EP0431522B1 (en)
JP (1) JP2509717B2 (en)
KR (1) KR940002394B1 (en)
DE (1) DE69016955T2 (en)

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US5739569A (en) * 1991-05-15 1998-04-14 Texas Instruments Incorporated Non-volatile memory cell with oxide and nitride tunneling layers
JP3548984B2 (en) * 1991-11-14 2004-08-04 富士通株式会社 Method for manufacturing semiconductor device
JP2924622B2 (en) * 1993-12-28 1999-07-26 日本電気株式会社 Method for manufacturing semiconductor device
US5422292A (en) * 1994-09-30 1995-06-06 United Microelectronics Corp. Process for fabricating split gate flash EEPROM memory
US5631178A (en) * 1995-01-31 1997-05-20 Motorola, Inc. Method for forming a stable semiconductor device having an arsenic doped ROM portion
US6043123A (en) * 1996-05-30 2000-03-28 Hyundai Electronics America, Inc. Triple well flash memory fabrication process
US6330190B1 (en) 1996-05-30 2001-12-11 Hyundai Electronics America Semiconductor structure for flash memory enabling low operating potentials
US5861650A (en) * 1996-08-09 1999-01-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising an FPGA
US6265266B1 (en) * 1996-09-27 2001-07-24 Xilinx, Inc. Method of forming a two transistor flash EPROM cell
JP3466851B2 (en) * 1997-01-20 2003-11-17 株式会社東芝 Semiconductor device and manufacturing method thereof
US6190966B1 (en) * 1997-03-25 2001-02-20 Vantis Corporation Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
KR100400764B1 (en) * 1997-12-29 2003-12-24 주식회사 하이닉스반도체 Method for forming dual gate of semiconductor device
US6015730A (en) * 1998-03-05 2000-01-18 Taiwan Semiconductor Manufacturing Company Integration of SAC and salicide processes by combining hard mask and poly definition
TW390028B (en) * 1998-06-08 2000-05-11 United Microelectronics Corp A flash memory structure and its manufacturing
KR20000003475A (en) * 1998-06-29 2000-01-15 김영환 Production method for memory device
KR100318320B1 (en) * 1999-05-10 2001-12-22 김영환 Method for fabricating semiconductor device
US7573095B2 (en) * 2006-12-05 2009-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Memory cells with improved program/erase windows
US7652923B2 (en) * 2007-02-02 2010-01-26 Macronix International Co., Ltd. Semiconductor device and memory and method of operating thereof
KR100835430B1 (en) * 2007-05-21 2008-06-04 주식회사 동부하이텍 Method for forming dual gate electrode of semiconductor device
CN108807397A (en) * 2018-05-31 2018-11-13 武汉新芯集成电路制造有限公司 A method of improving grid hole defect

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Also Published As

Publication number Publication date
KR910013483A (en) 1991-08-08
DE69016955T2 (en) 1995-07-20
DE69016955D1 (en) 1995-03-23
EP0431522A2 (en) 1991-06-12
KR940002394B1 (en) 1994-03-24
US5094967A (en) 1992-03-10
EP0431522A3 (en) 1991-11-06
JPH03177064A (en) 1991-08-01
JP2509717B2 (en) 1996-06-26

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