JPH05226579A - Heat-conducting substrate, semiconductor device using the heat-conducting substrate and manufacture of heat-conducting substrate - Google Patents
Heat-conducting substrate, semiconductor device using the heat-conducting substrate and manufacture of heat-conducting substrateInfo
- Publication number
- JPH05226579A JPH05226579A JP4059385A JP5938592A JPH05226579A JP H05226579 A JPH05226579 A JP H05226579A JP 4059385 A JP4059385 A JP 4059385A JP 5938592 A JP5938592 A JP 5938592A JP H05226579 A JPH05226579 A JP H05226579A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- type semiconductor
- heat transfer
- heat
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000000758 substrate Substances 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title description 12
- 230000002093 peripheral effect Effects 0.000 claims abstract description 29
- 230000005679 Peltier effect Effects 0.000 claims abstract description 13
- 238000012546 transfer Methods 0.000 claims description 45
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 239000010410 layer Substances 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000000945 filler Substances 0.000 claims description 9
- 239000010409 thin film Substances 0.000 abstract description 33
- 239000010408 film Substances 0.000 abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 229910008310 Si—Ge Inorganic materials 0.000 abstract 3
- 150000002500 ions Chemical class 0.000 abstract 2
- 239000012790 adhesive layer Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910000846 In alloy Inorganic materials 0.000 description 2
- FCDCNUKQQLSMMN-UHFFFAOYSA-N [GeH4].[Si] Chemical compound [GeH4].[Si] FCDCNUKQQLSMMN-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体基板の構造、詳
しくは半導体素子を利用した伝熱基板および半導体装置
および伝熱基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor substrate, and more particularly to a heat transfer substrate using a semiconductor element, a semiconductor device and a method for manufacturing the heat transfer substrate.
【０００２】[0002]
【従来の技術】トランジスタ層が縦方向に積層されてい
る多層構造デバイスを作成する方法の一つとして、ＣＵ
ＢＩＣ（Ｃｕｍｕｌａｔｉｖｅｌｙ Ｂｏｎｄｅｄ Ｉ
Ｃ）技術が知られている（林ら、Ｓｅｍｉｃｏｎｄｕｃ
ｔｏｒ Ｗｏｒｌｄ １９９０．９，ｐｐ５８〜６４参
照）。2. Description of the Related Art A CU is one of the methods for producing a multi-layer structure device in which transistor layers are vertically stacked.
BIC (Cumulatively Bonded I)
C) Technology is known (Hayashi et al., Semiconduc
tor World 1990.9, pp 58-64.).
【０００３】図１２に、ＣＵＢＩＣ技術による３次元Ｌ
ＳＩ形成スループロセスの工程断面図を示す。図におい
て、まず、通常のＬＳＩプロセスを利用してバルクシリ
コン基板１上に、ＭＯＳＦＥＴからなる集積回路を形成
し、さらに選択ＣＶＤ法を利用してＭＯＳＦＥＴのＭｏ
Ｓｉ2／Ａｌ配線２１上にタングステンバンプ２２を形
成する（図１２（ａ））。FIG. 12 shows a three-dimensional L based on CUBIC technology.
The process sectional drawing of SI formation through process is shown. In the figure, first, an integrated circuit composed of a MOSFET is formed on the bulk silicon substrate 1 by using a normal LSI process, and then Mo of the MOSFET is formed by using a selective CVD method.
A tungsten bump 22 is formed on the Si 2 / Al wiring 21 (FIG. 12A).
【０００４】このタングステンバンプ２２は、デバイス
／デバイス間の接続電極として用いる。その後、ＭＯＳ
ＦＥＴ形成面側に絶縁性のポリイミドを塗布し、その接
着層１５を介して支持基板１４に接着する。次に、ＭＯ
ＳＦＥＴの形成されたシリコン基板１の裏面より、選択
ポリッシングを行い、薄膜構造のＮＭＯＳＦＥＴを得る
（図１２（ｂ））。This tungsten bump 22 is used as a connection electrode between devices. Then MOS
Insulating polyimide is applied to the FET formation surface side and adhered to the support substrate 14 via the adhesive layer 15. Next, MO
Selective polishing is performed from the back surface of the silicon substrate 1 on which the SFET is formed to obtain an NMOSFET having a thin film structure (FIG. 12B).
【０００５】選択ポリッシングでは、シリコンの加工速
度に対してシリコン酸化物の加工速度が１０００分の１
程度となるような加工液を用いる。このため、ＭＯＳＦ
ＥＴのＬＯＣＯＳ酸化膜２の裏面まで加工面が達する
と、加工速度が著しく遅くなり、薄膜構造ＭＯＳＦＥＴ
（厚さ：１μｍ〜２μｍ）あるいは薄膜集積回路１７を
得ることができる。In selective polishing, the processing speed of silicon oxide is 1/1000 of the processing speed of silicon.
Use a working fluid that provides a degree. Therefore, MOSF
When the processed surface reaches the back surface of the LOCOS oxide film 2 of ET, the processing speed becomes remarkably slow, and the thin film structure MOSFET
(Thickness: 1 μm to 2 μm) or the thin film integrated circuit 17 can be obtained.
【０００６】次に、薄膜構造ＭＯＳＦＥＴ１７の表面側
（ここでは、ｎ＋ｐｏｌｙ−Ｓｉ配線２３あるいはＭｏ
Ｓｉ2／Ａｌ配線２１に流れる電気信号を薄膜構造ＮＭ
ＯＳＦＥＴ裏面側に接続することを目的として、薄膜集
積回路１７の裏面より、ＬＯＣＯＳ酸化膜上に形成され
たポリシリ配線層２３に至るスルーホール２４および裏
面配線２５を形成する（図１２（ｃ））。Next, the surface side of the thin film structure MOSFET 17 (here, n + poly-Si wiring 23 or Mo is used).
The electric signal flowing through the Si 2 / Al wiring 21 is transferred to the thin film structure NM.
A through hole 24 and a backside wiring 25 are formed from the backside of the thin film integrated circuit 17 to the polysilicon wiring layer 23 formed on the LOCOS oxide film for the purpose of connecting to the backside of the OSFET (FIG. 12C). ..
【０００７】さらに、裏面側デバイス接続極として、接
着層１５のポリイミド膜にＡｕ／Ｉｎ合金が埋め込まれ
た構造を有するＡｕ／Ｉｎプール２６を形成する。な
お、Ａｕ／Ｉｎプール２６は、裏面Ｗ／Ａｌ配線２５，
スルーホール２４，ポリシリ配線２３，ＭｏＳｉ2／Ａ
ｌ配線２１を介して、薄膜集積回路１７の表面に形成さ
れているタングステンバンプ２２と、電気的に接続され
ていることに注意されたい。Further, an Au / In pool 26 having a structure in which a polyimide film of the adhesive layer 15 is filled with an Au / In alloy is formed as a back surface side device connecting electrode. Note that the Au / In pool 26 includes the back surface W / Al wiring 25,
Through hole 24, polysilicon wiring 23, MoSi 2 / A
It should be noted that it is electrically connected to the tungsten bump 22 formed on the surface of the thin film integrated circuit 17 via the 1 wiring 21.
【０００８】次に、薄膜構造ＭＯＳＦＥＴあるいは薄膜
集積回路１７を単位として、順次デバイスをボンディン
グしてゆく。ここでは、赤外線顕微鏡を用い、下層デバ
イス１６のＭＯＳＦＥＴ表面に形成されているタングス
テンバンプ２２と、上層デバイスである薄膜構造ＭＯＳ
ＦＥＴ裏面に形成されているＡｕ／Ｉｎプール２６との
位置合わせを行う（図１２（ｄ））。Next, the devices are sequentially bonded using the thin film structure MOSFET or the thin film integrated circuit 17 as a unit. Here, using an infrared microscope, the tungsten bumps 22 formed on the MOSFET surface of the lower layer device 16 and the thin film structure MOS that is the upper layer device are used.
The alignment with the Au / In pool 26 formed on the back surface of the FET is performed (FIG. 12D).
【０００９】位置合わせ後、Ａｕ／Ｉｎ合金が溶融する
温度以上に試料を昇温・加圧し、溶融状態のＡｕ／Ｉｎ
プールにタングステンバンプを挿入させ、“ろう着”に
よるデバイス接続縦配線２７にて下層デバイスと、上層
デバイスとが電気的に接続される（図１２（ｅ））。最
後に、支持基板１４をエッチングにより除去することに
より、薄膜集積回路１７が積層された多層構造ＩＣを得
ている（図１２（ｆ））。After the alignment, the sample is heated and pressurized to a temperature above the melting temperature of the Au / In alloy, and Au / In in the molten state is pressed.
Tungsten bumps are inserted into the pool, and the lower layer device and the upper layer device are electrically connected by the device connection vertical wiring 27 by "brazing" (FIG. 12E). Finally, the support substrate 14 is removed by etching to obtain a multi-layer structure IC in which the thin film integrated circuits 17 are stacked (FIG. 12 (f)).
【００１０】[0010]
【発明が解決しようとする課題】かかる手段によって複
数の薄膜構造デバイスが積層された多層構造ＩＣを得る
ことができるわけであるが、一般に多層構造ＩＣの周辺
部には、熱伝導性の良い金属材料で入出力金属電極パッ
ドや金属縦配線（電源線やバス信号線）が形成してあ
り、かつ発熱源であるトランジスタ素子密度が低い。By such means, it is possible to obtain a multilayer structure IC in which a plurality of thin film structure devices are laminated. Generally, a metal having good thermal conductivity is provided around the periphery of the multilayer structure IC. Input / output metal electrode pads and metal vertical wirings (power supply lines and bus signal lines) are formed of a material, and the density of transistor elements that are heat sources is low.
【００１１】一方、多層構造ＩＣ中心部は、トランジス
タ密度が高く、かつ各薄膜構造デバイス層は、熱伝導性
の悪いポリイミド樹脂接着層で上面あるいは下面が覆わ
れているため、温度上昇が顕著になる。このため、トラ
ンジスタの正常動作が阻害されるといった問題点があっ
た。On the other hand, in the central part of the multi-layered structure IC, the transistor density is high, and in each thin film structure device layer, the upper surface or the lower surface is covered with the polyimide resin adhesive layer having poor thermal conductivity, so that the temperature rise remarkably. Become. Therefore, there is a problem that the normal operation of the transistor is hindered.
【００１２】本発明の目的は、ＩＣの中心部に蓄積され
た熱を熱伝導性の良い周辺部に移動させるための構造お
よびその製造方法を提供することにある。An object of the present invention is to provide a structure for moving heat accumulated in the central part of an IC to a peripheral part having good thermal conductivity, and a manufacturing method thereof.
【００１３】[0013]
【課題を解決するための手段】上記目的を達成するた
め、本発明による伝熱基板においては、ｎ型半導体素子
領域とｐ型半導体素子領域との複数の接合対を有する伝
熱基板であって、ｎ型半導体素子領域と、ｐ型半導体素
子領域との接合対は基板の中心部より周辺部へ向けてペ
ルチェ効果により熱移動を生じさせるものである。In order to achieve the above object, a heat transfer substrate according to the present invention is a heat transfer substrate having a plurality of junction pairs of an n-type semiconductor element region and a p-type semiconductor element region. , The junction pair of the n-type semiconductor element region and the p-type semiconductor element region causes heat transfer from the central portion of the substrate toward the peripheral portion by the Peltier effect.
【００１４】また、伝熱基板は、２μｍ〜５０μｍ程度
の厚さを有するものである。The heat transfer substrate has a thickness of about 2 μm to 50 μm.
【００１５】本発明による半導体装置においては、集積
回路基板と伝熱基板とが交互に積層され、周辺部に層間
接続縦配線，埋め込み金属フィラーを有する多層構造の
積層半導体装置であって、集積回路基板は、薄膜化され
たものであり、伝熱基板は、ｎ型半導体素子領域とｐ型
半導体素子領域との複数の接合対を有し、基板の中心部
より周辺部に向けてペルチェ効果により熱移動を生じさ
せるものであり、層間接続縦配線、あるいは埋め込み金
属フィラーは、各層の伝熱基板上で周辺部に移動した熱
を放熱させるものである。In the semiconductor device according to the present invention, an integrated circuit substrate and a heat transfer substrate are alternately laminated, and a multilayer semiconductor device having a multilayer structure having interlayer connection vertical wiring and a buried metal filler in the peripheral portion, The substrate is a thin film, and the heat transfer substrate has a plurality of junction pairs of an n-type semiconductor element region and a p-type semiconductor element region, and is formed by the Peltier effect from the central portion of the substrate toward the peripheral portion. The heat transfer is generated, and the interlayer connection vertical wiring or the embedded metal filler radiates the heat transferred to the peripheral portion on the heat transfer substrate of each layer.
【００１６】本発明による伝熱基板の製造方法において
は、基板の表面に形成された絶縁膜に複数個の凹部を形
成する工程と、前記凹部にｐ型半導体およびｎ型半導体
を埋め込む工程と、前記ｐ型半導体と前記ｎ型半導体と
を金属配線で接続する工程とを有するものである。In the method of manufacturing a heat transfer substrate according to the present invention, a step of forming a plurality of recesses in the insulating film formed on the surface of the substrate, a step of embedding a p-type semiconductor and an n-type semiconductor in the recesses, And a step of connecting the p-type semiconductor and the n-type semiconductor with a metal wiring.
【００１７】[0017]
【作用】本発明に係る伝熱基板構造では、ペルチェ効果
を利用する複数の半導体素子対が基板中央部より周辺部
に熱が移動するように配置されている。この伝熱基板を
薄膜化しても半導体素子の特性に影響を及ぼさない範囲
内であれば、基板中央部から周辺部への熱移動効果が損
なわれることはない。In the heat transfer substrate structure according to the present invention, a plurality of semiconductor element pairs utilizing the Peltier effect are arranged so that heat is transferred from the central portion of the substrate to the peripheral portion. Even if the heat transfer substrate is thinned, the effect of heat transfer from the central portion of the substrate to the peripheral portion is not impaired as long as it does not affect the characteristics of the semiconductor element.
【００１８】この薄膜伝熱基板と薄膜集積回路基板とを
ポリイミドを用いて張り合わせ積層するとしても、得ら
れた積層半導体装置の中央部から周辺部への熱移動が可
能であり、さらに積層構造半導体装置の周辺部に形成し
てある層間金属縦配線や埋め込み金属フィラーを介して
効率良く外界に放熱させることが可能となる。Even if the thin film heat transfer substrate and the thin film integrated circuit substrate are laminated by using polyimide, heat transfer from the central portion to the peripheral portion of the obtained laminated semiconductor device is possible, and the laminated semiconductor It is possible to efficiently dissipate heat to the outside through the inter-layer metal vertical wiring and the embedded metal filler formed in the peripheral portion of the device.
【００１９】本発明による積層構造半導体装置において
は、薄膜集積回路基板を熱伝導性の悪い有機接着材を用
いて張り合わせ積層したとしても、回路動作による発熱
を効率よく外界に放熱させることができる。In the laminated structure semiconductor device according to the present invention, even if the thin film integrated circuit substrates are laminated by using an organic adhesive having poor thermal conductivity, the heat generated by the circuit operation can be efficiently radiated to the outside.
【００２０】[0020]
【実施例】以下に本発明の実施例を図によって説明す
る。実施例として、まずペルチェ効果を示す半導体対と
して、ｐ型シリコン・ゲルマ（Ｓｉ−Ｇｅ）とｎ型シリ
コン・ゲルマ半導体対を利用した伝熱基板について説明
する。Embodiments of the present invention will be described below with reference to the drawings. As an example, first, a heat transfer substrate using a p-type silicon-german (Si-Ge) and an n-type silicon-german semiconductor pair as a semiconductor pair showing the Peltier effect will be described.
【００２１】表１に、Ｓｉ−Ｇｅ系材料の熱電特性を示
す（村上 欣一および西田 勲夫，“熱電半導体とその
応用”，日刊工業新聞社，ＩＳＢＮ４−５２６−０２４
５４−６ Ｃ３０ ５５，ｐｐ１７５参照）。Table 1 shows the thermoelectric properties of Si-Ge materials (Kinichi Murakami and Isao Nishida, "Thermoelectric semiconductors and their applications", Nikkan Kogyo Shimbun, ISBN4-526-024.
54-6 C30 55, pp175).
【００２２】[0022]
【表１】 [Table 1]
【００２３】Ｓｉ−Ｇｅ系材料のボロンあるいはリン等
の不純物を添加してｐ型半導体化あるいはｎ型半導体化
し、電流がｎ型半導体素子領域からｐ型半導体素子領域
に配線を施すことによりペルチェ効果により熱移動が生
じるわけである。A Peltier effect is obtained by adding an impurity such as boron or phosphorus of a Si-Ge-based material into a p-type semiconductor or an n-type semiconductor, and applying a wiring from the n-type semiconductor element region to the p-type semiconductor element region. This causes heat transfer.
【００２４】図１に示すがごとく、Ｓｉ基板１上にシリ
コン酸化膜２が形成され、そのｎ型半導体素子領域３に
おいては、基板周辺部から中心に向かって電流が流れ、
かつｐ型半導体素子領域４においては、中心部から周辺
部に向かって電流７が流れるように半導体素子領域を設
置し、配線５を施すことにより、基板中心部から周辺部
に矢印で示すように熱流束６が生じる。As shown in FIG. 1, a silicon oxide film 2 is formed on a Si substrate 1. In the n-type semiconductor element region 3, a current flows from the peripheral portion of the substrate toward the center,
In addition, in the p-type semiconductor element region 4, the semiconductor element region is installed so that the current 7 flows from the central portion to the peripheral portion, and the wiring 5 is provided so that the central portion of the substrate is surrounded by the peripheral portion as indicated by an arrow. Heat flux 6 occurs.
【００２５】すなわち、図１に示した半導体装置は、中
心部から周辺部への熱流束６を生じさせる伝熱基板とな
る。That is, the semiconductor device shown in FIG. 1 serves as a heat transfer substrate for generating the heat flux 6 from the central portion to the peripheral portion.
【００２６】図２から図７に、図１に示した構造を有す
る伝熱基板を形成するための工程を示す。まず、シリコ
ン基板１にシリコン酸化膜２を形成し（図２）、シリコ
ン酸化膜２にエッチングにより凹部８を形成する（図
３）。2 to 7 show steps for forming the heat transfer substrate having the structure shown in FIG. First, the silicon oxide film 2 is formed on the silicon substrate 1 (FIG. 2), and the recesses 8 are formed in the silicon oxide film 2 by etching (FIG. 3).
【００２７】基板表面に蒸着法等によりＳｉ−Ｇｅ膜９
を堆積し（図４）、凹部８以外の酸化膜２上のＳｉ−Ｇ
ｅ膜をフォトリソグラフィー工程と、エッチング工程に
より除去して前記凹部８にＳｉ−Ｇｅを埋め込む。The Si-Ge film 9 is formed on the surface of the substrate by vapor deposition or the like.
Is deposited (FIG. 4), and Si-G on the oxide film 2 other than the recess 8 is deposited.
The e film is removed by a photolithography process and an etching process to fill the recess 8 with Si—Ge.
【００２８】なお、このＳｉ−Ｇｅ膜の埋め込み構造を
得る方法として、酸化膜２上のＳｉ−Ｇｅ膜９をポリッ
シングにより除去する方法を用いても良い。しかる後、
レジスト１０によるフォトマスクを用いて複数個の埋め
込みＳｉ−Ｇｅ領域の内、その半数個の領域にボロンを
イオン注入してｐ型半導体素子領域４とし（図５）、残
りの半数個の領域にリンをイオン注入してｎ型半導体素
子領域３とする（図６）。As a method of obtaining the embedded structure of the Si-Ge film, a method of removing the Si-Ge film 9 on the oxide film 2 by polishing may be used. After that,
Of the plurality of embedded Si-Ge regions, a half of the plurality of embedded Si-Ge regions is ion-implanted into p-type semiconductor element regions 4 (FIG. 5) using the photomask formed by the resist 10, and the remaining half of the regions are formed. Phosphorus is ion-implanted to form the n-type semiconductor element region 3 (FIG. 6).
【００２９】層間絶縁膜１１を堆積した後、コンタクト
ホール１２およびアルミ配線５を通常のフォトリソグラ
フィーおよびドライエッチングにより形成する（図
７）。After depositing the interlayer insulating film 11, the contact hole 12 and the aluminum wiring 5 are formed by ordinary photolithography and dry etching (FIG. 7).
【００３０】なお、層間絶縁膜１１および素子分離酸化
膜２の熱抵抗を下げるため、それらの厚さをそれぞれ
０．５μｍ〜２μｍ程度と十分に薄膜化することが望ま
しい。In order to reduce the thermal resistance of the interlayer insulating film 11 and the element isolation oxide film 2, it is desirable that the thickness of each of them be made as thin as 0.5 μm to 2 μm.
【００３１】図７は、図１に示した伝熱基板の断面構造
図であるが、実際にペルチェ効果を利用して熱移動を生
じさせている領域は、厚さ数百ミクロンを有するシリコ
ン基板１上のｐ型半導体素子領域４およびｎ型半導体素
子領域３が形成されている表面層のみである。FIG. 7 is a sectional structural view of the heat transfer substrate shown in FIG. 1. The region where heat is actually transferred utilizing the Peltier effect is a silicon substrate having a thickness of several hundreds of microns. 1 only on the surface layer on which the p-type semiconductor element region 4 and the n-type semiconductor element region 3 are formed.
【００３２】従って、下地シリコン基板１を除去するこ
とにより、より効率の高い薄膜熱伝導基板とすることが
できる。図８に、下地シリコン基板１を研磨あるいはエ
ッチングにより除去することにより、厚さを２μｍから
５０μｍとした薄膜伝熱基板１３を示す。ここでは、ｐ
型半導体４およびｎ型半導体３の素子分離酸化膜２下に
シリコン基板１の一部を残した場合を示したが、図９に
示すがごとく、全てのシリコン基板を除去しても良い。
ただし、この場合、機械的補強を目的として伝熱基板を
支持基板１４に接着層１５を介して接着した後、伝熱基
板を薄膜化する必要がある。Therefore, by removing the base silicon substrate 1, a highly efficient thin film heat conduction substrate can be obtained. FIG. 8 shows a thin film heat transfer substrate 13 having a thickness of 2 μm to 50 μm by removing the base silicon substrate 1 by polishing or etching. Here, p
Although the case where a part of the silicon substrate 1 is left under the element isolation oxide film 2 of the type semiconductor 4 and the n-type semiconductor 3 is shown, as shown in FIG. 9, all the silicon substrates may be removed.
However, in this case, it is necessary to reduce the thickness of the heat transfer substrate after the heat transfer substrate is bonded to the support substrate 14 via the adhesive layer 15 for the purpose of mechanical reinforcement.
【００３３】図１０（ａ）に、集積回路１６の形成され
ているシリコン基板１に、薄膜伝熱基板１３と、薄膜集
積回路１７とを絶縁性接着層１５を介して張り合わせた
積層構造半導体装置の断面図を示す。薄膜集積回路１７
は、従来の技術を示す図１２に示したように、集積回路
が形成されてシリコン基板を選択ポリッシング法により
薄膜化することにより得られる。FIG. 10A shows a laminated structure semiconductor device in which a thin film heat transfer substrate 13 and a thin film integrated circuit 17 are bonded to a silicon substrate 1 on which an integrated circuit 16 is formed with an insulating adhesive layer 15 in between. FIG. Thin film integrated circuit 17
12 is obtained by forming an integrated circuit and thinning a silicon substrate by a selective polishing method, as shown in FIG. 12 showing a conventional technique.
【００３４】かかる積層半導体装置の構造の特徴は、回
路動作時に発熱するＭＯＳＦＥＴ等の半導体集積回路素
子形成領域１８を積層半導体装置中央部に配置し、その
周辺部に熱伝導性の良い金属材料からなる層間接続縦配
線１９や、埋め込み金属フィラー２０を形成して中央部
よりもその周辺部の熱伝導性を高くしてみることであ
る。A feature of the structure of such a laminated semiconductor device is that a semiconductor integrated circuit element forming region 18 such as a MOSFET that generates heat during circuit operation is arranged in the central portion of the laminated semiconductor device, and a peripheral portion thereof is made of a metal material having good thermal conductivity. By forming the inter-layer connection vertical wiring 19 and the embedded metal filler 20 to be formed, the thermal conductivity of the peripheral portion is made higher than that of the central portion.
【００３５】このような積層構造半導体装置の構造をと
ることで、図１０（ｂ）に示すがごとく半導体装置中央
部で発生した熱を薄膜伝熱基板１３により、周辺部に移
動させ、図１０（ｂ）では、図示を略しているが、周辺
部に形成してある層間金属縦配線や埋め込み金属フィラ
ーを通して放熱させる。By taking such a structure of the laminated structure semiconductor device, as shown in FIG. 10B, the heat generated in the central part of the semiconductor device is moved to the peripheral part by the thin film heat transfer substrate 13, and the heat is generated. In (b), although not shown, heat is dissipated through the interlayer metal vertical wiring and the embedded metal filler formed in the peripheral portion.
【００３６】なお、上述した積層半導体装置の実施例で
は、バルクシリコン基板に形成された集積回路上に、薄
膜伝熱基板１３と薄膜集積回路１７とを張り合わせた場
合を示したが、図１１に示すがごとく、さらに多層構造
の積層半導体装置に適応できることは自明である。In the embodiment of the laminated semiconductor device described above, the thin film heat transfer substrate 13 and the thin film integrated circuit 17 are attached to each other on the integrated circuit formed on the bulk silicon substrate. As shown, it is obvious that it can be applied to a stacked semiconductor device having a multilayer structure.
【００３７】また、シリコン集積回路製造プロセスとの
整合性を加味して、ペルチェ効果を利用する半導体とし
てＳｉ−Ｇｅを使用したが、Ｓｉ−Ｇｅ以外の材料、例
えばＢｉ−Ｔｅ−Ｓｂ系材料でも良いことは自明であ
る。Although Si-Ge was used as a semiconductor utilizing the Peltier effect in consideration of compatibility with the silicon integrated circuit manufacturing process, materials other than Si-Ge, for example, Bi-Te-Sb-based materials are also used. Good things are self-evident.
【００３８】また、ペルチェ効果を利用するｐ型および
ｎ型半導体素子対の数には制限はないことは自明である
が、ただし、熱移動の方向を基板中心から周辺部へ移動
させるには、少なくともｐ型半導体素子領域では基板中
心から周辺部へ電流が流れ、一方ｎ型半導体素子領域で
は周辺部から中心部へ流れるようにしておく必要があ
る。It is obvious that the number of p-type and n-type semiconductor element pairs utilizing the Peltier effect is not limited, but in order to move the heat transfer direction from the substrate center to the peripheral portion, At least in the p-type semiconductor element region, it is necessary to allow the current to flow from the center of the substrate to the peripheral portion, while in the n-type semiconductor element region, to flow from the peripheral portion to the central portion.
【００３９】[0039]
【発明の効果】以上述べたように本発明を適用するなら
ば、ペルチェ効果を利用して基板中央部から周辺部へと
熱移動させる伝熱基板を形成することができる。さら
に、薄膜半導体集積回路基板を張り合わせて得られる積
層構造半導体装置に薄膜伝熱基板を組み込むことによ
り、半導体装置中央部で発生した熱を周辺部に移動さ
せ、さらに周辺部に形成してある層間金属縦配線や埋め
込み金属フィラーを介して放熱させることを可能ならし
める。As described above, if the present invention is applied, it is possible to form a heat transfer substrate that transfers heat from the central portion of the substrate to the peripheral portion by utilizing the Peltier effect. Furthermore, by incorporating a thin film heat transfer substrate into a laminated structure semiconductor device obtained by laminating thin film semiconductor integrated circuit substrates, the heat generated in the central part of the semiconductor device is transferred to the peripheral part, and the interlayer formed in the peripheral part is further transferred. It is possible to dissipate heat through metal vertical wiring and embedded metal filler.
【００４０】すなわち、半導体装置において、発熱によ
る温度上昇により動作特性が劣化するのは主に中央部に
形成されている半導体集積回路素子領域であることに着
目し、薄膜伝熱基板を用いて半導体集積回路素子部から
の熱を接続縦配線形成領域である周辺部へ移動ならしめ
ている。That is, in the semiconductor device, the operation characteristics are deteriorated due to the temperature rise due to heat generation mainly in the semiconductor integrated circuit element region formed in the central portion, and the semiconductor is formed by using the thin film heat transfer substrate. The heat from the integrated circuit element portion is transferred to the peripheral portion, which is the connection vertical wiring formation region.
【００４１】このことにより、放熱特性の問題で積層数
に限界があるとされていた積層半導体装置の課題を解決
し、より多層・高密度の積層半導体装置の設計を可能な
らしめるものである。This solves the problem of the stacked semiconductor device, which has been limited in the number of stacked layers due to the problem of heat dissipation characteristics, and enables the design of a stacked semiconductor device with a higher number of layers and a higher density.
【図１】本発明の実施例を説明するための伝熱基板の斜
視図である。FIG. 1 is a perspective view of a heat transfer board for explaining an embodiment of the present invention.
【図２】本発明の実施例に係わる製造方法を説明するた
めの断面図である。FIG. 2 is a cross-sectional view for explaining the manufacturing method according to the embodiment of the present invention.
【図３】本発明の実施例に係わる製造方法を説明するた
めの断面図である。FIG. 3 is a cross-sectional view for explaining the manufacturing method according to the embodiment of the present invention.
【図４】本発明の実施例に係わる製造方法を説明するた
めの断面図である。FIG. 4 is a cross-sectional view for explaining the manufacturing method according to the embodiment of the present invention.
【図５】本発明の実施例に係わる製造方法を説明するた
めの断面図である。FIG. 5 is a sectional view for explaining the manufacturing method according to the embodiment of the present invention.
【図６】本発明の実施例に係わる製造方法を説明するた
めの断面図である。FIG. 6 is a sectional view for explaining the manufacturing method according to the embodiment of the present invention.
【図７】本発明の実施例に係わる製造方法を説明するた
めの断面図である。FIG. 7 is a cross-sectional view for explaining the manufacturing method according to the embodiment of the present invention.
【図８】本発明の実施例を説明するための薄膜熱伝基板
の断面図である。FIG. 8 is a cross-sectional view of a thin film heat transfer substrate for explaining an embodiment of the present invention.
【図９】本発明の実施例を説明するための薄膜熱伝基板
の断面図である。FIG. 9 is a cross-sectional view of a thin film heat transfer substrate for explaining an embodiment of the present invention.
【図１０】（ａ），（ｂ）は、本発明の実施例に係わる
積層半導体装置の構造および熱の流れ方向を説明するた
めの断面図である。10A and 10B are cross-sectional views for explaining a structure and a heat flow direction of a laminated semiconductor device according to an example of the present invention.
【図１１】本発明の実施例を発展・応用させた積層半導
体装置の構造を説明するための断面図である。FIG. 11 is a cross-sectional view for explaining the structure of a laminated semiconductor device which is an embodiment of the present invention developed and applied.
【図１２】従来の多層構造半導体装置の製造方法を説明
するための断面図である。FIG. 12 is a cross-sectional view for explaining the conventional method for manufacturing a multilayer-structure semiconductor device.
１ シリコン基板 ２ シリコン酸化膜 ３ ｎ型半導体素子領域 ４ ｐ型半導体素子領域 ５ 金属配線 ６ 熱の流れ ７ 電流の流れ ８ シリコン酸化膜に形成された凹部 ９ Ｓｉ−Ｇｅ膜 １０ レジスト １１ 層間絶縁膜 １２ コンタクトホール １３ 薄膜伝熱基板 １４ 支持基板 １５ 絶縁性接着層（ポリイミド） １６ シリコン基板表面層に形成された集積回路 １７ 薄膜集積回路 １８ 半導体集積回路素子形成領域 １９ 層間接続縦配線 ２０ 埋め込み金属フィラー DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 n-type semiconductor element region 4 p-type semiconductor element region 5 Metal wiring 6 Heat flow 7 Current flow 8 Recesses formed in silicon oxide film 9 Si-Ge film 10 Resist 11 Interlayer insulating film 12 Contact Hole 13 Thin Film Heat Transfer Substrate 14 Support Substrate 15 Insulating Adhesive Layer (Polyimide) 16 Integrated Circuit Formed on Silicon Substrate Surface Layer 17 Thin Film Integrated Circuit 18 Semiconductor Integrated Circuit Element Forming Area 19 Interlayer Connection Vertical Wiring 20 Embedded Metal Filler
Claims (4)
域との複数の接合対を有する伝熱基板であって、 ｎ型半導体素子領域と、ｐ型半導体素子領域との接合対
は基板の中心部より周辺部へ向けてペルチェ効果により
熱移動を生じさせるものであることを特徴とする伝熱基
板。1. A heat transfer substrate having a plurality of junction pairs of an n-type semiconductor element region and a p-type semiconductor element region, wherein the junction pair of the n-type semiconductor element region and the p-type semiconductor element region is of the substrate. A heat transfer board characterized by causing heat transfer from the central part to the peripheral part by the Peltier effect.
さを有するものであることを特徴とする請求項１に記載
の伝熱基板。2. The heat transfer board according to claim 1, wherein the heat transfer board has a thickness of about 2 μm to 50 μm.
され、周辺部に層間接続縦配線，埋め込み金属フィラー
を有する多層構造の積層半導体装置であって、 集積回路基板は、薄膜化されたものであり、 伝熱基板は、ｎ型半導体素子領域とｐ型半導体素子領域
との複数の接合対を有し、基板の中心部より周辺部に向
けてペルチェ効果により熱移動を生じさせるものであ
り、 層間接続縦配線、あるいは埋め込み金属フィラーは、各
層の伝熱基板上で周辺部に移動した熱を放熱させるもの
であることを特徴とする半導体装置。3. A laminated semiconductor device having a multilayer structure in which an integrated circuit substrate and a heat transfer substrate are alternately laminated, and an interlayer connection vertical wiring and a buried metal filler are provided in a peripheral portion, wherein the integrated circuit substrate is thinned. The heat transfer substrate has a plurality of junction pairs of an n-type semiconductor element region and a p-type semiconductor element region, and causes heat transfer from the central portion of the substrate toward the peripheral portion by the Peltier effect. The semiconductor device is characterized in that the interlayer connection vertical wiring or the embedded metal filler radiates the heat transferred to the peripheral portion on the heat transfer substrate of each layer.
の凹部を形成する工程と、 前記凹部にｐ型半導体およびｎ型半導体を埋め込む工程
と、 前記ｐ型半導体と前記ｎ型半導体とを金属配線で接続す
る工程とを有することを特徴とする伝熱基板の製造方
法。4. A step of forming a plurality of recesses in an insulating film formed on a surface of a substrate, a step of embedding a p-type semiconductor and an n-type semiconductor in the recesses, the p-type semiconductor and the n-type semiconductor And a step of connecting them with metal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4059385A JPH05226579A (en) | 1992-02-13 | 1992-02-13 | Heat-conducting substrate, semiconductor device using the heat-conducting substrate and manufacture of heat-conducting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4059385A JPH05226579A (en) | 1992-02-13 | 1992-02-13 | Heat-conducting substrate, semiconductor device using the heat-conducting substrate and manufacture of heat-conducting substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05226579A true JPH05226579A (en) | 1993-09-03 |
Family
ID=13111766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4059385A Pending JPH05226579A (en) | 1992-02-13 | 1992-02-13 | Heat-conducting substrate, semiconductor device using the heat-conducting substrate and manufacture of heat-conducting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05226579A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5436467A (en) * | 1994-01-24 | 1995-07-25 | Elsner; Norbert B. | Superlattice quantum well thermoelectric material |
| US5550387A (en) * | 1994-01-24 | 1996-08-27 | Hi-Z Corporation | Superlattice quantum well material |
| JP2004207385A (en) * | 2002-12-24 | 2004-07-22 | Rohm Co Ltd | Mask, its manufacturing method, and method of manufacturing semiconductor device using the same |
| JP2011526081A (en) * | 2008-06-27 | 2011-09-29 | クゥアルコム・インコーポレイテッド | Active thermal control for stacked IC devices |
| JP2013191753A (en) * | 2012-03-14 | 2013-09-26 | Fujitsu Ltd | Semiconductor device and method for using the same |
| JP2014204123A (en) * | 2013-04-09 | 2014-10-27 | ハーマン ベッカー オートモーティブ システムズ ゲーエムベーハー | Printed circuit board integrated thermoelectric cooler/heater |
-
1992
- 1992-02-13 JP JP4059385A patent/JPH05226579A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5436467A (en) * | 1994-01-24 | 1995-07-25 | Elsner; Norbert B. | Superlattice quantum well thermoelectric material |
| US5550387A (en) * | 1994-01-24 | 1996-08-27 | Hi-Z Corporation | Superlattice quantum well material |
| JP2004207385A (en) * | 2002-12-24 | 2004-07-22 | Rohm Co Ltd | Mask, its manufacturing method, and method of manufacturing semiconductor device using the same |
| US7344805B2 (en) | 2002-12-24 | 2008-03-18 | Rohm Co., Ltd. | Mask and method for producing thereof and a semiconductor device using the same |
| JP2011526081A (en) * | 2008-06-27 | 2011-09-29 | クゥアルコム・インコーポレイテッド | Active thermal control for stacked IC devices |
| KR101318842B1 (en) * | 2008-06-27 | 2013-10-17 | 퀄컴 인코포레이티드 | Active thermal control for stacked ｉｃ devices |
| US8598700B2 (en) | 2008-06-27 | 2013-12-03 | Qualcomm Incorporated | Active thermal control for stacked IC devices |
| US8987062B2 (en) | 2008-06-27 | 2015-03-24 | Qualcomm Incorporated | Active thermal control for stacked IC devices |
| EP2304792B1 (en) * | 2008-06-27 | 2020-03-11 | QUALCOMM Incorporated | Active thermal control for stacked ic devices |
| JP2013191753A (en) * | 2012-03-14 | 2013-09-26 | Fujitsu Ltd | Semiconductor device and method for using the same |
| JP2014204123A (en) * | 2013-04-09 | 2014-10-27 | ハーマン ベッカー オートモーティブ システムズ ゲーエムベーハー | Printed circuit board integrated thermoelectric cooler/heater |
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