JPH0522471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention performs pulse width control on one of a pair of semiconductor switching elements connected to each terminal of a primary winding of a power conversion transformer using an AVR signal, and controls the pulse width of the other one by using an AVR signal. The present invention relates to a method for suppressing biased excitation of the transformer by controlling the transformer to follow the above.

For example, a known power supply device as shown in FIG. 1 uses switching transistors Q ₁ and Q ₂ as shown in FIG.
Turns on alternately by the base drive signal shown in
The collector currents shown in b and c of the same figure are turned off, and the currents are passed from the DC power supply E to the primary windings N ₁ and N' ₁ of the power conversion transformer T alternately in opposite directions. As a result, an alternating current voltage is induced in the secondary windings N ₂ and N' ₂ of the transformer T, the voltage is rectified through the rectifiers D ₁ and D ₂ , smoothed by the choke coil CH and the capacitor C, and then applied to the load. The desired DC voltage is applied to L ₀ .

Here, PW is a pulse width control circuit that detects a voltage proportional to the output voltage and generates a pulse width control signal, OS is an oscillator that oscillates a rectangular wave as shown in Figure 2a, and PR are transistors Q ₁ and Q. ₂ is an overcurrent protection circuit for protecting 2 from overcurrent, and DV is a drive circuit that generates a base drive signal as shown in FIG. 2d and e.

A power supply device with such a configuration has a relatively high utilization rate of transistors and transformers, and is a method suitable for converting the same electric power. However, recently there has been a trend to increase the conversion frequency to make the device smaller and lighter. , the accumulation time of transistors, etc. has become impossible to ignore. Generally, the accumulation time of transistors Q ₁ and Q ₂ is the time difference between the base drive signal and the collector current shown in FIGS. 2b to 2e, and this accumulation time varies depending on the transistor and its driving conditions.

Therefore, if there is a difference in the storage time of transistors Q ₁ and Q ₂ , the on-periods of transistors Q ₁ and Q ₂ will differ by that difference, and if this phenomenon occurs in each cycle, the pulse width of the drive pulse and the transistor When the saturation voltages of are equal, the magnetic flux of transformer T continues to be biased in one direction, and finally transformer T reaches saturation,
An excessive current flows through the transistors Q ₁ and Q ₂ whose storage time is longer.

Conventionally, as a method to protect each circuit component from excessive current caused by such biased excitation, the current flowing through transistors Q ₁ and Q ₂ is detected using resistors R ₁ and R ₂ , and when this detected value exceeds a set value, an overcurrent is detected. The protection circuit 4 is activated to forcibly turn off the transistors Q ₁ and Q ₂ , but since the saturation phenomenon occurs quickly in a transformer using a ferrite core, the transistors Q ₁ and Q ₂ are turned off quickly.
Protection cannot be achieved unless the circuit is designed to have sufficient margin for the maximum collector current and a certain degree of regulation.Another method is to select transistors with the same characteristics such as storage time and saturation voltage. I am using it. However, as mentioned above, the former method has the disadvantage of being expensive and increasing the size of the transformer because it requires a margin in the capacity of the transistor, while the latter method has the disadvantage of requiring a considerable amount of cost to select the transistor. have.

Another method for suppressing biased excitation is to control both switching transistors Q ₁ and _{Q 2} using the AVR signal, compare the currents flowing through _each transistor, and adjust the currents so that they are equal to each other. There is also a method of controlling the pulse width of the transistors Q ₁ and Q ₂ , but each of the transistors is controlled by two control factors, so the circuit configuration becomes complicated and expensive.

In order to eliminate the above-mentioned conventional drawbacks, the present invention controls the first semiconductor switching element on the master side using an AVR signal, and the detected value of the current flowing through the second semiconductor switching element on the slave side is controlled by the first semiconductor switching element on the slave side. The current flows through one semiconductor switching element.

By generating an OFF signal to the second semiconductor switching element when the current becomes equal to the detected value at the time of generation of the OFF signal, the current flowing through the second semiconductor switching element is switched to the first semiconductor switching element. It is characterized by suppressing biased excitation by making it equal to the flowing current, and its purpose is to reliably suppress biased excitation of the power conversion transformer with a relatively simple circuit configuration.

First, the basic circuit configuration of the present invention will be explained with reference to FIGS. 3 and 4. In the figures, the same symbols as those shown in FIG. 1 indicate members corresponding to the first member. There is. The switching transistor Q ₁ on the master side receives a base drive signal from its drive circuit DV ₁ , and the switching transistor Q 1 on the slave side receives a base drive signal from its drive circuit DV 1.
Q ₂ is driven by its drive circuit DV ₂ . Here, we will explain Q ₁ and Q ₂ as transistors, but
Q ₁ and Q ₂ refer to a single semiconductor switching element, or a plurality of transistors connected in parallel or series, or semiconductor switching elements such as a thyristor.

The drive circuit DV ₁ is the oscillation signal S ₁ from the oscillation circuit OS.
It operates to turn on the transistor _Q1 , and turns off the transistor _Q1 upon receiving the first off signal _θ1 from the pulse width control circuit PW. This pulse width control circuit is a general type, and generates an off signal θ ₁ when the DC voltage between the output terminals T ₀ and T′ ₀ exceeds a reference value. On the other hand, the drive circuit DV ₂ on the slave side is operated by the oscillation signal S ₂ which has a phase difference of 180° from the signal S ₁ from the oscillation circuit OS, and the transistor
The transistor Q ₂ is turned on, and the second off signal θ ₂ from the comparator circuit CM turns off the transistor Q ₂ . The comparator circuit CM is the collector current of the transistor _Q2 detected through the detection resistor _R1 .
The base drive signal of transistor Q ₁ of the detection signal proportional to I _C2 is removed. In other words, the hold signal from the peak value detection hold circuit DH holds the value at time _t1 when the off signal _θ1 is generated as shown in Figure 4g.
Hm is compared with a detection signal from a detection resistor R ₂ that detects the collector current of a transistor Q ₂ as shown in the figure e, and at a time t ₄ when the detection signal exceeds the hold signal Hm, an off signal θ ₂ is generated. It is designed to output . As the transistors Q ₁ and Q ₂ are alternately turned on and off, the collector current I _C1 as shown in Fig. 4 d and e is generated.
When I _C2 flows through the first windings N ₁ and N' ₁ of the transformer T, a voltage as shown in the figure a is induced in the secondary windings N ₂ and N' ₂ , and at this time, the voltage of the transformer T The exciting current Ih flowing through the coil CH becomes as shown in the figure b, and the current I _L flowing through the choke coil CH becomes as shown in the figure c. Here, the times τ ₁ and τ ₂ in d and e of the same figure are respectively transistors.
It shows the accumulation time of Q ₁ and Q ₂ . Biased excitation will be explained in more detail with reference to FIG.

FIGS. 5A and 5B show the case where the storage times of the transistors Q ₁ and Q ₂ are equal and different, respectively, where a is the collector current I _C1 of the transistors Q ₁ and Q ₂ ,
I _C2 is shown on the same drawing, and b shows the exciting current Ih of the transformer T. Here, the turns ratio of each winding of the transformer T is all 1, and the
The pulsating current of CH is zero (CH
(assuming the value of is infinite). Therefore, the output current I ₀ is represented by a straight line in the drawing.

Under this assumption, first the transistors Q ₁ and Q ₂
When the accumulation times τ ₁ and τ ₂ are equal, the collector currents I _C1 and I _C2 of the transistors Q ₁ and Q ₂ are I _C1 = I _C2 = I ₀
It becomes +Ih. Here, if the self-inductance of the transformer T is Lt, then Ih is expressed as Ih = E・t/Lt (where E is the voltage of the DC power supply E _S ), and if the voltage E is constant, the time elapses. increases linearly with Therefore, as is clear from Figure A, the collector current I _C1 = Im at time t ₁ when the off signal θ ₁ of transistor Q ₁ is generated and the time t ₄ when the second off signal θ 1 of transistor Q ₂ is generated. If _the collector currents I _{C2 =} I _{S are} controlled _{to be equal} when I _C1 of , I _C2 of t=t ₃ )
are equal, and the respective excitation currents are Ih = Ih ₁ = Ih ₂
become. Therefore, no biased excitation occurs in this case.

Next, in the case of B in the same figure where the accumulation times τ ₁ and τ ₂ of the transistors Q ₁ and Q ₂ are different, assuming that τ ₂ > τ ₁ , the base drive signals of the respective transistors Q ₁ and Q ₂ are removed. In other words, if the transistor is controlled so that the collector current values Im and I _S at times t ₁ and t ₄ when the off signal is generated are equal, the collector currents I _C1 and I _C2 will become equal, as is clear from the figure.
The peak currents Ip ₁ and Ip ₂ are different. Here the output current
Since it is assumed that I ₀ is constant, the excitation current Ih flows in a biased state as shown in B and b in the figure. In other words, the peak value of collector current Ip ₂ is Ip ₁
When it becomes larger than , the excitation current Ih ₃ increases, which reduces the rising current of the collector current I _C1 in the next cycle, and therefore the current value Im decreases. As a result, it naturally works in the direction of decreasing the value I _S and the peak value Ip ₂ of the collector current of the transistor Q ₂ at time t ₄ . Here, under normal operating conditions (Tm + τ ₁ ) =
( _TS + τ ₂ ) (Tm and T _S are transistors Q _{1 and} TS, respectively)
Therefore, the excitation current Ih ₃ can be set as Ih ₁ , so if we proceed with the analysis below under this condition, the base signal removal time t ₁ of the transistors _{Q 1 and} Q ₂ , Collector current value Im, I _S at t ₄
Im=E/Lt・Tm+( _I0 − _Ih1 )= _IS =E/ _LtTS +( _I0 − _Ih2 )...(1) (However, Lt is the self-inductance of the transformer T. ), and the peak value of the collector current is
Ip ₁ and Ip ₂ are as follows: Ip ₁ = (I ₀ - Ih ₁ ) + E/Lt (Tm + τ ₁ ) = I ₀ + Ih ₂ ... (2) Ip ₂ = (I ₀ - Ih ₂ ) + E/Lt ( _TS +τ ₂ )=I ₀ +Ih ₁ ...(3) Then, from equations (1) to (3) above, Ih ₁ = E/2Lt (2Tm−T _S +τ ₁ ) = E/2Lt {(Tm+τ ₁ )+( Tm + τ ₁ ) − (T _S + τ ₂ )
+ (τ ₂ − τ ₁ )} …(4) Ih ₂ = E/Lt (T _S + τ ₁ ) = E/2Lt {(T _S + τ ₂ ) − (τ ₂ − τ ₁ )} ……(5 ) become.

Here, from the above, (Tm + τ ₁ ) = ( _TS + τ ₂ ), and if the DC component of the excitation current T _DC representing the degree of biased excitation is expressed as I _DC = (Ih ₁ − Ih ₂ )/2, then I _DC = E/Lt(τ ₂ −τ ₁ ) ...(6).

Here, the amount of DC bias in the transformer is expressed by magnetic flux density B _DC : B _DC = Lt・I _DC /N・S = 1/N・S・E(τ ₂ −τ ₁ )/2 …(7 ) (where N is the number of turns of the primary winding of transformer T, and S is the core cross-sectional area of transformer T). Therefore, the power conversion section including the power conversion transformer T operates with the magnetic flux density B _DC shown in equation (7) above biased, but in a normal design, the magnetic flux density of the transformer is equal to that of the power conversion section. Maximum magnetic flux density Bmax = 1/N in half cycle
S・E/2・(Tm+τ ₁ ) is the minimum required,
The ratio of the biased excitation to Bmax is the above B _DC ,
From Bmax, it becomes (τ ₂ −τ ₁ )/2(Tm+τ ₁ ).

Considering a specific example, in a power converter that operates at a conversion frequency of 20 KHz, (Tm + τ ₁ ) is approximately 25 μS, and (τ ₁ − τ ₂ ) is approximately 3 μS or less under normal operating conditions. Therefore, if (τ ₂ - _{τ 1} ) = 3 μS, then (τ ₂ - τ ₁ )/2 (Tm + τ ₁ ) = 0.06, and 6
It is sufficient to give a margin of about 1.9% to the magnetic flux density of the transformer T. The above explanation is for the output side chiyoke coil.
Although we considered the value of CH to be infinite and the pulsating current to be zero, similar results can be derived even if we consider the value of the chiyoke coil CH to be a finite value. In other words, the current flowing through the chiyoke coil CH is the primary and secondary current of the transformer T.
When converting to the primary side with _{the following} turns ratio as n, the _converted current i _L is: i _L = _n . 8) Become.

Here, L _C is the inductance of the choke coil CH, and V ₀ is the output voltage.

When the inductance L _C is assumed to be infinite in equation (8), if I ₀ is replaced by i _L , the amount of biased magnetism of the transformer T is calculated in exactly the same way, and the same result is obtained.

As mentioned above, the transistor on the slave side
The collector current of Q ₂ is the master side transistor.
The base drive signal of Q ₁ is removed, that is, the base drive signal of transistor Q ₂ is removed at time t ₄ when the collector current becomes equal to the value Im of the collector current at time t ₁ when the first off signal is generated. That is, by controlling the transformer so as to generate the second off signal every cycle, it is possible to suppress biased excitation and operate stably by providing the transformer with a slight margin of magnetic flux density.

Next, an embodiment of the present invention will be described using a bridge type inverter shown in FIG. 6. In this figure, the same symbols as those shown in FIG. 3 indicate members corresponding to those in FIG. 3. The first drive circuit DV ₁ is
The switching transistor _Q1 on the master side receives a signal from the oscillation circuit OS as shown in Figure 1a.
A base drive signal as shown in d of the same figure is applied to Q'1 and _Q'1 to turn them on simultaneously. As a result, a current as shown in Figure 4d flows from the positive side of the power source E _S to
Current transformer CT → transistor Q ₁ → primary winding N ₁ of transformer T → transistor Q′ ₁ → flows in a closed circuit to the negative side of power supply E _S , and this current is detected by current transformer CT ₁ ,
Applied to the peak value detection hold circuit DH. This peak value detection hold circuit DH includes reverse current blocking diodes d ₁ to d ₃ and a resistor for resetting the current transformer CT ₁ .
r ₁ , resistor r ₂ that detects the current proportional to the collector current of transistor Q ₁ , noise absorption capacitor
C ₁ , a voltage proportional to the value Im of the collector current I _C1 at the time when the base drive signal of the transistor Q ₁ is removed (t=t ₁ in Fig. 4) (hereinafter referred to as the hold value
A capacitor that holds the peak of Hm
C ₂ , the transistor Tr ₁ for clearing the hold value Hm, and the transistor Q ₁ turn on at the time when the base drive signal is removed, and turn on only for the accumulation time τ ₁ according to the accumulation time of the transistor Q ₁ It consists of a transistor _Tr2 that bypasses the detection current. Therefore, the detection signal from the current transformer CT ₁ is charged to the capacitor C ₂ via the resistor r ₁ and the diode 13, and this charging is applied to the output terminals T ₀ and T′ ₀
This is continued until the transistor Tr ₂ is turned on (time t ₁ in FIG. 4) by the off signal θ ₁ generated by the pulse width control circuit PW when the output voltage between the two reaches the set value. As a result, the master side transistor Q ₁ ,
A voltage proportional to the collector current _Im , that is, a hold value Hm, as shown in _FIG . continue. Next, the base drive circuit is activated by the oscillation signal from the oscillator OS.
DV ₂ works and slave side transistor Q ₂ ,
Turn on Q′ ₂ . The current transformer CT ₂ detects its collector current I _C2 , and its detection signal is sent to the comparator circuit CM through the diode d ₄ and capacitor C ₃ , etc.
is applied to the other terminal of The comparator circuit CM provides an off signal θ ₂ to the second drive circuit DV ₂ at the time t ₄ (FIG. 4g) when the detected voltage from the current transformer CT ₂ exceeds the hold value Hm. As a result, transistor Q ₂ ,
The base drive signal is removed from the base of Q′ ₂ ,
In other words, the collector current value at the time t ₁ when the base drive signal of the transistors Q ₁ and Q' ₁ on the master side is removed is
The base drive signal is removed at time _t4 when Im and the collector current value _IS become equal. It will be understood from the above description that biased excitation can be suppressed by performing such control.

As described above, the present invention directly controls only the semiconductor switching element on the master side according to the output voltage.
AVR operation is used to control the semiconductor switching device on the slave side by following the current flowing through the semiconductor switching device on the master side, so the semiconductor switching device on the master side is not restricted by the semiconductor switching device on the slave side. For example, if the output detection outputs a pulse width increase or decrease signal, a response can be immediately started from the next cycle. Therefore, even if the accuracy of bias excitation suppression control is improved by controlling the semiconductor switching device on the slave side to accurately follow the operation of the semiconductor switching device on the master side, high-speed response pulse width control will not be possible. It is possible. That is, according to the present invention, both high-speed response pulse width control and high-precision bias excitation suppression control are possible. In addition, the configuration of the control section of the power supply device can be simplified, and the degree of bias in the excitation current can be easily calculated, making it easy to determine and adjust the circuit constants, and is fully compatible with higher frequencies. This provides a highly practical method that can be used.

In addition, in FIG. 6, a 180° drive signal is applied alternately to the transistors Q' ₁ and Q' ₂ , and the transistors Q' 1 and Q' ₂ are
The same can be applied to the case where Q ₂ is controlled to be turned on and off alternately in a certain phase. Further, when a thyristor is used instead of a transistor, the time point at which the drive signal is removed, that is, the time point at which the OFF signal is generated, becomes the time point at which the extinction signal is generated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional power supply device equipped with a power conversion transformer, FIG. 2 is a diagram showing waveforms of various parts for explaining the conventional power supply device and the present invention, and FIG. 3 is a diagram showing waveforms of various parts for explaining the conventional method and the present invention. A basic circuit configuration diagram, FIG. 4 is a diagram showing current and voltage waveforms of each part to explain the present invention, FIG. 5 is a diagram showing current waveforms to explain biased excitation, and FIG. 6 is a diagram showing the present invention. FIG. 2 is a circuit configuration diagram of a power supply device for implementing one embodiment of the present invention. Q ₁ , Q' ₁ , Q ₂ , Q' ₂ ... Semiconductor switching element, DV ₁ , DV ₂ ... Drive circuit, PW ... Pulse width control circuit, DH ... Peak value detection hold circuit,
CM...comparison circuit, OS...oscillator, E _S ...DC power supply.

Claims (1)

[Claims] 1. A desired AC voltage is obtained between the secondary winding of the transformer by alternately turning on and off a pair of semiconductor switching elements connected in series to each terminal of the primary winding of the power conversion transformer. In a power supply device equipped with such a power converter, the pulse width of the master-side semiconductor switching element among the semiconductor switching elements is controlled so that the output voltage becomes constant, and the pulse width of the master-side semiconductor switching element among the semiconductor switching elements is controlled so that the output voltage becomes constant. The current flowing through the slave-side semiconductor switching device is equal to the current flowing through the master-side semiconductor switching device at the time when the first off signal for the master-side semiconductor switching device is generated. A power conversion transformer for suppressing biased excitation, characterized in that biased magnetization of the transformer is suppressed by exclusively controlling the transformer to be turned off by a second off signal generated when the value of the transformer becomes approximately equal to the value of Method.