JPH0522272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technology for automatically translating a computer program into a target program using a compiler (translation program), and in particular, the present invention relates to a technology for automatically translating a computer program into a target program using a compiler (translation program). This invention relates to a method for generating a target program for a vector processor using vectors.

In recent years, with advances in semiconductor technology, high-speed electronic computers called vector processors that take advantage of the ability to execute operations in parallel have been used to process programs written in computer languages such as FORTRAN.
There is a need for a vector compiler to translate target programs for vector processors. A vector compiler translates the loop operation part of a program into a target program that includes vector processor directive instructions called vector instructions, but if a control branch due to a conditional statement is included during the loop operation, the uniformity of the operation will be disrupted. This makes it difficult to generate the target program.

Conventionally, control vectors are one of the hardware mechanisms for vectorizing loop operations that include conditional statements, and merge is the conventional method for applying vector processors to loop operations that include conditional branches using control vectors. A method using functions is known. This is true for loop operations that include a two-way branch type conditional statement as shown in Figure 1a.
As shown in the figure, after performing the vector operations B+D, F×G specified by branching in both directions and generating the control vector CV, the vector merge instruction CVMGM is executed.
If the element value of CV is the logical value "1", select the corresponding element value of the first operand I ₁ , and if it is "0", select the corresponding element value of the second operand I ₂ , and select the corresponding element value of the second operand I 2. This is a method of assigning to the corresponding element.

However, this method has the disadvantage that its scope of application is limited for the following reasons.

First of all, since this method selectively obtains a value depending on whether a condition is met or not, it can be applied to conditional statement structures where the variables or array elements to which values are assigned differ depending on the branching of the condition, as shown in Figure 2. is not direct. Furthermore, it is difficult to apply this method to a multiple conditional sentence structure in which a conditional sentence is included again on a branch of a conditional sentence, as shown in FIG. Furthermore, if the program is written in the normal form as shown in Figure 1a, conventional compilers cannot generate the target program as shown in Figure 1c, but instead use a special function CVMGM as shown in Figure 1b. Since it is necessary to create a program using
This increased the amount of programming effort.

An object of the present invention is to provide a compilation method that automatically generates an object program including vector instructions for a loop operation including a conditional expression.

Another object of the present invention is to provide a compilation method that automatically generates a target program including vector instructions for a loop operation including multiple conditional expressions.

Another object of the present invention is to generate an object program that is as efficient as possible in applying vector instructions to loop operations including conditional statements.

To this end, the present invention analyzes a calculation program written in the FORTRAM language in a normal manner during automatic translation, separates and points out the condition judgment section and the conditional operation section, and efficiently streamlines the control/controlled relationship between the two. After clarifying the condition in a good manner, the condition determination unit generates a target program that reproduces a control vector, which is a logical value sequence that controls whether or not the operation of each vector element can be executed, based on the result of the condition determination of each element,
In the conditional operation section, the control vector is used to generate a target program using vector instructions that control the execution of operations on each element of the data vector, thereby realizing automatic application of the vector processor to the target program.

Furthermore, in the above method, for conditional judgment expressions based on variables and array elements whose values do not change regardless of the progress of the loop, the judgment can be made without generating a control vector.
Generate a target program that performs calculation control using branch instructions, and for conditional expressions that depend on loop index values at the start and end points of the loop, expand the calculations at the start and end points outside the loop. To eliminate expressions from loops, eliminate the need for generation of control vectors and controlled operation instructions, and achieve efficient generation of target programs. Regarding the elimination of conditional expressions that depend on the loop index value, it is possible to eliminate not only conditions related to endpoint values but also conditions related to intermediate values using the same method.

The present invention will be explained below with reference to Examples.

As an example of a loop operation that includes a conditional statement, the one written in FORTRAM77 language as shown in Figure 4 is
Use the Do loop operation. The meaning of each line composing this program is as follows.

Line number 1: Below, the line with sentence number 10 (line number
14) by changing the value of the indicator variable I from 1 to N.
Repeat by changing one step at a time.

Line number 2: If the value of array element C ₁ (I) is greater than 0.0, execute the following steps up to the ELSE line (line number 7).

Line number 3: If the value of array element C ₂ J is greater than 1.0, the following steps are executed up to just before the corresponding ENDIF line (line number 6).

Line number 4: If the value of array element C ₃ (I) is greater than 0.0, execute the following steps up to the corresponding ENDIF line (line number 5).

Line number 5: Add array elements B(I) and D(I) and store the result in A(I).

Line number 6: End of the statement group controlled by the conditional statement in line number 4.

Line number 7: End of the statement group controlled by the conditional statement in line number 3.

Line number 8: The value of C ₁ (I) in the conditional statement of line number 2 is
If not greater than 0.0, the following line number 13
Executes up to just before the ENDIF statement (line number 12).

Line number 9: If the value of variable I is equal to 1, execute the following lines up to the ENDIF statement in line number 11 (line number 10).

Line number 10: Add array elements F(I) and G(I) and store the result in E(I).

Line number 11: End of the statement group controlled by the conditional statement on line number 9.

Line number 12: Add the array elements Y(I) and Z(I) and store the result in X(I).

Line number 13: End of the statement group controlled by the conditional statement in line number 2.

Line number 14: End of the statement group controlled by the Do statement in line number 1.

According to the method of the present invention for a loop operation having a complicated conditional control structure as described above, a target program including vector instructions can be automatically generated by a compiler in the following manner.

First, the compiler scans the program description in Figure 4 and converts it into an internal representation. In doing so, it divides the program description into statement blocks, analyzes the control transfer relationship between blocks, and writes the program into main memory. Record it on the table. Analyzing the relationship between block division and control transfer is performed by recognizing the syntax based on the grammar, determining the sentence type, and collecting control transfer information accordingly, which is conventionally performed by a compiler to optimize the target program. is similar to

A feature of the present invention is that, following the analysis of control movement relationships, the control dominance relationships between blocks are analyzed and recorded. In other words, in the example of FIG. 4, in the conventional analysis, the block with line number 2 (hereinafter abbreviated as block 2) only explicitly indicates that control is transferred to block 3 and block 4, but in this case, In the invention, we take this further and characterize block 2 as something that actively controls the execution of other blocks (such blocks are called conditional blocks), 3, 7, 8, 9, 11, 12. The execution of blocks in block 2 is directly controlled by block 2. Furthermore, it will be clarified whether these blocks are controlled by the satisfied or unfulfilled side of the conditional expression in the conditional block. The control/controlled relationship between blocks is multilayered; for example, block 4 is controlled by block 3, which in turn is controlled by block 2. However, by pointing out the block group that directly controls the execution of each block (this is called the block's control block group), all the control/controlled relationships between blocks can be clarified. .

Detection of control block groups is performed based on control movement information between blocks, but prior to this detection, conditional blocks and non-conditional blocks are discriminated. This determination is made based on the type of statements that make up the block, and whether the statement is a logical IF statement, a block IF statement, or
ELSEIF statement, arithmetic IF statement, simple GoTo statement, computational type
If it is either a GoTo statement or an assignment-type GoTo statement, it is considered a conditional block, and if it is not, it is considered a non-conditional block.

Before describing the analysis procedure of the control dominance relationship, the storage format of the control transfer relationship and block discrimination results on the main storage device and its abbreviation will be explained. FIG. 5a shows the storage format on the main memory, FIG. 5b shows its abbreviated notation, and FIG. 6 shows the analysis result of the example problem of FIG. 4 in abbreviated notation.

As shown in Figure 5a, the information of each block is
It is managed by a table BLOCKT that has multiple fields located on the main memory. here,
Field 1 indicates the starting address of the subsequent BLOCKT, Field 2 indicates the type of conditional block/non-conditional block, Field 3 indicates the line number of the statement that makes up the block, and Field 4 indicates the BLOCKT representing the group of blocks to which control is transferred. Field 5 is the index of the FLINK table that holds the start address group, field 5 is the index of the BLINK table that holds the start address group of BLOCKT representing the control transfer source block group, and field 7 is the start address of the statement body that makes up the block. hold. Field 6 will later contain BLOCKT representing the control block group of the block in question.
This field is reserved to contain the index of the CLINK table that holds the starting addresses of . Field 15 is a field in which the starting address of BLOCKT of the equivalent backward definition block of the block is placed in order to efficiently analyze the control/dominance relationship. Field 8 of table FLINK, BLINK
Field 10 indicates whether this is the last of a series of control transfer destination block groups or control transfer source block groups. Fields 9 and 11 hold the BLOCKT start address of the control movement destination or movement source block. Similarly, the CLINK field indicates whether the control block group is final or not, field 13 indicates the BLOCKT start address of the control block, and field 14 indicates which control bus originating from the control block is on. The storage format on the main storage device has been described above, but this is just an example, and as long as the necessary information is included, the format is not as important as the invention.

FIG. 5b shows an abbreviation for the above storage format. The distinction between conditional blocks and non-conditional blocks is shown in the form of a frame, the numbers in the frame indicate the corresponding line number, the solid line arrows indicate the block group to which the control is to be moved, and the dashed-dotted line arrows indicate the control block group that will be revealed later. Make it clear.

FIG. 6 shows the inter-block control movement information of the example program in abbreviated notation and the condition/non-condition block classification.

Based on the above preparations, the procedure for analyzing the inter-block control relationship will be described with reference to FIG.

Step 1: Based on the inter-block control transfer information, confirm that there is no control transfer loop other than the loop from the end point block 14 of the Do statement to the loop head block 2. This confirmation direction is a known direction used in normal directed graph analysis. Also, confirm that the control does not jump out of the loop midway through. If a loop exists or if there is a jump out of the loop, the vector processor cannot be applied in principle, so processing is interrupted here.

Step 2: For each block from the first block to the loop end point, search all routes from that block to the first block according to the sequence of control movement sources, and collect the condition blocks closest to the relevant block on each route. This is used as the control block group for the block.

When searching for a route, the concept of equivalent backward definition blocks is used to make the search more efficient. In other words, for the tip block of the searched route at each stage,
Find the backward definition block (Back Target Block: the block that is on all the block series from the first block of the loop to the block and has the shortest distance from the block), and then calculate the forward definition block of the backward definition block (Forward Target Block).
Block: In this example, find the block that is on all the block sequences up to the end point of the backward defined block loop and has the shortest distance from the block. If it matches the root tip block again, the root tip block and the backward definition block have the same control conditions, so the search up to the backward definition block is bypassed,
The root tip can be positioned behind the rear definition block. Such a backward definition block is called an equivalent backward definition block of the block in question, and is used to shorten the search time and simplify the control block group. Here, the detection method for backward defined blocks and forward defined blocks is a known method used in conventional compilers, but the efficiency can also be improved by using the concept of equivalent backward defined blocks.

The above processing will be explained using block 12 as an example and in accordance with table operations on the main memory. In order to detect the control block group, the procedure shown in FIG.
In addition to BLOCKT, FLINK, BLINK, and CLINK, it is shown in Figure 7 to maintain the backward route being searched.
STKPTR holding RSTACK and its final indicator
use. STKPTR initially stores a zero value. In addition, tables for detecting backward defined blocks and forward defined blocks are required, but they are well known and will therefore be omitted.

First, when searching for the backward route of block 12, after counting up the contents of STKPTR by one,
RSTACK indicated by STKPTR
field 16. Also,
Set the contents of field 5 of BLOCKT (BLINK index) to field 17 of RSTACK. By testing field 10 of the BLINK pointed to by field 5, it is determined that this is the only backward block and this
The block specified by fields 16 and 17 of RSTACK becomes the block to be searched next. That is, since field 11 of the BLINK table specified by field 17 of RSTACK stores the BLOCKT start address of block 11, after counting up STKPTR, the BLOCKT start address of block 11 and the contents of field 5 are stored. Store in fields 16 and 17 of RSTACK pointed to by STKPTR. field 16
Tests field 2 of BLOCKT indicated by , and since it is a non-conditional block, continues searching further backwards. That is, by testing field 10 of the BLINK entry pointed to by field 17, we find that it holds multiple backward blocks since it does not display the last block. Therefore, field 15
If it is zero, it is assumed that an equivalent backward definition block has not been found, and the above-described procedures for detecting backward definition block 9 and its forward definition block are executed. Since it again matches block 11, block 9 is determined to be an equivalent backward definition block of block 11,
Block 9 in field 15 of BLOCKT
Set the starting address of BLOCKT. Also
The contents of fields 16 and 17 of RSTACK are replaced with the BLOCKT start address of backward definition block 9 and the contents of field 5 thereof. If an equivalent backward definition block has already been found in field 15 by analyzing other blocks, then
Replace the contents of fields 16 and 17 of RSTACK. Furthermore, by searching the backward blocks according to field 17, block 8 and block 2 are registered in RSTACK, and the test result of field 2 of block 2 determines that it is a condition block. It is recognized as a control block. Therefore, the first address of BLOCKT of block 2 in field 16 of RSTACK is stored in field 13 of the new area for CLINK, and field 7 of BLOCKT for block 2 is stored.
By analyzing the sentence intermediate words pointed from
It is determined which control movement path that block 8 obtained from field 16 in the previous stage of RSTACK belongs to, which is separated from block 2, and is set in field 14 of CLINK. Furthermore, the index of the CLINK is added to field 6 of BLOCKT for block 12 pointed from field 16 of the RSTACK.
Set to .

After registering block 2 to CLINK, count down STKPTR by one and move on to searching for a control block on another route. i.e. pointed to by STKPTR
Indicated by field 17 of RSTACK
Since field 10 of the BLINK table indicates that this is the last block after block 8, it is determined that there is no other control path after block 8. Therefore, further
The search continues while lowering STKPTR, and the search ends when it reaches blocks 9 and 12. Finally, write the final symbol in field 12 of the only CLINK table pointed to by field 6 of block 12.

In this way, the search time can be shortened by saving the route search between 11 and 9 using the concept of equivalent backward definition blocks.

In addition, if equivalent backward definition blocks are not used, all control paths between blocks 11 and 9 will be scanned, so it is necessary to point out both the establishment and non-establishment of block 9 as a group of control blocks for block 12. Not only is it redundant, but block 9
The fact that the number of control blocks is 2 indicates an indirect control/dominance relationship, which impairs the efficiency of the final target program. By using the equivalent backward definition block, it becomes possible to display the control/dominance relationship in a concise manner.

The procedure for detecting control block groups for each block in FIG. 6 is as follows.

In the control block group detection of block 3 in FIG. 6, the first and only condition block on the route to loop entrance 2 is 2, so the control block 3 is 2. Similarly, the control blocks of blocks 4, 5, 8, 9, and 10 become 3, 4, 2, 2, and 9, respectively. Regarding block 6, since the front definition block of its rear definition block 4 is 6 and it matches that block,
The search can begin with the backward definition block of block 4. Since it is the first condition block, the control block of 6 becomes 3. Similarly, for block 7, it is known that the equivalent backward definition block of 6 is 4, and its equivalent backward definition definition block 3 is efficiently detected. Block 3
The search begins from behind and control block 2 is obtained.
After the block 11 detects the equivalent backward definition block 9, it starts searching from the backward block 8, follows the route 8 and 2, and identifies 2 as a control block. Block 12 searches for block 11, then skips to the equivalent backward definition block 9, and resumes the search from block 8 to identify block 2. Finally, 13 uses the fact that the equivalent backward definition blocks of 7 and 11 are 3 and 9,
Efficiently identify the equivalent backward definition block 2,
The search starts from after 2, but since no block within the loop is left, it is determined that there is no control block.

By the above procedure, the control block group of each block is determined as shown by the dashed line in FIG. 6, and the inter-block control relationship is clarified.

By the way, in the conditional expression during the loop calculation, there is a control variable I of the Do loop, as shown in line number 9 in Figure 4.
Often, the success or failure of a condition is determined depending on the initial value of . Such a conditional expression is
As shown in FIG. 8, by extending the first iteration outside the loop and limiting the range of control variables within the loop, it is possible to determine whether the conditions within the loop are satisfied or not, so this is implemented. That is, if I only takes values from 2 to N within the loop, the condition of IF (I.EQ.1) will not hold, so the operation at line number 10 will not be executed within the loop. Therefore, by deleting the control movement path, the control structure is simplified and the efficiency of the target program is improved.

The above procedure will be explained using FIG. 5a and FIG. 9.

First, a series of BLOCKTs constituting a loop is scanned, field 2 is used to determine whether or not it is a conditional block, and field 7 is used to determine whether or not the conditional block is to be erased by initial expansion. If there is a conditional block to be deleted, expand it using the following steps.

The first development is the 5th block from block 2 to 14.
Tables shown in figure a and field 7
This is done by copying the sentence intermediate word pointed to by to a free area on the main memory, positioning field 1 of block 1 at its first BLOCKT, and positioning field 1 of the last BLOCKT of the copy block group at block 2.

Next, the control structure of blocks 8 to 12 is simplified, and the procedure is as follows. Block 1 is determined by evaluating the conditional expression of block 9.
Since it has been determined that the control movement to 0 does not occur, the logic pointed to by field 7 of 9
The IF statement is changed to a simple GoTo statement for block 11, and at the same time, the control transfer information for block 10 is deleted. In other words, the entry of block 10 on the FLINK sequence pointed to by field 4 of BLOCKT of block 9 is erased, and at the same time the entry pointed to by field 5 of BLOCKT of block 10 is deleted.
Delete the entry in block 9 on BLINK.
In this case, since block 9 is the only entry, there is no subsequent block, and field 5 is filled with zeros (see a→b in FIG. 9). Then,
All blocks are checked again, and for blocks that do not have a backward block, the control movement destination information from there is deleted. That is, block 10
Delete the entry of block 11 on FLINK pointed to by BLOCKT field 4, and
BLINK pointed to by BLOCKT field 5 of
Erase the entry in block 10 above. This process continues until blocks with no blocks behind them disappear. This process always ends in a finite number of times, and if an inner loop is not included, the result of control path deletion can be correctly transmitted to all blocks in the end. (Fig. 9b→c).

After that, block 9, which had a change in control movement,
After checking the sentence intermediate words of block 11 using field 7 of BLOCKT and confirming that they do not perform any operation, block 8 is checked as shown in Figure 9d.
BLOCKT field 1 of block 12
By rewriting BLOCKT to the beginning, blocks 9 and 11 are deleted.

Control structure simplification through such expansion can be similarly implemented for conditional expressions regarding the final values of control variables.

If the control/dominance relationship changes as a result of the expansion processing described above, it is also updated.

After simplifying the end point condition elimination and analyzing the control-dominance relationship, we change the control-movement relationship to apply vector calculations.

Prior to explaining the changing method, the function of the control vector will be explained with reference to FIG. A control vector is a data string consisting of elements having a logical value of "0" or "1", and is used to display control information using data.

In other words, a vector comparison instruction such as VCGT compares each element of two vectors A and B, and as a result of comparing certain elements Ai and Bi, if the comparison is successful, a logical value of "1" is given, and if the comparison is not true, the logical value is "1".
Logical value "0" is set to the corresponding element of control vector CV
Leave as CVi. Next, for a vector addition instruction such as VEA that adds to vectors X and Y, the control vector CV generated in this way is
The elements of the control vector CV by working with
When the value of CVi is 1, perform addition of corresponding elements Xi and Yi, generate element Zi of result vector Z,
When the value of element CVi of control vector CV is 0, addition of these elements Xi and Yi is suppressed. In this way, the role of the control vector is to apply the result of element comparison of vectors A and B to vector calculations for other vectors X and Y.

The procedure for updating the inter-block control movement relationship for using the control vector in the example problem of FIG. 6 will be explained with reference to FIG.

The basic principle of the update is to change the large loop from block 14 to block 2 into a group of small loops that go around each block so that vector operations can be applied.

Conditional blocks are first classified into variable conditional blocks in which the values of variables or array elements constituting the conditional expression may change as the loop progresses, and invariant conditional blocks such as block 3, which do not change. This classification applies to this block.
This is done by checking the presence or absence of definitions or updates within the loop of variables and arrays forming the conditional expression for the sentence intermediate word obtained via field 7 of BLOCKT.

Next, loop variable condition blocks such as blocks 2 and 4 are made into small loops by inserting new blocks 20, 21, 22, 23, etc. for generating control vectors under the conditional expressions. Insertion of a new block is achieved by creating new tables as shown in FIG. 5a and changing the fields of blocks 2 and 13.
In block 20, it is determined whether array element C1(I) satisfies the conditions specified in block 2,
If this condition is met, set "1" to the corresponding element of CV1 of the control vector for block 2,
In block 21, a sentence intermediate word that sets "0" is generated ahead of field 7 of BLOCKT of these blocks, and similarly, in block 22,
At step 23, a sentence intermediate word is generated for setting the control vector CV2 for block 4 to ``1'' or ``0'' regarding array element C3(I).

On the other hand, for a loop invariant block such as block 3, a small soup is not created because arithmetic control can be performed by judgment/branch instructions without creating a control vector.

A non-conditional block determines whether or not to make a small loop depending on the type of the corresponding statement. Assignment statement blocks that use different values depending on the loop, such as blocks 5 and 12, are made into smaller loops, while non-operational blocks such as 6, 7, 8, and 13 are not made into smaller loops.

As the conditional block becomes a smaller loop, the control movement of the non-established block is changed. Block 8 is located on the non-established side of block 2, but the FLINK and BLINK of block 8 are updated and changed so that it receives control from the final block 7 on the established side as shown in FIG.

In order to implement the above-described short loop formation, it is confirmed in advance that the data dependencies between blocks do not contradict the short loop formation, and this is a known technique that is also required in conventional vector compilers.

After forming small loops, a target program including vector operations corresponding to each block or small loop is generated. The procedure is described below.

First, for the small loops of blocks 2, 20, 21, and 14, a code that generates the control vector CV1 is generated by vector comparison of conditions based on the sentence intermediate word pointed to by BLOCKT field 7, and point. The method of changing array elements in a conditional expression to vector representation is a known technique for conventional compilers.

For the following block 3, the conventional sentence intermediate word is used as an intermediate word for comparison and branching.

For the small loops of blocks 4, 22, 23, and 14, an intermediate word is first generated to generate the control vector CV2. By the way, the control block of block 4 is changed to block 3 by BLOCKT field 6.
Then, block 3 is found to be an invariant block by checking the sentence intermediate word, and has no control vector. However, since the control vector of block 3 is block 2, the control vector CV2 of block 4 is It is necessary to perform an AND with the control vector CV1 of block 2. So the control vector
Take the AND of CV1 and CV2 and create a new control vector
Add the intermediate word NCV to be CV2.

For the small loop containing block 5, the control block of block 5 is 4, and the control vector of block 4 is found to be CV2 by checking the sentence intermediate word, so the vector addition intermediate word VEA using that is found. Replace with (CV2).

Since blocks 6, 7, and 8 are non-operational blocks, a dummy intermediate word NULL is generated for them, and the small loop including block 12 is
Block 2 by CLINK fields 13 and 14
Since it is controlled by the non-establishment side of CV1, a vector addition intermediate word whose control vector is the negative form of CV1
Replace with VEA (CV1).

Finally, NULL for non-operation block 13
Replace it with an intermediate word.

The conversion procedure from an intermediate language to an executable object program on a processing device is straightforward and obvious from the prior art.

Through the above procedure, an object program using vector instructions is generated for a loop operation including multiple conditional statements, and high-speed processing by a vector processor is enabled.

According to the present invention, it becomes possible for a compiler to automatically generate vector instruction codes for loop operations including conditional statements, which has been difficult in the past. Furthermore, according to another invention of the present application, an object program including vector instructions can be automatically generated for a loop operation including multiple conditional expressions. Furthermore, according to another invention of the present application, a loop portion including an invariant conditional expression can also be efficiently converted into a target program. Therefore, with these inventions of the present application, the number of man-hours required to create a program for utilizing a vector processor can be significantly reduced.

[Brief explanation of the drawing]

Figure 1a is an example of a program for selective loop operations written using conditional statements, Figure 1b is an example of the above program using a merge function, Figure 1C is how it is executed using a merge instruction, and Figure 2 is an example of a different selective operation on the left side of an assignment statement, and FIG. 3 is an example of a program including multiple conditional statements. FIG. 4 shows an example of a loop operation including the conditional statement taken up in the embodiment, FIG.
Figure b is its abbreviation, Figure 6 is a diagram of inter-block control movement and control dominance relationships in the embodiment, Figure 7 is a work table diagram for analyzing inter-block control dominance relationships, and Figure 8 is loop development in the embodiment. As a result, Fig. 9 is an update/process diagram of the control movement relationship accompanying loop expansion, Fig. 10 is a functional explanatory diagram of control vectors, and Fig. 1
Figure 1 shows an update diagram of inter-block control transfer relationships for use of vector instructions and the generated target program. Explanation of the symbols and the meanings of the symbols in FIG. 5a are as follows. 1... Field for storing the address of the following block table (BLOCKT), 2
...Field to place the block type, 3...Statement number field, 4...Field to put the index of the control transfer destination table (FLINK), 5...Field to put the index of the control transfer source table (BLINK), 6... ...Field for placing the index of the control control table (CLINK), 7...Field for the start address of the sentence intermediate word, 8...Field for setting whether or not it is the end of a series of control transfer destination blocks, 9...For the control transfer destination block. 10: field for storing the block table address; 10: field for determining whether it is the last of a series of control transfer source blocks; 11: field for storing the block table address of the control transfer source block;
12...Field for setting whether it is the last of a series of control/dominance blocks, 13...Field for setting the block table address of the control/dominance block, 14...
Field 15 for identifying the control path exiting from the control dominant block... Field for storing the address of the block table (BLOCKT) of the equivalent backward definition block of the block in question.The meanings of the symbols in FIG. 7 are as follows. 16...Start address of block table (BLOCKT) during route exploration, 17
...Indicator of control movement source table (BLINK) during route exploration.

Claims (1)

[Scope of Claims] 1. Whether or not to execute an operation part in a loop part of a source program that specifies an operation on an element of a certain array data that has a subscript that depends on a loop repetition variable. Is there in the loop part at least one conditional statement that specifies a conditional expression regarding the value of any element of array data that has a subscript that depends on the loop repetition variable? When there is a first determination of whether or not and such a conditional statement,
A second determination is made to determine whether the calculation part is executed on the satisfied or unfulfilled side of the conditional expression, and when it is determined that such a conditional statement exists, the result of the second determination is A step for generating an instruction sequence for a vector processor using
Each time the loop part is repeated, it is evaluated whether this conditional expression holds true or not, and the result of the second determination is made among the vector data whose vector elements are elements belonging to the array data subjected to the operation in the calculation part. A compiling method comprising the steps of generating an instruction string for a vector processor that selectively performs the above operation on some vector elements determined depending on the above evaluation results. 2 The above instruction sequence for the vector processor evaluates whether the above conditional expression is satisfied or not every time the loop portion is repeated, and generates a control vector consisting of vector elements representing the evaluation result. 2. The compilation according to claim 1, comprising a sequence of instructions for a vector processor that controls whether or not to execute the operation on each element of the vector data depending on the control vector and the result of the second determination. Method. 3 The above instruction sequence for the vector processor evaluates whether or not the above conditional expression is satisfied each time the loop portion is repeated, and generates a control vector consisting of vector elements representing the evaluation result. A second controller that controls whether or not to perform the above operation on each element of the vector data depending on the vector processor instruction, the generated control vector, and the result of the second determination. Claim 2 containing instructions for a vector processor
Compilation method described in. 4 The second vector processor instruction is an operation instruction for a vector processor whose execution of operations is controlled by the control vector, or an operation instruction for a vector processor whose execution of operations is controlled by a control vector that is an inversion of the control vector. 4. The compiling method according to claim 3, including an arithmetic instruction. 5 The second vector processor instruction is a vector processor operation instruction in which the execution of the operation is controlled by the control vector when the operation part is executed on the side where the conditional statement is satisfied; 4. The compiling method according to claim 3, wherein the computation part is an arithmetic instruction for a vector processor in which execution of the computation is controlled by a control vector obtained by inverting the control vector when the computation part is executed on the non-fulfilling side of the conditional statement. 6 A multiplex function that controls whether or not to execute each calculation part in a loop part of a source program that specifies an operation on an element of a certain array data that has a subscript that depends on the loop repetition variable. The first conditional statement that specifies a conditional expression related to the value of an element of any array data whose index depends on the loop repetition variable is in the loop part. When there are such multiple conditional statements, a second determination is made to determine whether the calculation part is executed on the satisfied side or non-true side of each conditional expression, and such multiple conditional statements If there is, the step is to generate an instruction sequence for the vector processor using the result of this second determination, and it is evaluated whether each conditional expression is satisfied each time the loop part is repeated. , among the vector data whose vector elements are the elements of the array data specified in the calculation part, for some vector elements determined depending on the above evaluation results for each conditional expression and the above second determination results. A compilation method for generating an instruction sequence for a vector processor that selectively performs the above operations. 7 The above instruction sequence for the vector processor evaluates whether each conditional expression holds true each time the loop portion is repeated, and generates a control vector consisting of vector elements representing the evaluation results for each conditional expression. is generated in accordance with the conditional expression of 7. The compiling method according to claim 6, comprising a sequence of instructions for a vector processor. 8 The above instruction sequence for the vector processor evaluates whether or not each conditional expression holds true each time the loop portion is repeated, and generates a control vector consisting of vector elements representing the evaluation results for each conditional expression. A single control vector is created by combining a plurality of vector processor instructions, each generated in response to a conditional expression, and a control vector generated in response to each conditional expression. at least one second vector processor instruction that generates a vector processor, and executes the operation on each element of the vector data depending on the synthesized control vector and the result of the second determination. Claim 7 further comprising a third vector processor instruction for controlling whether or not.
Compile method as described. 9 The third vector processor instruction is a vector processor operation instruction whose execution is controlled by the combined control vector, or a vector whose execution is controlled by a control vector obtained by inverting this control vector. 9. The compiling method according to claim 8, including processor arithmetic instructions. 10 The third vector processor instruction is such that when the calculation part is executed on the side where multiple conditions determined by the multiple condition statements are satisfied, the execution of the calculation is controlled by the combined control vector. An arithmetic instruction for a vector processor, in which when the arithmetic part is executed on the side where the multiple conditions are not met, the execution of the arithmetic operation is controlled by a control vector that is an inversion of the control vector. The compiling method according to claim 8. 11 In the loop part of the source program,
For an operation part that specifies an operation on elements of a certain array data whose subscripts depend on the loop repetition variable, does the loop part have at least one conditional statement that controls whether the operation part is executed? If there is such a conditional statement, it determines whether the calculation part is executed on the satisfied side or the unfulfilled side of the conditional expression specified by the conditional statement, and then If there is a statement, the conditional expression specifies either a conditional expression of the first type that uses an element of a subscript that depends on the loop repetition variable of some array data, or a conditional expression that does not depend on the loop repetition. If there are both such a first-type conditional statement and a second-type conditional statement, determine whether the conditional expression specified by the second-type conditional statement holds true. After determining whether or not the second conditional statement is true, it generates an instruction to switch whether or not to execute the part of the loop excluding the second conditional statement based on the determination result, and executes the conditional expression specified by the first conditional statement. a step of generating a vector processor instruction sequence corresponding to a portion of the loop excluding the second conditional statement by using the above-mentioned determination result regarding
Each time the loop part is repeated, it is evaluated whether the conditional expression specified by the first conditional statement is satisfied, and the calculation part evaluates whether or not the conditional expression specified by the above-mentioned first conditional statement holds true, and the calculation part generates vector data whose vector elements are the elements of the array data to be operated on. It consists of a step of generating an instruction sequence for a vector processor that selectively performs the above operation on some vector elements determined depending on the evaluation result and the above judgment result regarding the conditional expression specified by the first conditional statement. How to compile.