JPH0522092A - Peak position detector - Google Patents

Abstract

PURPOSE:To exactly detect timing for the peak of an electric signal outputted from an equipment such as a sensor or the like without being affected by noise. CONSTITUTION:Analog/digital(A/D) conversion is successively executed to an input signal from the outside by an A/D converter 13 synchronously to a clock signal, and the A/D converted signal of arbitrary high-order bits is temporarily stored in a latch circuit 14 synchronously to the above-mentioned clock signal. A comparator 15 compares the signal of the high-order bits outputted from the A/D converter 13 with the output of the latch circuit 14, and the compared output and the output of an OR circuit 10, to which the signal of the high-order bits outputted from the A/D converter 13 is supplied, are inputted to an AND circuit 17. Then, the AND circuit 17 outputs timing for the peak of the input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak position detecting device capable of detecting an accurate peak position of a signal output from a device such as a sensor.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional peak position detecting device disclosed in, for example, Japanese Patent Publication No. 2-42435. In the figure, 1 is an external device such as a sensor (not shown)
Is applied to the input signal from the input terminal 1, 2 is a differential circuit for obtaining a differential waveform with respect to the time of the input signal from the input terminal 1, and 3 is a zero-cross detector for detecting the time when the differential waveform from the differential circuit 2 passes through the zero point 4 is a zero cross detector 3
Is an output terminal connected to. Differentiating circuit 2 is input terminal 1
A capacitor 5 connected to the capacitor 5, a linear amplifier 6 provided between the capacitor 5 and the zero-cross detector 3, and a feedback resistor 7 connected between the input and output ends of the linear amplifier 6.
It has a positive clamp diode 8 connected in parallel with the feedback resistor 7 and a negative clamp diode 9 connected in parallel with the positive clamp diode 8.

Next, the operation will be described with reference to FIG. First, the input signal Sa as shown in FIG. 7A is input to the differentiating circuit 2 from the input terminal 1. In the capacitor 5 of the differentiating circuit 2, charges are charged and discharged in accordance with the potential change of the input signal based on the capacitance C [F], so that the output becomes the potential difference across the feedback resistor 7 of the amplifier 6. Appears. Therefore, when the value of the feedback resistor 7 is R, the output potential change rate related to the potential difference across the feedback resistor 7 is C
It is proportional to R · dVi / dt (Vi is the input voltage). Here, since it is necessary to find the inflection point at the peak portion of the input signal Sa, it is assumed that the normal differential sensitivity CR is sufficiently large. Further, the positive and negative clamp diodes 8 and 9 prevent unnecessary output swing caused by increasing the sensitivity of the linear amplifier 6. For this reason, the waveform of the output signal Sb of the differentiating circuit 2 has its amplitude in the positive and negative directions limited to a predetermined width as shown in FIG. 7B. Further, the output signal Sb of the differentiating circuit 2 is supplied to the zero-cross detector 3, where the zero alternate time is detected, and the zero-cross output signal Sc as shown in FIG. 7C is generated at the output terminal 4. This zero-cross alternating time coincides with the rising of the zero-cross output signal Sc from the L level to the H level. Noise (FIG. 3) based on various factors is added to the actual input signal Sa, and it is difficult to detect the zero-cross depending on the amount of the noise. This is generally an unstable element such as a time lag of the input signal on the clock measurement due to the cause of noise and the like.
tter). The time jitter, which is the time shift of the input signal, is represented as a time delay with respect to the signal waveform of the solid line as shown by the broken line in FIG.

[0004]

Since the conventional peak position detecting device is constructed as described above, the peak position of the input signal to be detected is a constant noise amount of the measurement system and the peak of the input signal Sa. Since it depends on the curvature, the effect of the time jitter cannot be eliminated unless the noise amount is extremely reduced, and the peak position of the input signal waveform cannot be detected accurately.

The present invention has been made in order to solve the above problems, and it is possible to accurately detect the peak position of an input signal without being affected by noise in the input signal. The purpose is to obtain the device.

[0006]

SUMMARY OF THE INVENTION A peak position detecting device according to the present invention comprises an A / D converter for analog-digital converting an input signal in synchronization with a clock signal and the A / D converter in synchronization with the clock signal. A latch circuit for temporarily storing the upper bit data of the output of the D converter, a comparator for comparing the output of the latch circuit with the upper bit data of the output of the A / D converter, and the A / D It is provided with a high-order bit data of the output of the converter and a logic circuit for logically processing the output of the comparator.

[0007]

In the present invention, adjacent A / D conversion result data are successively compared, and a pulse signal is output when it is determined that they are equal. Further, since any lower bit of the A / D conversion result is not included in the comparison data, the influence of noise on the input signal can be avoided.

[0008]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 10 is an input terminal to which a signal is input from an external device (not shown) such as a sensor, 11
Is a clock input terminal for inputting a clock signal for operating the A / D converter and the latch circuit incorporated in the peak position detecting device, and 12 is a peak position of the signal input from the input terminal 10 as a pulse signal An output terminal for outputting, 13 is a signal input from the input terminal 10, for example, 6
A for converting to bit digital code data
A / D converter, 14 is, for example, the upper 4 from the A / D converter 13.
A latch circuit for inputting and temporarily storing the data of the bits D ₂ , D ₃ , D ₄ , and D ₅ , and 15 is the upper 4-bit data from the A / D converter 13 and the latch circuit 14 for temporary storage. Comparator for inputting the 4-bit data stored in, and outputting an H-level signal only when two 4-bit data are compared and both are equal, and 16 is the upper 4 bits of the A / D converter 13 OR that inputs data and outputs H level signal if at least 1 bit is H level
A circuit 17 is an AND circuit which inputs the output signals of the OR circuit 16 and the comparator 15 and outputs an H level signal only when the two inputs are both at the H level. The AND circuit 17
The signal output from is output to the outside of the device at the output terminal 12. The OR circuit 16 and the AND circuit 17 form a logic circuit.

Next, the operation of FIG. 1 will be described with reference to FIGS. It is assumed that a signal as shown in FIG. 2 is input to the input terminal 10 from an external device (not shown) such as a sensor. The A / D converter 13 performs analog-to-digital conversion on the signal from the input terminal 10 and outputs data D ₀ , D ₁ , D ₂ ,
Each of D ₃ , D ₄ , and D ₅ is H level or L level 2
Output a digitized signal. The combination of output values is 2 ⁵ = 64
There are 64 patterns. For example, assuming that the power width of the signal input from the input terminal 10 is adjusted to 0 to 64 [V], if 1 [V] is input, only the data D ₀ that is the least significant bit is output. It is H level, and when 3 [V] is input, the data of D ₀ and D ₁ becomes H level. The output of the A / D converter 13 is from the L level to the H level of the clock signal input from the clock input terminal 11 to the T terminal.
The data of the upper 4 bits D ₂ , D ₃ , D ₄ , and D ₅ that change in synchronization with the rising to the level are input to the latch circuit 14, the comparator 15, and the OR circuit 16, respectively. The latch circuit 14 capable of temporarily storing the data from the A / D converter 13 operates with the same clock signal as the clock signal input to the A / D converter 13, and its output Q _0. , Q ₁ , Q ₂ and Q ₃ are data which are earlier than the inputs D ₀ , D ₁ , D ₂ and D ₃ from the A / D converter 13 by one cycle of the clock. The outputs D ₂ , D ₃ , D _{4 of} the A / D converter 13,
FIG. 4 shows the changes over time of D ₅ and the outputs Q ₀ , Q ₁ , Q ₂ and Q ₃ of the latch circuit 14. As shown in FIG.
The / D converter 13 outputs the data in the order of 1-2-3-4, and the output of the latch circuit 14 becomes the data which is one cycle earlier than the output of the A / D converter 13. There is. The comparator 15 compares the output of the A / D converter 13 with the output of the latch circuit 14, but the rate of change in the input signal waveform of FIG. 2 is extremely small, t ₁ −t ₂ , t ₄ −t ₅ , t ₇ −. t ₈
In the interval, A ₁ is the comparison input by the comparator 15, A _2, A
The data of ₃ , A _{4 and} the data of B ₁ , B ₂ , B ₃ , B ₄ match, and an H level signal is output from the = output terminal of the comparator 15. Meanwhile, the _{t 2 -t 4, t 5 A} 1 larger change rate of the input signal in a section of _{-t 7, A 2, A 3} , A 4 of the data and _{B 1, B 2, B 3} , B 4 The data is different,
An L level signal is output from the output terminal of. Noise is added to the actual signal input from the input terminal 10, as shown in FIG. it can. In this embodiment, the noise level is 3
The noise is avoided by assuming that it is within [V _PP ] and unwiring the lower 2 bits D ₀ , D ₁ or the data line. In addition, the signal input from the input terminal 10 is 3 [V].
When the value exceeds the upper limit, the upper 4 bits D ₂ , of the A / D converter 13
At least one of the data of D ₃ , D ₄ , and D ₅ becomes H level, and the output of the OR circuit 16 becomes H level. Figure 2
The output of the interval OR circuit 16 of t ₂ -t ₇ becomes H level. The AND circuit 17 outputs the H level during the period of t ₂ -t _{7 in} which the output of the OR circuit 16 becomes the H level, and only when the output of the = output terminal of the comparator 15 becomes the H level. This shows the section of the peak t ₄ -t ₅ of the input signal waveform of FIG. Output of the = output terminal of the comparator 15, A / D
FIG. 5 shows the changes over time in the outputs D ₂ , D ₃ , D ₄ , D _{5 of} the converter 13, the output of the OR circuit 16 and the output of the AND circuit 17. As shown in FIG. 5, the AND circuit 1
Reference numeral 7 outputs an H level signal at the peak position of the input signal waveform.

Embodiment 2. Although the A / D converter 13 has a 6-bit output in the above embodiment, the number of bits can be increased depending on the accuracy of the peak position to be detected. In addition, in order to avoid noise, the A / D converter 13
Although the lower 2 bit line of the output of 1 is left unwired, the number of bits can be increased depending on the level of noise to be avoided.

[0011]

As described above, according to the present invention, in the data digitized by sequentially A / D-converting the input signal, any lower bit that affects noise is ignored, and the upper bit conversion result is obtained. Since the peak position is detected by comparing the adjacent data in (1), there is an effect that the peak position of the input signal can be accurately detected without being affected by noise. Further, according to the present invention, the A / D converter of the input signal is synchronized with the clock input from the outside, but by increasing the frequency of this clock, a more accurate peak position can be detected. It also has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a peak position detecting device according to the present invention.

FIG. 2 is a diagram showing a position example of a signal input to the peak position detecting device according to the present invention.

FIG. 3 is a diagram showing an example of an actual signal in consideration of input noise.

FIG. 4 is a diagram comparing and comparing output states of an A / D converter and a latch circuit incorporated in the peak position detecting device according to the present invention.

FIG. 5 is a diagram showing the timing at which the peak position is detected by the operation inside the peak position detecting device according to the present invention in comparison with FIG.

FIG. 6 is a configuration diagram showing a conventional peak position detecting device.

FIG. 7 is a diagram showing a signal operation in a conventional peak position detecting device.

[Explanation of symbols]

 13 A / D converter 14 Latch circuit 15 Comparator 16 OR circuit 17 AND circuit

Claims (1)

Claim: What is claimed is: 1. An A / D converter for analog-digital converting an input signal in synchronization with a clock signal, and an upper bit of an output of the A / D converter in synchronization with the clock signal. Latch circuit for temporarily storing the data of the above, a comparator for comparing the output of this latch circuit and the upper bit data of the output of the A / D converter, and the upper bit of the output of the A / D converter A peak position detecting device comprising a logic circuit for logically processing data and an output of the comparator.