JPH05219360A - Picture processor - Google Patents

Abstract

PURPOSE:To prevent the disturbance of a picture at joints between shuttle scannings by setting the relation of position between a picture element before conversion and a picture element after conversion so as to have no deviation between scannings. CONSTITUTION:Picture data from a picture output device are inputted in a serial form, and picture element data are inputted to a vertical/horizontal writing conversion processing section 1603 in a prescribed order. The address of the data is sequentially stored in a picture storage section 1605 from the processing section 1603. An address generated by a write address counter 2101 at write is realized for vertical/horizontal writing conversion and the picture data are converted in a raster form. In this case, a vertical/horizontal writing conversion processing section 1604 at a printer side converts the data from the raster form into the serial form, the address is generated and the picture data are read and then the data are read by a scanner 1601 in the serial form. The read picture is subject to magnification processing by a linear interpolation processing section 1602 and the vertical/horizontal writing conversion processing section 1603 applies vertical/horizontal writing conversion to the data and the result is stored in the storage section 1605. Then the capacity of a line buffer is enough to be that equivalent to a shuttle width and disturbance of a picture at joints of shuttle scannings is not caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for performing scaling processing on serial format image data.

[0002]

2. Description of the Related Art In the scaling processing of image data, it is necessary to generate new pixels (post-conversion pixels) generated after the scaling processing from each pixel (pre-conversion pixel) data of the original image data.

Conventionally, in an image processing apparatus that handles serial format image data, there is a method of scaling the image data for each scanning as a method for scaling the image data. This is to generate newly generated post-conversion pixels from the input serial image data by successively interpolating (for example, linearly interpolating) from the information of the pre-conversion pixels. The position of the converted pixel to be interpolated is determined by the value of the set scaling ratio.

[0004]

In the above-mentioned conventional example, 1
The positional relationship between the post-conversion pixel and the pre-conversion pixel generated by the scaling processing of the image data in the scan serial format is the same throughout each scan. For this reason, the intervals of the converted pixels at the seams between the scans may be different from the intervals of the other portions, and the image may be disturbed.

The present invention has been made in view of the above problems, and an image for preventing image distortion at a joint between shuttle scans when performing scaling processing of serial scan image data for one scan. An object is to provide a processing device.

[0006]

An image processing apparatus according to the present invention for achieving the above object has the following configuration. That is, an image processing apparatus that performs scaling processing on serial format image data, performs scaling processing on the image data for each scan based on the set scaling ratio, and converts the pixel data after conversion. And a setting unit that sets the position of the post-conversion pixel generated by the scaling process with respect to the pre-conversion pixel for each scan.

[0007]

With the above configuration, when performing the scaling process on the serial format image data for one scan, the positional relationship between the pre-conversion pixel and the post-conversion pixel is set so that there is no deviation between the scans. It prevents the image from being disturbed at the seams between the scans.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 13 is a view best showing the present invention. Reference numeral 1601 is a scanner for reading an image in a serial format, 1602 is a linear interpolation processing section for performing a scaling process by a linear interpolation method, and 1603 is a raster format image for raster. A vertical / horizontal conversion processing unit 1604 for converting into a format, a vertical / horizontal conversion processing unit 1604 for converting an image in a raster format into a serial format,
Is an image storage unit for storing image data in a raster format, 16
A printer 06 prints an image in a serial format.

First, the serial format will be described.
FIG. 16 is a diagram for explaining the serial format.
Reference numeral 01 is a read head in the case of a scanner and a print head in the case of a printer. Reference numeral 1902 is a reading element such as a CCD in the case of a scanner and a print nozzle or a print head in the case of a printer. 1903 is 1
It represents the second scanning area, and 1904 represents the second scanning area. Reference numeral 1905 represents one page of paper.

The serial format is one in which one page is read or printed by scanning a plurality of times with a predetermined scanning width as shown in FIG. Hereinafter, this one scan is called a shuttle operation.

The linear interpolation method will be described in detail below with reference to the accompanying drawings. In this description, the main scanning direction and the sub-scanning direction in the serial format will be described. Therefore, the main scanning direction in the raster format is the sub scanning direction in this description. The sub-scanning direction in the raster format is the main scanning direction in this description.

FIG. 1 is a block diagram showing the arrangement of a linear interpolation processing unit (hereinafter referred to as a device) according to this embodiment. In the same figure, the input image signal is
The line is delayed, and the flip-flops 102 and 103 delay one pixel. Further, the oscillator 131 generates an image clock, and the line synchronization signal generation device 132 generates a line synchronization signal.

In addition, the present apparatus uses multipliers 104 to 10
7, 113, adders 108 to 110, a calculation unit 111 that calculates the length of the side in the main scanning direction, a calculation unit 112 that calculates the length of the side in the sub-scanning direction, and a fixed value (128 here) are output. Block 114, subtractors 115 to 118, inverters 119, 120, 125, 126, AND gate 1
21, 122, 129, 130, OR gates 123, 1
24 and NAND gates 127 and 128, and performs a predetermined calculation described later.

FIG. 2 shows the relationship between points before conversion and points after conversion in the linear interpolation method. In the figure, point V, point W, point X,
The point Y represents the point before conversion. Further, the brightness levels of the respective points are set to v, w, x, and y, respectively.

The point after conversion is point P, and the positional relationship between point P and the point before conversion is from point V to La and point W to Lb in the main scanning direction (left-right direction in the figure), and In the scanning direction (vertical direction in the figure), it is assumed that the positions are from point V to Ka and from point X to Kb. In this embodiment, the length of one side before conversion is 1
Since it is considered as 28, La + Lb = 128, Ka + K
b = 128.

Therefore, the brightness level p of the point P in FIG. Becomes

FIG. 3 is a timing chart of image signals handled by this apparatus. In the figure, shuttle synchronization signal 3
1 is a high active signal which becomes High as a logic level during the period in which the image signal of 1 shuttle is valid, and the line synchronization signal 32 becomes High in the period during which the image signal for one line is valid. This is a high active signal. Further, the image synchronization clock 33 is a clock output in units of one pixel, and the image signal is output in synchronization with the rising edge of this clock. The image signal 34 is multi-valued data composed of 8 bits per pixel.

FIG. 11 is a block diagram showing the relationship between the linear interpolation processing section 1602 and the image supply source 1101 according to this embodiment. Further, FIG. 12 is a timing chart of signals of the image supply source 1101 and the linear interpolation processing unit 1602.

In FIG. 11, the signal output from the image supply source 1101 is the same as the image signal shown in FIG. 3, but the linear interpolation processing section 1602 supplies a line request signal and an image request clock to the image supply source. Output. Then, as shown in FIG. 12, when the line synchronization signal is input from the linear interpolation processing unit to the image supply source, the image supply source outputs the image signal. The image supply source updates the image signal when the image request clock is input. That is, it is possible to stop the supply of the image by controlling the line request signal and the image request clock.

<Description of Level Calculation Method> A level calculation method in the apparatus according to the present embodiment will be described.

The image signal is input line by line as shown in FIG. 3, and is delayed by one line in the line buffer 101 shown in FIG. Here, the signal delayed by one line is delayed by one pixel in the flip-flop 102, and the data is v, and the image data not passing through the flip-flop 102 is w. Further, it is assumed that the image data delayed by one pixel in the flip-flop 103 by the input image signal without line delay is x, and the pixel data not passing through the flip-flop 103 is y. In this way, the four reference points necessary for the processing by the linear interpolation method can be referred to at the same time.

The main scanning direction side calculation unit 111 of FIG. 1 has a function of calculating and outputting La described above, a signal for thinning out an image synchronization clock when reducing in the main scanning direction, and an expansion in the main scanning direction. Has a function of outputting a main scanning direction control signal which is a signal for thinning out the image request clock output to the image signal supply source when performing the above. Also,
The sub-scanning direction side operation unit 112 has a function of calculating and outputting Ka, and a signal for thinning out the line synchronization signal when performing reduction in the sub-scanning direction and an image signal when performing enlargement in the sub-scanning direction. It has a function of outputting a sub-scanning direction control signal which is a signal for thinning out the image request signal output to the source.

The minimum value of both La and Ka is 0, and the maximum value is 80H (H represents a hexadecimal number). Further, in this embodiment, the number of internal operation bits is all 8 bits.

In calculating the level, La output from the main scanning direction side calculation unit 111 and the sub-scanning direction side calculation unit 1
From Ka output from 12, La · Ka / 128, L
a ・ Kb / 128, Lb ・ Ka / 128 and Lb ・ Kb
It is necessary to calculate / 128. Here, it is all divided by 128 because the maximum value of the side length is 80H, so when the maximum values are multiplied by each other, it becomes 4000H,
This is because the upper 15th bit to the 8th bit are valid.

The multiplier 113 is a side scanning direction computing section 11 in the main scanning direction.
La output from 1 is multiplied by Ka output from the side calculation unit 112 in the sub-scanning direction to output the lower 15th bit to the 8th bit. This value is La · Kb / 128. In addition, the subtractor 116 changes from La to La · Ka / 12
La · Kb / 128 is obtained by subtracting 8.
This is because La = La · (Ka + Kb) / 128.

Similarly, the subtractor 117 operates from Ka to La ·
By subtracting Ka / 128, Lb · Ka / 12
8 is obtained, and La is obtained by subtracting La from 128 by the subtractor 115. Further, the subtractor 118 is
From the output of the subtractor 115, Lb to Lb · Ka / 128
Lb · Kb / 128 is obtained by subtracting.

The multiplier 104 has the above-mentioned v and Lb · Kb /
128 is multiplied, and the lower 15th bit to the 8th bit are output. This value is v · Lb · Kb / 16384. Further, the multiplier 105 multiplies w by La · Kb / 128 and outputs the lower 15th bit to the 8th bit. This value is w · La · Kb / 16384. Further, the multiplier 106 multiplies x by Lb · Ka / 128 and outputs the lower 15th bit to the 8th bit. This value is x · La · Ka / 16384. Then, the multiplier 107 multiplies y by La · Ka / 128 and outputs the lower 15th bit to the 8th bit. This value is y
La · Ka / 16384.

The adder 108 adds the output of the multiplier 104 and the output of the multiplier 105, and outputs the lower 9th bit to the 2nd bit. This value is (vLbKb + w
・ La ・ Kb) / 32768. The adder 109 is
The output of the multiplier 106 and the output of the multiplier 107 are added, and the lower 9th bit to the 2nd bit are output. If this value is (x
・ Lb ・ Ka + y ・ La ・ Ka) / 32768.
Further, the adder 110 adds the output of the adder 108 and the output of the adder 109, and outputs the lower 9th bit to the 2nd bit. This value is the level p of the point P, that is, (v · L
b ・ Lb + w ・ La ・ Kb + x ・ Lb ・ Ka + y ・ La
-Ka) / 65536.

<Description of Sync Signal Control Method> Next, the sync signal control method will be described using specific numerical values by dividing it into cases of reduction, enlargement and equal magnification.

FIG. 4 is a block diagram showing a detailed configuration of the side-direction calculator 111 in the main scanning direction shown in FIG. In the figure, a block 401 having a value of n-128 and a block 402 having a value of n are input to a selector 403, and the selector 403 outputs a reduction * / enlargement signal to its S terminal to a logical L level.
When it is ow, the value of block 401 is output, and when it is High, the value of block 402 is output. The block 404 has a value of −128, and the block 405 has n−.
It has a value of 128. Then, the selector 406 inputs the values of the blocks 404 and 405, and outputs the value of the block 404 when the reduction * / enlargement signal to the S terminal is Low, Hi.
When it is gh, the value of block 405 is output.

The selector 409 includes adders 407 and 408.
When the carry of the adder 408 is 0, the value of the adder 407 is output, and when the carry of the adder 408 is 1, the value of the adder 408 is output. The output of the selector 409 is input to the 8-bit latch 410. The initial value setting block 411 has an initial value of the positional relationship between the pixel before conversion and the pixel after conversion, and the value can be rewritten by a CPU (not shown). Then, the selector 412
Inputs the values from the initial value setting block 411 and the latch 410, outputs the value of the initial value setting block 411 when the first pixel data is input, and outputs the value of the latch 410 after the second pixel. To do. The select signal to the selector 412 is generated by delaying the line synchronization signal by one pixel by the flip-flop 413. The carry signal of the adder 408 is also used to control the image synchronization clock for the reduction process in the main scanning direction and the image request clock for the enlargement process. By setting the initial value of the initial value setting block 411 for each scan by a CPU (not shown), the position of the converted pixel between the scans is adjusted.

During the reduction processing in the main scanning direction, the reduction * / enlargement signal in the main scanning direction becomes Low, so in FIG.
The input terminal a of the AND gate 121 becomes High. Therefore, the main scanning direction control signal output from the main scanning direction side calculation unit 111 becomes valid, and the output image synchronization clock is controlled by the OR gate 123. When this main scanning direction control signal is Low, the output image synchronization clock is output, and when it is High, it is thinned out. At this time, A
Since the input terminal c of the ND gate 122 is Low, O
The input terminal f of the R gate 124 also becomes Low, and the image request clock is always output.

When enlarging in the main scanning direction, the reduction * / enlargement signal in the main scanning direction becomes High,
Since the input terminal c of the AND gate 122 also becomes High, the main scanning direction control signal becomes valid, and the OR gate 12
The image request clock is controlled by 4. Therefore, the image request clock is output when the main scanning direction control signal is High, and is thinned out when it is Low. At this time, the input terminal a of the AND gate 121 becomes Low, and the OR gate 1
Since the input terminal e of 23 is also always Low, the output image synchronization clock is always output.

Since the processing in the sub-scanning direction is also the same as that in the main scanning direction, its explanation is omitted here.

Next, the operation of the main scanning direction side calculation unit 111 will be described using specific numerical values.

<Explanation of Reduction Processing> FIG. 5 shows 128/20.
.. represents the reference length before conversion, and D1, D2, D3, ... after conversion represent the lengths of sides when the reduction processing of 0 times (64%) is performed. Of pixels. Moreover, the numerical value enclosed with a circle represents the value of La.

FIG. 6 is a timing chart when the reduction processing of 128/200 times is performed. 6, the clock is the basic operation clock generated by the oscillator 131 of FIG. The image request clock is a clock output to the image supply source, and the image supply source is
The image signal is output in synchronization with this clock. The output value of 407 is the output value of the adder 407 of FIG. 4 showing the internal configuration of the main scanning direction side calculation unit 111 of FIG. The output value of 408 and the carry of 408 are also output values of the adder 408.

As described above, La is the side length calculation result of the main scanning direction side calculation unit 111 in FIG. 1, and Lb is the calculation result.
This is the output value of the subtractor 115 in FIG. The input line synchronization signal is a line synchronization signal input from the image supply source to the linear interpolation processing unit. v, w, x, and y indicate reference pixels, 1, 2, 3, ... Denote numbers sequentially assigned to pixels in the main scanning direction, and a, b ,. The output line synchronization signal, output image synchronization clock, and output image signal are image signals output from the linear interpolation processing unit.

When the reduction processing is performed, as shown in FIG.
The reduction * / enlargement signal at is low and the selector 4
03 selects the value of block 401. This block 4
01 has a value of n-128, but since n = 200 here, its value is 72. The selector 406 also selects the value of block 404, which is -1.
It has a fixed value of 28.

The value of the initial value setting block 411 having the initial value of the side is 64 here. Since the selector 412 first selects the value of the initial value setting block 411, the calculation result in the adder 407 is 64 + 72 = 136, and the calculation result in the adder 408 is 64 as shown in FIG.
-128 = -64 <0. Since the operation result of the adder 408 is a negative number, the carry is 0. Therefore, La
= 64 and output. Then, the selector 409 selects the value of the adder 407, that is, 136, and the latch 410
Takes in this value at the timing of the rising edge of the image synchronization clock, and its output value becomes 136.

Next, the selector 412 selects the value of the latch 410, and the operation result of the adder 407 is 136 + 72 = 2.
08, the calculation result of the adder 408 is 136−128 = 8
Since ≧ 0, the carry of the adder 408 becomes 1.
At this time, the output image synchronization clock is gated and thinned. Further, the selector 409 selects 8 which is the value of the adder 408, and the latch 410 fetches this value at the rising edge of the image synchronization clock, so that the output value is 8.

The operation result of the adder 407 is 8 + 7.
2 = 80, the operation result of the adder 408 is 8-128 = -1.
Since 20 <0, the carry of the adder 408 becomes 0. Therefore, La = 8 is output. Further, the selector 409 selects the value 80 of the adder 407, and the latch 412
Captures this value. Thereafter, similarly, the value of the side is calculated as shown in FIG.

FIG. 6 is a timing chart showing the above operation. The data of the interpolated pixel at the position of La = 64 is calculated at the rising edge of the image request clock S2, and the calculated pixel data is output as the output image signal P1 at the rising edge of the output image synchronization clock D1. The carry of the adder 408 is "1".
When, the output image synchronization clock is thinned out.

<Explanation of Enlargement Processing> FIG. 7 shows 128/10.
It represents the length of the side when the enlargement processing of 0 times (128%) is performed. The meanings of the symbols here are the same as those in FIG.

FIG. 8 is a timing chart when the enlargement processing of 128/100 times is performed. Since each signal here is the same as the signal shown in FIG. 6, the description thereof is omitted. The operation of the linear interpolation processing unit in the enlargement processing will be described below with reference to FIGS. 4, 7, and 8.

As described above, during the enlargement processing, the reduction * / enlargement signal shown in FIG. 4 becomes High, and the selector 403 selects the value of the block 402. The block 402 has a value of n, but since n = 100 here, the output value of the selector 403 is 100. Also, the selector 406
Selects the value of block 406 and this block 405 has a value of n-128, so that when n = 100, the value of block 405 is 100-128 = -28.

If the initial value of the side of the initial value setting block 411 is 64, the selector 412 initially selects the value of the initial value setting block 411.
The calculation result in 7 is 64 + 100 = 164, the adder 408
The carry result of the adder 408 is 1 because the result of the calculation at is −28 = 36 ≧ 0. Therefore, the image request clock is output to the image supply source and the pixel to be referred to next is updated. Then, the side length is output as La = 64. Further, the selector 409 selects the value 36 of the adder 408, and the latch 410 fetches this value at the rising edge of the image synchronization clock, and its output value becomes 36.

Since the selector 412 selects the value of the latch 410, the operation result of the adder 407 is 36 + 100 = 1.
36, the carry of the adder 408 is 1 because the calculation result of the adder 408 is 36−28 = 8 ≧ 0. Therefore, the image request clock is output and the pixel to be referred to next is updated. Then, the side length is output as La = 36. Further, the selector 409 selects the value 8 of the adder 408, and the latch 410 fetches this value at the timing of the rising edge of the image synchronization clock, and the output value thereof is 8.
Becomes

The calculation result in the adder 407 is 8 + 100 =
108, and the operation result of the adder 408 is 8-28 =
Since −20 <0, the carry of the adder 408 becomes 0. Therefore, the image request clock is thinned out so that the pixel to be referred to next is not updated. The side length is output as La = 8. Selector 409 is adder 40
The value 108 of 7 is selected and the latch 412 captures this value. Thereafter, similarly, the value of the side is calculated as shown in FIG.

As described above, the calculation processing of the side length in the main scanning direction is performed.

The sub-scanning direction side arithmetic unit for performing arithmetic processing of the side length in the sub-scanning direction has the same configuration as the main scanning direction side arithmetic unit, and the calculation method therefor is also the main scanning direction. It is almost the same as the side calculation unit. Therefore, the latch 41
A pulse is used once per line instead of the clock of 0, and the adder 40 is used when the reduction processing in the sub-scanning direction is performed.
The carry signal of No. 8 is used as a gate signal for the line synchronizing signal, and when performing enlargement processing, it is used as a gate signal for the line request signal for the image supply source. The calculation method in the sub-scanning direction can be explained by replacing the reference pixel with the reference line. The level of the output pixel is calculated from the area of the rectangle formed by the reference pixel level, the pre-conversion pixel and the post-conversion pixel as described above.

<Explanation of equal-magnification processing> FIG. 9 is a diagram showing a case where equal-magnification processing is performed by a calculation method of reduction processing.
[Fig. 6] is a diagram corresponding to a case of performing equal-magnification processing by a calculation method of enlargement processing.

FIG. 9 shows the length of the side when the reduction processing of 128/128 times (100%) is performed. Since the reduction process is performed here, the reduction * / enlargement signal shown in FIG. 4 becomes Low as described above, and the value of the block 401 of the selector 403 is selected. Block 401 is n-128
However, since n = 128 here, the value is 0. The selector 406 also selects the value of block 404, which has a fixed value of -128.

Initial value setting block 41 having initial values of sides
The value of 1 is 64. Initially, the value of the initial value setting block 411 is selected by the selector 412.
Since the calculation result in 07 is 64 + 0 = 64 and the calculation result in the adder 408 is 64-128 = -64 <0, the carry of the adder 408 is 0. Therefore, La = 64 is output. Further, the selector 409 selects the value 64 of the adder 407, and the latch 410 fetches this value at the timing of the rising edge of the image synchronization clock, and the output value becomes 64.

Since the selector 412 selects the value of the latch 410, the operation result of the adder 407 is 64 + 0 = 64,
Since the operation result of the adder 408 is 64-128 = -64 <0, the carry of the adder 408 is 0. Therefore, La = 64 is output. Also, the selector 409
Selects the value 64 of the adder 407, and the latch 410 captures this value at the rising edge of the image synchronization clock, and its output value becomes 64. Thereafter, the side value is similarly calculated, La is always 64, the carry of the adder 408 is always 0, and the output clock is always output. In this way, equal-magnification processing is performed using the calculation method of reduction processing.

Next, the case of performing the same-size processing by the calculation method of the enlargement processing will be described.

FIG. 10 shows the length of the side when 128/128 (100%) enlargement processing is performed. As described above, when the enlargement processing is performed, the reduction * / enlargement signal of FIG. 4 becomes High, and the selector 403 selects the value of the block 402. This block 402 has a value of n,
Since n = 128 here, the output value of the selector 403 is 128. The selector 406 is a block 40.
5 is selected and block 405 has a value of n-128, but since n = 128, that value is 128-128 =
It becomes 0.

Initial value setting block 4 having initial values of edges
Assuming that the value of 11 is 64, the selector 412 first selects the value of the initial value setting block 411.
The calculation result in 7 is 64 + 128 = 192, and the adder 408
The result of the calculation at 64 + 0 = 64 ≧ 0 is
The carry of 8 becomes 1. Therefore, the image request clock is output to the image supply source and the pixel to be referred to next is updated. Then, the side length is output as La = 64.

Further, the selector 409 selects 64, which is the value of the adder 408, and the latch 410 fetches this value at the rising edge of the image synchronization clock, and its output value becomes 64. Next, since the selector 412 selects the value of the latch 410, the operation result of the adder 407 is 64+.
128 = 192, the calculation result in the adder 408 is 64 + 0
= 64 ≧ 0, and the carry of the adder 408 becomes 1. Therefore, the image request clock is output and the pixel to be referred to next is updated. Then, the side length is output as La = 64.

The selector 409 selects the value 64 of the adder 408, and the latch 410 fetches this value at the timing of the rising edge of the image synchronization clock, and its output value becomes 64. Thereafter, the side value is similarly calculated, La is always 64, the adder carry of 408 is always 1, and the image request clock is always output. As described above, the same-magnification processing is performed even when the calculation method of the enlargement processing is used.

When executing the scaling processing in the shuttle unit as described above, it is necessary to pay particular attention to the next shuttle. FIG. 14 is a diagram showing images before and after conversion at the joints of the shuttle, in which ◯ marks are pixels before conversion and X marks are pixels after conversion. This figure shows an example in which the initial value in the main scanning direction of the second shuttle is set so that the post-conversion pixel interval between shuttles is constant, and the post-conversion pixel interval is constant even at the joints between shuttles ( h). The main scanning direction and the sub scanning direction in this figure are based on the serial format. For comparison, FIG. 15 shows an example in which the initial value of the second shuttle is the same as the initial value of the first shuttle.
If the initial value of the post-conversion pixel position is constant in this way, the interval between the post-conversion pixels (marked x) at the joint between the first shuttle and the second shuttle will not be constant (h ≠ h '). In FIG. 14 or FIG. 15, in order to execute the linear interpolation on the post-conversion pixel at the bottom of the first shuttle, the data of the pre-conversion pixel at the top of the second shuttle is required. In the shuttle scanning in the present embodiment, the pixel data of the uppermost stage of the second shuttle is also read in the first shuttle, which enables the linear interpolation of the converted pixels in the lowermost stage. That is, the uppermost pixel of the second shuttle is read by both the first shuttle and the second shuttle.

Next, the vertical / horizontal conversion processing unit will be described. The vertical / horizontal conversion processing unit 1603 on the reading side performs conversion from serial format to raster format. Further, the print side vertical / horizontal conversion processing unit 1604 converts the raster format to the serial format.

FIG. 19 is a block diagram of the vertical / horizontal conversion processing section. 2101 is a write address counter, 2102 is a read address counter, 2103 is a multiplexer, 1
An image storage unit 605 is provided.

First, the vertical / horizontal conversion from the serial format to the raster format will be described. FIG. 17 shows serial format image data, which has 256 pixels in the main scanning direction and 4 pixels in the sub scanning direction.
It is a figure which shows the coordinate of 096 pixels. FIG. 18 is a table showing the relationship between storage addresses and data. First, since image data is input from the image output device in a serial format, pixel data is input to the vertical / horizontal conversion processing unit 1603 in the order of (1, 1), (2, 1), (3, 1) .... .. Then, the vertical / horizontal conversion processing unit 1603 stores in the image storage unit 1605 in the order of addresses as shown in FIG. The part that generates this address is the write address counter 2101.
Is. That is, at the time of writing, the addresses generated by the write address counter 2101 are 0000H, 01000H, 02000H, ..., FF.
000H, ... 00001H, 01001H, 02001H, ..., FF
001H, ... FFFFBH, FFFFCH, FFFFDH, FFFF
Vertical / horizontal conversion is realized by outputting as EH and FFFFFH, and the image data input in serial format is converted into raster format.

The multiplexer 2103 stores the count value of the write address counter 2101 at the time of writing and the count value of the read address counter 2102 at the time of reading in the image storage unit 1.
Output to the address 605.

In the vertical / horizontal conversion processing unit 1604 on the print side, 1
Conversion from the raster format to the serial format is performed by the reverse processing of 603. That is, the read address counter 2102 generates an address in the same manner as the write address counter described above, and by reading the image data, the image data stored in the raster format is read in the serial format.

As for the overall flow of the image, first, the scanner 1
The image read in 601 is subjected to scaling processing in the linear interpolation processing unit 1602, vertical / horizontal conversion is performed in the vertical / horizontal conversion processing unit 1603, and stored in the image storage unit 1605. When printing this, the vertical / horizontal conversion processing unit 1604 first performs vertical / horizontal conversion to perform linear interpolation processing unit 1.
In step 602, the scaling process performed on the reading side and the inverse scaling process are performed, and printing is performed by the printer 1606.

As described above, according to the present embodiment, there is an effect that the line buffer needs only the shuttle width by performing the scaling processing on the serial format image. Also, when performing scaling processing in shuttle units, the positional relationship between the first pre-conversion pixel and the first post-conversion pixel in the sub-scanning direction should be adjusted so that the positional relationship between the pre-conversion pixel and the post-conversion pixel does not shift between shuttles. The initial value of can be set, which has the effect of preventing image distortion at the joint between shuttles.

[0070]

[Other Embodiments] FIG. 20 is a view showing a second embodiment,
An encoding process 2301 and a decoding process unit 2302 are added to the configuration of the above-described first embodiment. With this configuration, in addition to the effect of the first embodiment, there is an effect that the image storage unit can be effectively used.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0072]

As described above, when the scaling processing is performed in shuttle units, it is possible to prevent the positional relationship between the pre-conversion pixel and the post-conversion pixel at the joint between the shuttles from being shifted, and to obtain a high-quality scaled image.

[0073]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a linear interpolation processing unit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between points before conversion and points after conversion in a linear interpolation method.

FIG. 3 is a timing chart of image signals handled by the apparatus according to the embodiment.

FIG. 4 is a block diagram showing a detailed configuration of a side scanning direction side calculation unit.

FIG. 5 is a diagram showing a positional relationship between pixels before and after conversion in a 64% reduction process.

FIG. 6 is a timing chart when 64% reduction processing is performed.

FIG. 7 is a diagram illustrating a positional relationship between pixels before and after conversion in a 128% enlargement process.

FIG. 8 is a timing chart when a 128% enlargement process is performed.

FIG. 9 is a diagram showing a positional relationship of pixels before and after conversion in the case of performing equal-magnification processing by a calculation method of reduction processing.

FIG. 10 is a diagram showing a positional relationship of pixels before and after conversion in the case of performing equal-magnification processing by a calculation method of enlargement processing.

FIG. 11 is a block diagram showing a relationship between a linear interpolation processing unit and an image supply source according to the embodiment.

FIG. 12 is a signal timing chart between an image supply source and a linear interpolation processing unit.

FIG. 13 is a block diagram of an image processing apparatus according to an embodiment of the present invention.

FIG. 14 is a diagram showing a positional relationship between pixels before and after conversion in the case where a joint process between shuttles is performed.

FIG. 15 is a diagram showing a positional relationship of pixels before and after conversion in the case of a conventional example in which a processing of seams between shuttles is not performed.

FIG. 16 is an explanatory diagram of a serial format.

FIG. 17 is a diagram showing memory mapping of a vertical / horizontal conversion processing unit.

FIG. 18 is a diagram showing a relationship between a storage address and data.

FIG. 19 is a block diagram of an aspect conversion processing unit.

FIG. 20 is a block diagram of an image processing apparatus according to a second embodiment of the present invention.

[Explanation of symbols]

 411 Initial value setting block 1601 Scanner 1602 Linear interpolation processing unit 1603, 1604 Vertical / horizontal conversion processing unit 1606 Printer

Claims (2)

[Claims] 1. An image processing apparatus for performing scaling processing on serial format image data, wherein scaling processing is performed on the image data for each scan based on a set scaling ratio, and conversion is performed. An image processing apparatus comprising: a scaling unit that determines a subsequent pixel; and a setting unit that sets the position of the converted pixel generated by the scaling process with respect to the pixel before conversion for each scan. 2. An image processing apparatus for performing scaling processing on serial format image data, wherein scaling processing is performed on the image data for each scan based on a set scaling ratio, and conversion is performed. It is provided with a scaling processing unit that determines a subsequent pixel using a linear interpolation method, and a setting unit that sets the position of the converted pixel generated by the scaling process with respect to the unconverted pixel for each scan. Image processing device.