JPH0521837A - Semiconductor functional element - Google Patents

Semiconductor functional element

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Publication number
JPH0521837A
JPH0521837A JP17685691A JP17685691A JPH0521837A JP H0521837 A JPH0521837 A JP H0521837A JP 17685691 A JP17685691 A JP 17685691A JP 17685691 A JP17685691 A JP 17685691A JP H0521837 A JPH0521837 A JP H0521837A
Authority
JP
Japan
Prior art keywords
light
substrate
light emitting
semiconductor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17685691A
Other languages
Japanese (ja)
Inventor
Yasuhiro Osawa
康宏 大沢
Shiro Sato
史朗 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Original Assignee
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Research Institute of General Electronics Co Ltd, Ricoh Co Ltd filed Critical Ricoh Research Institute of General Electronics Co Ltd
Priority to JP17685691A priority Critical patent/JPH0521837A/en
Publication of JPH0521837A publication Critical patent/JPH0521837A/en
Pending legal-status Critical Current

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  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Abstract

PURPOSE:To solve a problem of forming a step upon electrical and optical separations between elements to become a problem in a process of an optical functional element. CONSTITUTION:A structure in which a photoreceptor 70 is provided on a semiconductor substrate 58, a light emitting unit 62 is further disposed thereon, and an input light, an output light are input and output through a window 73 provided at the unit 62 side, is provided. Element isolation grooves 64 are formed in the same depth as the thickness of the unit 62 of a semiconductor optical functional element between individual elements 60 on the substrate 58, and a light shielding region 68 for shielding a light emitted in parallel with the substrate 58 from the light emitting unit of the functional element is formed on the side of the groove 64. A high resistance region 72 having an electrically high resistance, is formed in depth deeper than the thickness of the unit 70 of the functional element toward the inside of the substrate 58 from the surface in the bottom of the groove 64.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体による発光部と
受光部をモノリシックに集積化した光機能素子に関す
る。本発明は、二次元光情報処理用の基本素子となる光
演算素子に好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical functional element in which a semiconductor light emitting portion and a light receiving portion are monolithically integrated. INDUSTRIAL APPLICABILITY The present invention is suitable for an optical operation element which is a basic element for two-dimensional optical information processing.

【0002】[0002]

【従来の技術】従来より、集積型光機能素子として、図
7に示すようなヘテロ接合フォトトランジスタと発光ダ
イオードを集積したInGaAsP系の光メモリー素子
がある(Technical digest 20C3-2,Integrated Optics a
nd Optical-fiber Communication (IOOC) 1989,Kobe,Ja
pan)。この光メモリー素子は基板100側から、光を入
射させ、基板100上方へ出力光102を出射させる構
成のため、素子サイズに比べて基板100の厚さが厚
く、基板裏面からの入力光101が基板表面の各素子に
到達する時に発生する隣接素子間での入力光のクロスト
ークや、基板100のサポートの困難性、大規模集積化
における放熱の問題など、解決されるべき問題点が多
い。なお、図7は集積型光機能素子の断面図を示してい
るが、各層を判り易くするため、断面に斜線は引いてい
ない。
2. Description of the Related Art Conventionally, as an integrated optical functional device, there is an InGaAsP-based optical memory device integrated with a heterojunction phototransistor and a light emitting diode as shown in FIG. 7 (Technical digest 20C3-2, Integrated Optics a
nd Optical-fiber Communication (IOOC) 1989, Kobe, Ja
pan). This optical memory device has a structure in which light is incident from the substrate 100 side and output light 102 is emitted above the substrate 100. Therefore, the thickness of the substrate 100 is thicker than the device size, and the input light 101 from the back surface of the substrate is There are many problems to be solved, such as crosstalk of input light between adjacent elements that occurs when reaching each element on the substrate surface, difficulty in supporting the substrate 100, and heat dissipation problem in large-scale integration. Although FIG. 7 shows a cross-sectional view of the integrated optical functional device, hatching is not drawn in the cross-section for easy understanding of each layer.

【0003】[0003]

【発明が解決しようとする課題】また、公知ではない
が、図8に示すように、光集積型の半導体光機能素子と
して特願平2−73908に提案されているものがあ
る。この半導体機能素子は、n−GaAs基板22上に
n−Al0.4Ga0.6Asエミッタ層23,p−GaAs
ベース層24,n−GaAsコレクタ層25,n−Al
0.4Ga0.6Asn型クラッド層26,p−Al0.4Ga
0.6Asp型クラッド層27,p−GaAsキャップ層
28を順に積層した構造である。基板の裏にはn側オー
ミック電極21,キャップ層28の上にはp側オーミッ
ク電極29が形成されている。p−GaAsキャップ層
28は部分的に除かれて入出力光の窓46となってい
る。
Although not publicly known, there is an optical integrated semiconductor optical functional device proposed in Japanese Patent Application No. 2-73908, as shown in FIG. This semiconductor functional device comprises an n-Al 0.4 Ga 0.6 As emitter layer 23 and p-GaAs on an n-GaAs substrate 22.
Base layer 24, n-GaAs collector layer 25, n-Al
0.4 Ga 0.6 Asn-type cladding layer 26, p-Al 0.4 Ga
This is a structure in which a 0.6 Asp type clad layer 27 and a p-GaAs cap layer 28 are sequentially stacked. An n-side ohmic electrode 21 is formed on the back side of the substrate, and a p-side ohmic electrode 29 is formed on the cap layer 28. The p-GaAs cap layer 28 is partially removed to form a window 46 for input / output light.

【0004】この素子において発光ダイオード41は発
光部41として働き、ヘテロ接合フォトトランジスタ4
0は受光部40として働く。そして発光部41から受光
部40へ素子内部において正の光帰還があり、このこと
によって入力光強度と出力光強度の間に、図10に示す
ような光機能素子特有の、光微分利得81(一点鎖線で
示す),光双安定82(実線で示す),光スイッチ83
(破線で示す)といった非線形、又はヒステリシス特性
を持たせることができる。
In this element, the light emitting diode 41 functions as the light emitting portion 41, and the heterojunction phototransistor 4
0 functions as the light receiving unit 40. Then, there is positive optical feedback from the light emitting section 41 to the light receiving section 40 inside the element, which causes the optical differential gain 81 (specific to the optical functional element as shown in FIG. 10 between the input light intensity and the output light intensity. (Shown by a chain line), optical bistable 82 (shown by a solid line), optical switch 83
It may have a non-linear or hysteresis characteristic (shown by a broken line).

【0005】光機能素子の上記3つの特性が実現される
原理は、発光部41からの発光があることを除けばフォ
トサイリスタと全く同じであり、図9に示すように、電
流−電圧特性が入射光の強度によって変化し、光機能素
子に直列に接続した負荷抵抗42による負荷線85上の
みで素子の状態が決るので、負荷抵抗42やバイアス電
圧43を変化させることで3つの特性が実現されるので
ある。
The principle by which the above three characteristics of the optical functional element are realized is exactly the same as that of the photothyristor except that light is emitted from the light emitting section 41. As shown in FIG. It changes depending on the intensity of the incident light, and the state of the element is determined only on the load line 85 by the load resistor 42 connected in series to the optical function element. Therefore, three characteristics are realized by changing the load resistor 42 and the bias voltage 43. Is done.

【0006】例えば負荷抵抗42が大きい場合は、素子
に流れる電流が小さい値に制限されるので、入力光を0
から増加させていくと電流は単調に増加し、出力光も単
調に増加する(光微分利得特性)。負荷抵抗42が小さ
い場合は、入力光を0から増加させていくと電流−電圧
特性が入力光強度に応じて負荷線85を横切る点が現れ
る。この時の入力光を越えると、光機能素子はオン状態
に突然移行し出力光が急増する。一旦オン状態になる
と、素子は内部に流れる電流で発光し、その光でさらに
電流が流れる正帰還がかかりオン状態が保持され、その
後入力光を遮断しても、素子はオン状態を保つ(光スイ
ッチ特性)。抵抗値が両者の中間の場合は、入力光が増
加するうちに突然オン状態に移行するが、入力光を減少
させていく過程でオン状態を保持するための電流が不足
しているので、オンした光入力より小さな光入力の値で
再度オフ状態に突然移行する(光双安定特性)。なお、
図9において、符号88は入力光が無限大の時の特性曲
線、符号89は入力光がある場合の特性曲線、符号90
は入力光がない場合の特性曲線をそれぞれ示す。
For example, when the load resistance 42 is large, the current flowing through the element is limited to a small value, so that the input light is reduced to 0.
The current increases monotonically and the output light also monotonically increases (optical differential gain characteristic). When the load resistance 42 is small, when the input light is increased from 0, a point where the current-voltage characteristic crosses the load line 85 according to the intensity of the input light appears. When the input light at this time is exceeded, the optical functional element suddenly shifts to the ON state and the output light sharply increases. Once in the ON state, the element emits light with the current flowing inside, and the light causes positive feedback that causes a further current to flow to maintain the ON state. Switch characteristics). If the resistance value is in the middle of the two, it suddenly shifts to the ON state while the input light increases, but the current for maintaining the ON state is insufficient in the process of decreasing the input light, so The optical input suddenly shifts to the off state again with a smaller optical input value (optical bistable characteristic). In addition,
In FIG. 9, reference numeral 88 is a characteristic curve when the input light is infinite, reference numeral 89 is a characteristic curve when the input light is present, and reference numeral 90.
Shows the characteristic curves when there is no input light.

【0007】しかし上記の基板に垂直に集積した光機能
素子は、発光部と受光部が各々光を発生させ、吸収する
に必要な厚さより薄くは構成できないので、素子全体の
厚みが厚くなる。素子の積層方法としては、はじめに光
機能素子の各層を平らな基板上に、基板に平行に積層し
てからメサ形成によって各素子を分離していく方法が一
般的である。このため素子をメサ形成により電気的に分
離しようとすると、素子の厚みだけ基板に達するように
エッチングを行う必要があり、エッチングを行った部分
と行わない部分の段差が大きくなって電極の形成時に電
極の段切れが生じるなど、プロセスに問題が生じやす
い。
However, since the optical functional element vertically integrated on the substrate cannot be constructed to have a thickness smaller than that required for the light emitting portion and the light receiving portion to generate and absorb light, the overall thickness of the element increases. As a method for laminating the elements, a method is generally used in which each layer of the optical functional element is first laminated on a flat substrate in parallel with the substrate, and then each element is separated by mesa formation. For this reason, if an element is to be electrically separated by forming a mesa, it is necessary to perform etching so that the substrate reaches the thickness of the element, and the step between the etched portion and the non-etched portion becomes large. Process problems such as electrode breakage are likely to occur.

【0008】図11は電極の段切れを模式的に示した断
面図であり、半導体基板92上に受光部93と発光部9
4が積層された半導体機能素子端部に、発光部94の上
面から基板92の表面まで電極91が引き延ばされ、電
極91の段切れが生じた状態を示している。このよう
に、受光部93と発光部94の積層による厚さが大きく
なるに従って、電極の形成時に電極の段切れなどの問題
が生じる。SiO2などを用いて段差を埋め込むことも
可能ではあるが、完全な平坦化は難しい。
FIG. 11 is a cross-sectional view schematically showing the disconnection of electrodes. A light receiving portion 93 and a light emitting portion 9 are formed on a semiconductor substrate 92.
The electrode 91 is extended from the upper surface of the light emitting portion 94 to the surface of the substrate 92 at the end portion of the semiconductor functional element in which 4 is stacked, and the electrode 91 is disconnected. As described above, as the thickness of the light receiving portion 93 and the light emitting portion 94, which are laminated, increases, a problem such as electrode breakage occurs during electrode formation. Although it is possible to fill the step using SiO 2 or the like, complete flattening is difficult.

【0009】また、光機能素子は素子に入力する光に敏
感であるから、図12に示すように、素子がアレー状に
隣接して形成されていると、隣接素子96,97からの
洩れ光98によって素子がオン状態になるという誤動作
の原因となるので、素子間の基板に平行方向の光的分離
も必要となる。光的分離には上述のようなメサ形成後
に、光を遮断する層(例えば電極)をメサ間の溝に沿っ
て積層することがよく行われているので、電気的分離と
同様に電極の段切れが発生すると、光的分離不良の問題
が発生しやすい。ゆえに、光機能素子のプロセスは、隣
接素子間を電気的かつ光的に確実に分離し、プロセス中
に形成される段差を、可能な限り小さくするようなもの
でなくてはならない。本発明の目的は、光機能素子のプ
ロセス上問題となる、素子間の電気的かつ光的分離に伴
う段差形成の問題を解決することにある。
Further, since the optical functional element is sensitive to the light input to the element, if the elements are formed adjacent to each other in an array as shown in FIG. 12, the leaked light from the adjacent elements 96 and 97 is generated. Since 98 causes an erroneous operation in which the elements are turned on, optical separation in the direction parallel to the substrate between the elements is also necessary. For optical isolation, it is often practiced to stack a layer that blocks light (eg, electrodes) along the grooves between mesas after the formation of mesas as described above. When the breakage occurs, a problem of poor optical separation easily occurs. Therefore, the process of the optical functional device must ensure that the adjacent devices are electrically and optically separated from each other, and the step formed during the process is made as small as possible. An object of the present invention is to solve the problem of forming a step due to electrical and optical isolation between elements, which is a problem in the process of an optical functional element.

【0010】[0010]

【課題を解決するための手段】本発明の基本的構成の断
面図を図1に示す。半導体基板58上に受光部70があ
り、更にその上に発光部62があり、発光部62上側に
設けられた窓部73より入力光と出力光が入出力する構
造の半導体光機能素子で、光機能素子の発光部62を構
成する半導体材料の禁制帯巾は入力光の主ピークエネル
ギーより大きく、光機能素子の発光部70を構成する半
導体材料の禁制帯巾は入力光の主ピークエネルギーに等
しいかそれより小さく、発光部62から発生した出力光
の一部が受光部70に帰還し、受光部70で吸収され光
帰還効果を持つように構成されている。この効果によっ
て入力光と出力光の間に非線形な応答を有する。
FIG. 1 is a sectional view showing the basic structure of the present invention. A semiconductor optical function element having a structure in which a light receiving section 70 is provided on a semiconductor substrate 58, a light emitting section 62 is further provided thereon, and input light and output light are input and output through a window section 73 provided above the light emitting section 62, The forbidden band width of the semiconductor material forming the light emitting portion 62 of the optical functional element is larger than the main peak energy of the input light, and the forbidden band width of the semiconductor material forming the light emitting portion 70 of the optical functional element is the main peak energy of the input light. A part of the output light generated from the light emitting portion 62 is equal to or smaller than that and is returned to the light receiving portion 70, and is absorbed by the light receiving portion 70 to have an optical feedback effect. This effect has a non-linear response between the input light and the output light.

【0011】また、半導体基板58上で1次元または2
次元アレー状に並んだ半導体光機能素子の個別の素子6
0の間に、半導体光機能素子の発光部62の厚さと同じ
深さに素子分離用溝64が形成されていて、その素子分
離用溝64の側面に上記半導体光機能素子の発光部66
から基板58と平行方向へ発する光を遮光する遮光領域
68が形成されていて、素子分離用溝64の底にその表
面から半導体基板58の内側の方向へ、受光部70の厚
さ以上の深さまで電気的に高抵抗な高抵抗領域72が形
成されていることを特徴としている。
In addition, one-dimensional or two-dimensional on the semiconductor substrate 58.
Individual elements 6 of semiconductor optical functional elements arranged in a three-dimensional array
0, an element isolation groove 64 is formed at the same depth as the thickness of the light emitting portion 62 of the semiconductor optical functional element, and the light emitting portion 66 of the semiconductor optical functional element is formed on the side surface of the element isolation groove 64.
A light-blocking region 68 for blocking light emitted from the substrate 58 in a direction parallel to the substrate 58 is formed, and a depth equal to or larger than the thickness of the light-receiving portion 70 is formed in the bottom of the element isolation trench 64 from its surface toward the inside of the semiconductor substrate 58. The feature is that a high resistance region 72 having a high resistance is formed.

【0012】個別の光機能素子の電気的分離に関して
は、発光部62の厚さ以上に形成されたメサ部分と、形
成したメサ間の底部に受光部70の厚さ以上に形成され
た高抵抗領域72で行っていることが特徴である。ま
た、個別の光機能素子の光的分離に関しては、発光部6
2の厚さ以上に形成されたメサ部分の側面に光を遮光す
る遮光領域68を形成して、半導体光機能素子の発光部
62から基板58と平行方向へ発した光が、隣接する光
機能素子の受光部70で吸収されないようにしているこ
とが特徴である。
Regarding the electrical isolation of the individual optical function elements, a mesa portion formed more than the thickness of the light emitting portion 62 and a high resistance formed more than the thickness of the light receiving portion 70 at the bottom between the formed mesas. The feature is that it is performed in the area 72. Also, regarding the optical separation of the individual optical function elements, the light emitting unit 6
A light-shielding region 68 for shielding light is formed on the side surface of the mesa portion formed to have a thickness of 2 or more, so that light emitted from the light emitting portion 62 of the semiconductor optical function element in the direction parallel to the substrate 58 is adjacent to the optical function. The feature is that the light receiving portion 70 of the element is not absorbed.

【0013】[0013]

【作用】本発明では、素子間の電気的分離と光的分離の
条件を満たしながら、素子分離用溝64の深さが発光部
62の厚さとなり、単純に発光部62と受光部70の厚
さをあわせた深さまで分離溝を形成するより段差が小さ
くなり、光機能素子の上部と側面とに沿って形成される
電極や絶縁膜等の段切れ等の問題が軽減される。
In the present invention, the depth of the element isolation groove 64 becomes the thickness of the light emitting portion 62 while satisfying the conditions of electrical isolation and optical isolation between elements, and the light emitting portion 62 and the light receiving portion 70 are simply combined. The step is smaller than the case where the separation groove is formed to a depth that matches the thickness, and problems such as disconnection of electrodes and insulating films formed along the upper and side surfaces of the optical functional element are alleviated.

【0014】[0014]

【実施例】以下、本発明の実施例を説明する。図2は本
発明の一実施例を示す断面図である。この実施例に係る
半導体機能素子は、n−GaAs基板119上にn−A
0.4Ga0.6Asエミッタ層118,p−GaAsベー
ス層117,n−GaAsコレクタ層116,n−Al
0.4Ga0.6Asn型クラッド層115,無添加Al0.2
Ga0.8As活性層114,p−Al0.4Ga0.6Asp
型クラッド層113,p−GaAsキャップ層112を
順に積層された構成となっている。n−Al0.4Ga0.6
Asn型クラッド層115,無添加Al0.2Ga0.8As
活性層114,p−Al0.4Ga0.6Asp型クラッド層
113で発光ダイオード(発光部)を構成し、この発光
ダイオード130は発光効率を向上させるためにダブル
ヘテロ接合構造をとっている。
EXAMPLES Examples of the present invention will be described below. FIG. 2 is a sectional view showing an embodiment of the present invention. The semiconductor functional element according to this embodiment has an n-A substrate on an n-GaAs substrate 119.
l 0.4 Ga 0.6 As emitter layer 118, p-GaAs base layer 117, n-GaAs collector layer 116, n-Al
0.4 Ga 0.6 Asn-type cladding layer 115, undoped Al 0.2
Ga 0.8 As active layer 114, p-Al 0.4 Ga 0.6 Asp
The mold clad layer 113 and the p-GaAs cap layer 112 are laminated in this order. n-Al 0.4 Ga 0.6
Asn-type cladding layer 115, undoped Al 0.2 Ga 0.8 As
The active layer 114 and the p-Al 0.4 Ga 0.6 Asp clad layer 113 constitute a light emitting diode (light emitting portion), and the light emitting diode 130 has a double heterojunction structure in order to improve the light emission efficiency.

【0015】また、n−Al0.4Ga0.6Asエミッタ層
118,p−GaAsベース層117,n−GaAsコ
レクタ層116で受光部を構成し、この受光部132は
エミッタからベースへの電子の注入効率を上げるため、
禁制帯巾の大きいエミッタを用いたヘテロ接合フォトフ
ォランジスタで構成されている。素子の上部には、p−
GaAsキャップ層112をエッチングして、p−Al
0.4Ga0.6Asp型クラッド層113まで達する入射窓
128が形成され、入射光及び出射光が出入りできるよ
うに構成されている。n−GaAs基板119裏面には
n型オーミック共通電極120が形成され、前記p型オ
ーミック上部電極110との間に所定の電圧が印加され
る。
Further, the n-Al 0.4 Ga 0.6 As emitter layer 118, the p-GaAs base layer 117, and the n-GaAs collector layer 116 constitute a light-receiving portion, and the light-receiving portion 132 has an electron injection efficiency from the emitter to the base. To raise
It is composed of a heterojunction photophoresistor using an emitter with a large forbidden band. At the top of the device, p-
The GaAs cap layer 112 is etched to form p-Al.
An incident window 128 reaching the 0.4 Ga 0.6 Asp type clad layer 113 is formed so that incident light and outgoing light can enter and exit. An n-type ohmic common electrode 120 is formed on the back surface of the n-GaAs substrate 119, and a predetermined voltage is applied between the n-type ohmic common electrode 120 and the p-type ohmic upper electrode 110.

【0016】個別の素子の間には発光ダイオード130
の厚さと同じ深さ、n−GaAsコレクタ層116の表
面位置のところまで達する素子分離用溝134が形成さ
れている。この素子分離用溝134は個別の素子が基板
上に複数個配列されている場合には、素子を囲む形に形
成される。
A light emitting diode 130 is provided between the individual devices.
An element isolation trench 134 reaching the surface position of the n-GaAs collector layer 116 is formed at the same depth as the thickness of the. The element separating groove 134 is formed so as to surround the element when a plurality of individual elements are arranged on the substrate.

【0017】また、p−GaAsキャップ層112上
と、発光ダイオード130の側面(素子分離用溝134
の側面でもある)には、SiO2絶縁層111が形成さ
れ、さらにその上に形成されたp型オーミック上部電極
110が光を遮光する遮光領域を形成している。また、
素子分離用溝134の底にその表面からn−GaAs基
板119の内側の方向へ、受光部132の厚さ以上の深
さまで電気的に高抵抗な高抵抗領域121が形成されて
いる。
Further, on the p-GaAs cap layer 112 and on the side surface of the light emitting diode 130 (element isolation groove 134).
SiO 2 insulating layer 111 is formed on a side surface of the p-type ohmic upper electrode 110, and a p-type ohmic upper electrode 110 formed on the SiO 2 insulating layer 111 forms a light-blocking region that blocks light. Also,
A high resistance region 121 having a high electrical resistance is formed in the bottom of the element isolation groove 134 from the surface thereof toward the inside of the n-GaAs substrate 119 to a depth equal to or larger than the thickness of the light receiving portion 132.

【0018】次に本実施例の作製方法の一例を説明す
る。まず、図3に示すように、n−GaAs基板119
上にn−Al0.4Ga0.6Asエミッタ層118(厚さ
0.2μm,キャリア濃度1×1017cm~3),p−G
aAsベース層117(厚さ0.1μm,キャリア濃度
1×1018cm~3),n−GaAsコレクタ層116
(厚さ1μm,キャリア濃度1×1015cm~3)、n−
Al0.4Ga0.6Asn型クラッド層115(厚さ1μ
m,キャリア濃度1×1018cm~3),無添加Al0.2
Ga0.8As活性層114(厚さ0.1μm,キャリア
濃度1×1015cm~3),p−Al0.4Ga0.6Asp型
クラッド層113(厚さ1μm,キャリア濃度1×10
18cm~3),p−GaAsキャップ層112(厚さ0.
2μm,キャリア濃度2×1018cm~3)を順に有機金
属気相成長法を用いて積層した。
Next, an example of the manufacturing method of this embodiment will be described. First, as shown in FIG. 3, an n-GaAs substrate 119 is formed.
N-Al 0.4 Ga 0.6 As emitter layer 118 (thickness 0.2 μm, carrier concentration 1 × 10 17 cm to 3 ), p-G
aAs base layer 117 (thickness 0.1 μm, carrier concentration 1 × 10 18 cm to 3 ), n-GaAs collector layer 116
(Thickness 1 μm, carrier concentration 1 × 10 15 cm to 3 ), n−
Al 0.4 Ga 0.6 Asn-type cladding layer 115 (thickness 1 μm
m, carrier concentration 1 × 10 18 cm 3 ), undoped Al 0.2
Ga 0.8 As active layer 114 (thickness 0.1 μm, carrier concentration 1 × 10 15 cm 3 ), p-Al 0.4 Ga 0.6 Asp type cladding layer 113 (thickness 1 μm, carrier concentration 1 × 10 5
18 cm ~ 3 ), p-GaAs cap layer 112 (thickness: 0.
2 μm and a carrier concentration of 2 × 10 18 cm 3 ) were sequentially stacked by using the metal organic chemical vapor deposition method.

【0019】続いて、図4に示すように、フォトリソグ
ラフィー技術により作製したエッチングマスクを用い
て、NH4OH:H22=4:1,20℃,40秒(深
さ2.5μm)という条件で発光部の分離のためのエッ
チングを行った。このエッチングにより、素子分離用溝
134が形成されることとなる。
Subsequently, as shown in FIG. 4, NH 4 OH: H 2 O 2 = 4: 1, 20 ° C., 40 seconds (depth: 2.5 μm) using an etching mask produced by photolithography technique. Under the conditions, etching for separating the light emitting portion was performed. By this etching, the element isolation groove 134 is formed.

【0020】この上に、図5に示すように、イオン打ち
込みのマスクと素子の絶縁およびパッシベーションを兼
ねたSiO2絶縁膜111をプラズマCVD法で300
nm堆積する。フォトリソグラフィーによるエッチング
マスクを用いて、素子分離用溝134の底だけSiO2
絶縁膜111をエッチングし、イオン打ち込みのマスク
とした。イオン打ち込みの条件は、イオン種としてはプ
ロトンを用い、打ち込みのエネルギーレベルは140k
eV,ドーズ量は1014cm~2とした。このイオン打ち
込みにより、高抵抗領域121が形成されることとな
る。なお、イオン打ち込みの条件は、ベース層の深さ
(溝の底から1μm)の所にプロトンの分布ピークが位
置するようにエネルギーレベルを設定し、ベース層のキ
ャリア濃度1×1018cm~3を補償し、高抵抗領域12
1を形成できるドーズ量を選んだ。
On this, as shown in FIG. 5, a SiO 2 insulating film 111, which also serves as an ion implantation mask and element insulation and passivation, is formed by plasma CVD to 300
nm deposition. By using an etching mask by photolithography, only the bottom of the isolation trench 134 is SiO 2
The insulating film 111 was etched and used as a mask for ion implantation. The ion implantation conditions are that protons are used as the ion species and the implantation energy level is 140 k.
The eV and dose amount were set to 10 14 cm to 2 . The high resistance region 121 is formed by this ion implantation. The ion implantation conditions were set so that the proton distribution peak was located at the depth of the base layer (1 μm from the bottom of the groove), and the carrier concentration of the base layer was 1 × 10 18 cm ~ 3. To compensate for the high resistance region 12
The dose amount that can form 1 was selected.

【0021】次いで、図6に示すように、フォトリソグ
ラフィーを用いて再度SiO2絶縁膜111にパターン
を形成し、p−GaAsキャップ層112の上の電極1
10と接触させるための窓を形成する。エッチングには
HF:NH4F=1:5,20℃,60秒の条件を用い
た。続いてエッチングマスクを用いて、NH4OH:H2
2=1:20,20℃,5秒という条件のもとでp−
GaAsキャップ層112を選択的にエッチングして、
光の入出力窓128を形成した。次にp側電極Cr/A
uZn/Au(300nm)をp−GaAsキャップ層
112とSiO 2絶縁膜111の上に蒸着し、リフトオ
フ法により電極のパターンを形成してp型オーミック上
部電極110を形成する。
Next, as shown in FIG. 6, photolithography
Using Raffy again SiO2Pattern on insulating film 111
To form an electrode 1 on the p-GaAs cap layer 112.
A window for contacting with 10 is formed. For etching
HF: NHFourF = 1: 5, 20 ° C., 60 seconds are used
It was Then, using an etching mask, NHFourOH: H2
O2= 1: 20, 20 ° C, p-under the condition of 5 seconds
By selectively etching the GaAs cap layer 112,
The light input / output window 128 is formed. Next, the p-side electrode Cr / A
uZn / Au (300 nm) is a p-GaAs cap layer
112 and SiO 2Evaporate on the insulating film 111 and lift
On the p-type ohmic by forming the electrode pattern by the
The partial electrode 110 is formed.

【0022】最後にn−GaAs基板119の裏面をア
ルミナの粉末を用いて100μmの厚さにラッピングし
て、基板裏面にn側電極AuGe/Ni/Auを100
nm蒸着し、n型オーミック共通電極120を形成し、
製造プロセスを終了した。なお、p型オーミック上部電
極110は発光部130の光を横方向に閉じ込める働き
もしている。素子の並びの上に形成される段差は2.5
μmなので、p型オーミック上部電極110の形成には
何の問題もなく素子を作製でき、図9及び図10に示し
た、従来通りの光機能素子特性を得ることができた。
Finally, the back surface of the n-GaAs substrate 119 was lapped with alumina powder to a thickness of 100 μm, and the n-side electrode AuGe / Ni / Au of 100 μm was laid on the back surface of the substrate.
nm vapor deposition to form the n-type ohmic common electrode 120,
Finished the manufacturing process. The p-type ohmic upper electrode 110 also has a function of horizontally confining the light of the light emitting unit 130. The step formed on the array of elements is 2.5
Since it is μm, the device can be manufactured without any problem in forming the p-type ohmic upper electrode 110, and the conventional optical functional device characteristics shown in FIGS. 9 and 10 can be obtained.

【0023】本発明は前記実施例に限らず、各種の変形
が可能である。例えば、上記の実施例で用いられた材料
系以外、例えばInP等の半導体材料や他の組成を用い
ていても適用可能である。1次元または2次元のアレー
状に素子が並んでいるときなど、電気的かつ光的に素子
相互に干渉しやすい場合、特に有効である。上記の実施
例で、半導体層を有機金属気相成長法を用いて作製した
が、液相成長法や分子線ビーム成長法等の、薄膜形成が
できる他の手段で成長した場合にも本発明の構造を適用
できる。さらに、上記の実施例の作製方法はその一例に
すぎず、半導体作成に用いられる各種の製法プロセスを
用いて作成することができることは明らかである。
The present invention is not limited to the above embodiment, but various modifications can be made. For example, other than the material system used in the above-mentioned embodiment, a semiconductor material such as InP or another composition may be used. This is particularly effective when the elements are arranged in a one-dimensional or two-dimensional array and the elements are likely to electrically and optically interfere with each other. Although the semiconductor layer is formed by using the metal organic chemical vapor deposition method in the above-mentioned embodiment, the present invention is also applicable to the case where the semiconductor layer is grown by other means capable of forming a thin film such as liquid phase growth method and molecular beam growth method. The structure of can be applied. Further, it is obvious that the manufacturing method of the above-mentioned embodiment is only one example, and that it can be manufactured by using various manufacturing processes used for manufacturing a semiconductor.

【0024】[0024]

【発明の効果】請求項1記載の発明によれば、前記発光
部の厚さと同じ深さの素子分離用溝を設け、その素子分
離用溝の側面に遮光領域を形成し、かつ素子分離用溝の
底にその表面から半導体基板の内側の方向へ、受光部の
厚さ以上の深さまで電気的に高抵抗な高抵抗領域を設け
ることにより、機能素子本来の特性を損なうことなく、
光機能素子を作製するにあたり問題となっていた、素子
の電気的かつ光的分離溝による電極の段切れなどプロセ
スの問題を解決することができる。
According to the first aspect of the invention, an element isolation groove having the same depth as the thickness of the light emitting portion is provided, and a light shielding region is formed on the side surface of the element isolation groove, and the element isolation groove is formed. In the bottom of the groove, from the surface to the inside of the semiconductor substrate, by providing a high resistance region of high electrical resistance to a depth equal to or greater than the thickness of the light receiving portion, without impairing the original characteristics of the functional element,
It is possible to solve process problems such as disconnection of electrodes due to electrical and optical isolation grooves of the device, which has been a problem in manufacturing the optical functional device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体機能素子の基本的構成を示す断
面図である。
FIG. 1 is a sectional view showing a basic configuration of a semiconductor functional device of the present invention.

【図2】本発明の半導体機能素子の一実施例を示す断面
図である。
FIG. 2 is a sectional view showing an embodiment of a semiconductor functional device of the present invention.

【図3】本実施例の製造プロセスを示す断面図である。FIG. 3 is a cross-sectional view showing the manufacturing process of the present embodiment.

【図4】本実施例の製造プロセスを示す断面図である。FIG. 4 is a cross-sectional view showing the manufacturing process of the present embodiment.

【図5】本実施例の製造プロセスを示す断面図である。FIG. 5 is a cross-sectional view showing the manufacturing process of the present embodiment.

【図6】本実施例の製造プロセスを示す断面図である。FIG. 6 is a cross-sectional view showing the manufacturing process of the present embodiment.

【図7】従来の半導体機能素子の断面図である。FIG. 7 is a cross-sectional view of a conventional semiconductor functional element.

【図8】既に提案済の公知でない半導体機能素子の断面
図である。
FIG. 8 is a cross-sectional view of a semiconductor functional device which has not been known and has already been proposed.

【図9】半導体機能素子の電圧−電流特性を示す図であ
る。
FIG. 9 is a diagram showing voltage-current characteristics of a semiconductor functional element.

【図10】半導体機能素子の3つの特性を説明するため
の図である。
FIG. 10 is a diagram for explaining three characteristics of the semiconductor functional element.

【図11】電極の段切れを説明するための断面図であ
る。
FIG. 11 is a cross-sectional view for explaining disconnection of electrodes.

【図12】個別の素子間の光的クロストークを説明する
ための断面図である。
FIG. 12 is a cross-sectional view for explaining optical crosstalk between individual elements.

【符号の説明】[Explanation of symbols]

58,119 半導体基板 70,132 受光部 62,130 発光部 73,128 窓部 64,134 素子分離用溝 68 遮光領域 72,121 高抵抗領域 Reference numeral 58,119 Semiconductor substrate 70,132 Light receiving portion 62,130 Light emitting portion 73,128 Window portion 64,134 Element separating groove 68 Light shielding area 72,121 High resistance area

Claims (1)

【特許請求の範囲】 【請求項1】半導体基板上に受光部があり、さらにその
上に発光部があり、該発光部側に設けられた窓部より入
力光および出力光が入出力する構成であり、前記発光部
を構成する半導体材料の禁制帯巾が入力光の主ピークエ
ネルギーより大きいものであり、前記受光部を構成する
半導体材料の禁制帯巾は入力光の主ピークエネルギーに
等しいかそれより小さく、前記発光部から発生した出力
光の一部は前記受光部に帰還し、前記受光部で吸収され
る光帰還効果による入力光強度と出力光強度の間に非線
形な応答を有することを特徴とする半導体光機能素子で
あって、 前記基板上で1次元または2次元アレー状に並んだ前記
半導体光機能素子の個別の素子の間に、少なくとも前記
発光部の厚さと同じ深さに素子分離用溝が形成されてい
て、その素子分離用溝の側面に前記発光部から基板と平
行方向へ発する光を遮光する遮光領域が形成されてい
て、前記素子分離用溝の底にその表面から前記半導体基
板の内側の方向へ、前記受光部の厚さ以上の深さまで電
気的に高抵抗な高抵抗領域が形成されていることを特徴
とする半導体光機能素子。
Claim: What is claimed is: 1. A structure in which a light receiving portion is provided on a semiconductor substrate, a light emitting portion is further provided thereon, and input light and output light are input and output through a window portion provided on the light emitting portion side. And the forbidden band width of the semiconductor material forming the light emitting portion is larger than the main peak energy of the input light, and the forbidden band width of the semiconductor material forming the light receiving portion is equal to the main peak energy of the input light. A part of the output light generated from the light emitting unit, which is smaller than that, is returned to the light receiving unit, and has a non-linear response between the input light intensity and the output light intensity due to the optical feedback effect absorbed by the light receiving unit. A semiconductor optical functional element characterized by comprising: a semiconductor optical functional element arranged in a one-dimensional or two-dimensional array on the substrate; Element isolation groove And a light-shielding region for shielding light emitted from the light emitting portion in a direction parallel to the substrate is formed on a side surface of the element isolation groove, and the semiconductor isolation substrate is formed on the bottom of the element isolation groove from its surface. A semiconductor optical functional device, characterized in that a high resistance region having a high resistance is formed inwardly to a depth equal to or larger than the thickness of the light receiving portion.
JP17685691A 1991-07-17 1991-07-17 Semiconductor functional element Pending JPH0521837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17685691A JPH0521837A (en) 1991-07-17 1991-07-17 Semiconductor functional element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17685691A JPH0521837A (en) 1991-07-17 1991-07-17 Semiconductor functional element

Publications (1)

Publication Number Publication Date
JPH0521837A true JPH0521837A (en) 1993-01-29

Family

ID=16021023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17685691A Pending JPH0521837A (en) 1991-07-17 1991-07-17 Semiconductor functional element

Country Status (1)

Country Link
JP (1) JPH0521837A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018147141A1 (en) * 2017-02-07 2018-08-16 キヤノン株式会社 Imaging device and imaging system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018147141A1 (en) * 2017-02-07 2018-08-16 キヤノン株式会社 Imaging device and imaging system
JP2018129359A (en) * 2017-02-07 2018-08-16 キヤノン株式会社 Imaging apparatus and imaging system
US10861897B2 (en) 2017-02-07 2020-12-08 Canon Kabushiki Kaisha Imaging device and imaging system

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