JPH05218321A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To reduce a resistance by the use of embedded tungsten in order to ground a substrate by forming the rear surface of a high-frequency operation high-output field effect transistor, in the case of a lateral type electric field structure, into a source. CONSTITUTION:A tungsten-embedded region 10 is formed through an epitaxial layer 2 in order to connect a source electrode 9 to a silicon substrate 1. This renders the silicon substrate 1 free of a raised area, and hence makes it possible to withstand a high voltage. Also, the area of an element can be reduced because of the low resistance of tungsten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, and more particularly to a horizontal field effect transistor and a vertical field effect transistor, a high frequency high power individual semiconductor device and a high power integrated circuit semiconductor device.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor device is composed of a source 5, a drain 3, a low concentration N type diffusion layer 4 and a gate 7, as shown in FIG. In the case of grounding the source of the lateral field effect transistor, in order to reduce the source inductance component, the low-concentration epitaxial layer 2 is highly concentrated and grown on the silicon substrate 1, and the source electrode 9 is highly concentrated on the high-concentration silicon substrate. Connection is made via the diffusion layer 15.
Therefore, it has a structure in which the silicon substrate 1 is used as a source electrode.

Next, FIG. 5 shows the structure of an individual semiconductor element of a vertical field effect transistor. In FIG. 2, 14
Is an epitaxial layer, 5 is a source, 12 is a base region,
Reference numeral 7 is a gate, and 9 is a source electrode. In the vertical field effect transistor, the silicon substrate 13 serves as a drain terminal,
The power supply terminal is connected to the silicon substrate 13.
Further, as shown in FIG. 6, the buried layer 11 is formed by the diffusion layer.
It has a structure to connect to.

[0004]

In this conventional semiconductor device, in the case of the lateral field effect transistor, the source electrode 9 is grounded by the high-concentration diffusion layer 15 to the silicon substrate 1 which is the back surface of the semiconductor device. Therefore, when a parasitic resistance component exists in the source electrode 9 serving as the ground terminal and a large resistance component is parasitic in the ground terminal, a voltage drop occurs at the source terminal serving as the ground terminal and the amplification characteristic is significantly deteriorated. Therefore, when the source is grounded to the back silicon substrate by the high-concentration diffusion layer 15, it is necessary to increase the cross-sectional area of the diffusion layer 15 to reduce the resistance. However, as shown in the plot A of FIG. 3, when the high-concentration diffusion layer 15 is grounded to the rear surface of the high-concentration silicon substrate, when the high-concentration silicon substrate 1 is boron, the P-type silicon substrate 1 rises up to a conventional level. In contrast to the concentration distribution B of the epitaxial layer (concentration distribution before diffusion), there was a problem that the concentration was increased C (concentration distribution of the raised epitaxial layer), the breakdown voltage was lowered, and the threshold value of the transistor was increased.

In the case of a vertical field effect transistor,
Similarly, when the drain electrode 8 is formed on the surface of the semiconductor device, the parasitic resistance decreases the value of the non-saturation current such as the threshold current and increases the on-resistance. Therefore, like the lateral field effect transistor, it is necessary to increase the cross-sectional area of the high-concentration diffusion layer 15 and reduce the resistance. For this reason, the element area of the semiconductor device increases, and there is a problem in miniaturization and integration of the element.

[0006]

The first gist of the present invention is to provide an epitaxial layer grown on a semiconductor substrate, source and drain regions formed on the surface of the epitaxial layer, a gate electrode, and a source region. In a lateral field-effect transistor having a source electrode and a drain electrode respectively connected to the drain region and the drain region, by forming a contact region penetrating the epitaxial layer and connecting the source electrode and the semiconductor substrate with a refractory metal. is there.

A second gist of the present invention is to connect an epitaxial layer grown on a semiconductor substrate, a source region and a drain region formed on the surface of the epitaxial layer, a gate electrode, and a source region and a drain region, respectively. In a method for manufacturing a lateral field effect transistor having a source electrode and a drain electrode, the step of forming a contact region trench penetrating the epitaxial layer and connecting the source electrode and the semiconductor substrate, and the trench And a step of filling with melting point metal by chemical vapor deposition.

A third aspect of the present invention is that an epitaxial layer grown on a semiconductor substrate and functioning as a drain region, a buried layer provided at an interface between the semiconductor substrate and the epitaxial layer, and a surface portion of the epitaxial layer. In a vertical field effect transistor including a provided base region and a source region provided on the surface of the base region, a refractory metal is used as a contact region that penetrates the epitaxial layer and connects the buried layer and the drain electrode. It was formed in.

[0009]

Even if the contact region is formed of a refractory metal, the impurity concentration of the epitaxial layer does not change, and the refractory metal has a low resistance, so that the cross-sectional area is small and the field effect transistor is occupied on the semiconductor substrate. The area can be reduced.

[0010]

The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a sectional view of an N-channel lateral field effect transistor according to a first embodiment of the present invention. A low-concentration P-type epitaxial layer 2 is grown on a high-concentration P-type silicon substrate 1. A high-concentration N-type drain 3, a low-concentration N-type diffusion layer 4, and a high-concentration N-type source 5 are formed on the P-type epitaxial layer 2, and a silicon oxide film 6 for element isolation and parasitic capacitance reduction and gate insulation is formed. , A gate electrode 7, a drain electrode 8 and a source electrode 9. Here, in order to connect the source electrode 9 to the high-concentration silicon substrate 1 on the back surface, a trench groove is formed in the epitaxial layer 2 and a refractory metal 10 such as tungsten formed by chemical vapor deposition is embedded therein.

Since the refractory metal 10 is lower than the resistivity of silicon in a high concentration state by about three orders of magnitude, the cross-sectional area can be remarkably reduced, and since the high-concentration layer of the substrate does not rise, the concentration of the epitaxial layer 2 is high. However, the drain breakdown voltage is maintained without increasing the concentration. Therefore, the power supply voltage can be increased.

FIG. 2 is a sectional view showing a second embodiment of the present invention. A buried layer 11 is formed between the silicon substrate 13 and the epitaxial layer 14 for integration of the vertical field effect transistor. A base region 12 for forming a vertical field effect transistor is formed around the source region 5, and a trench groove opening to the buried layer 11 is formed in the epitaxial layer 14, and tungsten is formed therein by a chemical vapor deposition method. A refractory metal 10 such as is embedded to reduce the parasitic resistance of the drain.

[0013]

In the case of the lateral field effect transistor, the high temperature heat treatment in the case of the vapor phase growth method is not applied and it is processed at a low temperature, so that the high-concentration silicon substrate does not rise and the high breakdown voltage and the low breakdown voltage are lowered. A threshold value transistor can be realized. Further, both the lateral and vertical field effect transistors have the effect of significantly reducing the cross-sectional area of the connection region connected to the substrate and the buried layer as compared with the high-concentration diffusion layer.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment.

FIG. 2 is a sectional view showing a second embodiment.

FIG. 3 is a concentration distribution diagram in the case where a high concentration diffusion layer of a lateral field effect transistor is formed.

FIG. 4 is a sectional view of a conventional example.

FIG. 5 is a sectional view of a conventional example.

FIG. 6 is a sectional view of a conventional example.

[Explanation of symbols]

 1 P-type high-concentration silicon substrate 2 P-type epitaxial layer 3 Drain 4 Low-concentration N-type diffusion layer 5 Source 6 Silicon oxide film 7 Gate electrode 8 Drain electrode 9 Source electrode 10 Tungsten 11 Buried layer 12 Base region 13 Silicon substrate 14 Epitaxial layer 15 High concentration diffusion layer

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (3)

[Claims] 1. An epitaxial layer grown on a semiconductor substrate, a source region and a drain region formed on the surface of the epitaxial layer, a gate electrode, and a source electrode and a drain electrode connected to the source region and the drain region, respectively. A lateral field-effect transistor comprising: a contact region penetrating an epitaxial layer and connecting a source electrode and a semiconductor substrate with a refractory metal. 2. An epitaxial layer grown on a semiconductor substrate, a source region and a drain region formed on the surface of the epitaxial layer, a gate electrode, and a source electrode and a drain electrode connected to the source region and the drain region, respectively. In a method of manufacturing a lateral field effect transistor including: a step of forming a trench for a connection region that penetrates an epitaxial layer and connects a source electrode and a semiconductor substrate; and chemical vapor deposition of a refractory metal in the trench. A method of manufacturing a lateral field effect transistor, comprising: 3. An epitaxial layer grown on a semiconductor substrate and functioning as a drain region, a buried layer provided at an interface between the semiconductor substrate and the epitaxial layer, and a base region provided on a surface portion of the epitaxial layer. In a vertical field effect transistor having a source region provided on the surface of a base region, a contact region penetrating an epitaxial layer and connecting a buried layer and a drain electrode is formed of a refractory metal. Vertical type field effect transistor.