JPH0521828A - Light input type semiconductor device - Google Patents

Abstract

PURPOSE:To offer a light input type semiconductor device having an electrode of low resistance and good photoelectric conversion efficiency. CONSTITUTION:An N<-> epitaxial film 3 is provided on the top surface of an N<+> drain substrate 1, a P-well region 5 is provided on its surface layer part and an aluminium-made source electrode 13 is provided in the P-well region 5 and on a part of an N<+> source region 7. A drain electrode 15 is provided on the lower part surface of the N<+> drain substrate 1. The N<+> source regions 7 are provided on the surface layer parts near both ends of the P-well regions 5a and a gate electrode 11 is provided on the region between two adjacent P-well regions 5 through a gate insulating film 9. A photovoltaic element 19 is provided on the gate electrode 11 through an insulating film 17. The photovoltaic elements 19 are individually formed on the regions not overlapping the surface electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical input type semiconductor device which performs a switching operation by an optical signal.

[0002]

2. Description of the Related Art Conventionally, in factories and the like, automation of manufacturing facilities and transfer facilities has been advanced, and processing machines, transfer devices, robots and other devices are electrically connected to a computer via an interface. The operation is controlled by a computer.

However, the signal level of equipment such as processing machines, conveyors, and robots is 100 to several hundreds of volts, whereas the signal level of a computer controlling these equipments is several volts. The noise generated in a machine or the like may affect the computer, causing the computer to malfunction.

In order to prevent this, an optical signal is used as a signal exchanged between the processing machine and the computer, and on / off control is performed by the optical signal. Further, in order to perform such operation control, an optical input type semiconductor element or a semiconductor device configured by combining a photoelectric conversion element and a field effect transistor (FET) has been proposed (Japanese Patent Laid-Open No. 63-293887). Japanese Patent Laid-Open No. 1-235282, etc.). In such a semiconductor device or the like, one end of the photoelectric conversion element is connected to the gate electrode of the transistor and the other end is connected to the source electrode,
The field effect transistor is turned on / off according to an optical signal input to the photoelectric conversion element.

[0005]

However, in the above-mentioned conventional semiconductor device and the like, the photoelectric conversion element is formed on the source electrode of the FET, and the photoelectric conversion element is FE.
Since it is formed after forming the source electrode of T, the photoelectric conversion element must be formed at a temperature lower than the heat resistant temperature of the source electrode. It is desirable to use aluminum for the source electrode because of its low resistance, but it was difficult to produce a photoelectric conversion element with good photoelectric conversion efficiency at a heat-resistant temperature of aluminum of about 660 ° C. or lower.

An object of the present invention is to provide an optical input type semiconductor device having a low resistance electrode and high conversion efficiency.

[0007]

To achieve the above object, the present invention provides a semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate via an insulating film, and a surface of the semiconductor substrate. A source electrode formed and connected to a source region formed near the gate electrode; and a drain electrode connected to a drain region formed on the semiconductor substrate, and a voltage applied to the gate electrode ,
An optical input having an insulated gate transistor in which conduction between the source region and the drain region is controlled, and a photoelectric conversion element formed on the surface of the semiconductor substrate and connected to the gate electrode and the source electrode. In the semiconductor device, the source electrode is made of a low resistance metal, and the photoelectric conversion element is individually formed in a region different from the region where the source electrode is formed on the semiconductor substrate. The gist is an optical input type semiconductor device.

[0008]

In the present invention, the photoelectric conversion element is individually formed in a region different from the region where the source electrode is formed on the semiconductor substrate. Therefore, if the photoelectric conversion element is formed before the source electrode, the photoelectric conversion element can be formed without being affected by the heat resistance of the source electrode. Further, as the source electrode, a metal having low resistance can be used regardless of the heat resistance. As a result, it is possible to provide a light input type semiconductor device having a low resistance electrode and high photoelectric conversion efficiency.

[0009]

1 is a plan view showing an optical input type semiconductor device according to a first embodiment of the present invention. 2 is a line A shown in FIG.
It is sectional drawing in alignment with -A. 3 is a line BB shown in FIG.
FIG. Next, the configuration of the light input type semiconductor device of the first embodiment will be described with reference to FIGS.

As shown in FIG. 2, the optical input type semiconductor device 1
0 ⁺ N ⁺ drain substrate 1 has N ⁻ on the upper surface.
An epitaxial film 3 is provided. P well regions 5 are provided in the surface layer portion of the N ⁻ epitaxial film 3 at predetermined intervals. N ⁺ source regions 7 are provided in the surface layer portions near both ends of the P well region 5 except the central portion. N ⁻ epitaxial film 3 between two adjacent P well regions 5
And the end of the P well region 5 and the N ⁺ source region 7
On a part of the gate electrode 1 through the gate insulating film 9
1 is provided. As can be seen from FIG. 3, the gate electrode 11 extends in the vertical direction along the line BB in FIG. 1, and the portion 13 of the source electrode 13 described later
It extends laterally under b and has a grid shape.

As shown in FIG. 2, a source electrode 13 is provided on a portion of P well region 5 and N ⁺ source region 7. As shown in FIG. 1, the source electrode 13 extends in the vertical direction of the figure and is arranged at predetermined intervals 13a.
And portions 1 which are orthogonal to them and arranged at predetermined intervals
3b and has a lattice shape. Above part 13
b serves to reduce the series resistance of the source electrode 13 (resistance in the extending direction of the portion 13a). The region 13c shown in FIG. 1 includes the P well region 5 and the N ⁺ source region 7.
And the source electrode 13 are in contact with each other.

A drain electrode 15 is provided on the lower surface of the N ⁺ drain substrate 1. The gate electrode 11, the gate insulating film 9, the source electrode 13, the P well region 5, the N ⁺ source region 7, the N ⁻ epitaxial film 3, the N ⁺ drain substrate 1 and the drain electrode 15 are the power MOS.
Configure FET.

An insulating film 17 is formed on the gate electrode 11.
A photovoltaic element 19 as a photoelectric conversion element is provided via the. The photovoltaic element 19 is formed in a region that does not overlap the source electrode 13. In this embodiment, as shown in FIG. 1, three photovoltaic elements 19 arranged in a line in the vertical direction form one unit, and each unit is arranged in each lattice of the source electrode 13 one by one. ing. Photovoltaic element 19
Is a PN junction element made of a polycrystalline silicon film whose upper portion is P-type and whose lower portion is N-type. The width La of the photovoltaic element 19 shown in FIG. 2 is less than or equal to the width of the gate electrode, and the length Lb thereof shown in FIG. 3 is a value determined by the cell size of the photodiode.

As shown in FIG. 3, a photovoltaic element electrode 21 is provided between two adjacent photovoltaic elements 19 of each unit, and the three photovoltaic elements 19 are connected to each other. The electrodes 21 are connected in series. Electrode 2 for photovoltaic element
1 is made of metallic aluminum.

When the threshold voltage of the power MOSFET is positive, the gate end of the P-side end of the three continuous photovoltaic elements 19 is the gate electrode 11 through the hole formed in the insulating film 17.
Is connected to the connection portion 23 extending from the N-side end, and the N-side end is connected to the connection portion 25 extending from the source electrode 13. The connecting portion 25 is connected to the portion 13b as shown in FIG.

Each unit consisting of three photovoltaic elements connected in series is connected in parallel by connecting the P-side and N-side ends to the gate electrode 11 and the source electrode 13, respectively. .. The photovoltaic elements 19 thus connected in series and in parallel form a photovoltaic section described later.

Further, a transparent insulating film 27 is provided so as to cover the photovoltaic element 19, the photovoltaic element electrode 21, the connecting portions 23 and 25, and the source electrode 13. The transparent insulating film 27 is made of, for example, silicon nitride. Transparent insulating film 27
Protects the photovoltaic element 19 and the power MOSFET and guides an optical signal from the outside to the photovoltaic element 19.

FIG. 4 is an equivalent circuit diagram of the light input type semiconductor device of this embodiment. In FIG. 4, in this embodiment, the high potential side of the photovoltaic section 33 formed by combining the photovoltaic elements 19 in series and in parallel as described above is connected to the gate (G) of the power MOSFET 31, The low potential side is connected to the source (S). Power MOSFET 31
Is an element that performs a switching operation by changing the conduction state between the source (S) and the drain (D) according to the magnitude of the voltage applied to the gate (G).

In this embodiment, three photovoltaic elements 1 are used.
9 are connected in series, but the number n of elements connected in series is generally the threshold voltage of the power MOSFET 31 being Vth.
And the photovoltaic power of the photovoltaic element 19 is Vph,
n = Vth / Vph. The number of elements connected in parallel can be calculated from the total element area determined by the required photocurrent and the element area of the n photovoltaic elements 19 obtained by the above equation.

Next, the light input type semiconductor device 10 of the present embodiment.
The operation will be described. When light enters each photovoltaic element 19 of the photovoltaic section 33, the photovoltaic section 33 generates an electromotive force of, for example, about several volts. This electromotive force is power MOS
When it is higher than the threshold voltage Vth of the FET 31, the power MOSFET 31 is turned on. And
When the light is cut off, the electromotive force of the photovoltaic unit 33 becomes 0 V, and the power MOSFET 31 is turned off.

5 to 7 are cross-sectional views for each step for explaining the method of manufacturing the light input type semiconductor device of this embodiment.
Next, the manufacturing method of the present embodiment will be described with reference to FIGS. First, as shown in FIG.
^{+ On the} drain substrate 1, the N ⁻ epitaxial film 3 is epitaxially grown. Both the N ⁺ drain substrate 1 and the N ⁻ epitaxial film 3 are made of single crystal silicon,
The concentration of phosphorus as the dopant is 10 ²⁰ atoms /
cm ³ and the latter is 10 ¹⁵ atoms / cm ³ .

Next, a photoresist is applied on the N ^- epitaxial film 3, and the photoresist is applied by photolithography to FIG.
As shown in (b), a resist pattern 41 is formed by patterning, and boron is ion-implanted using the resist pattern 41 as a mask to form the P well region 5. The concentration of boron is 2 × 10 ¹⁶ atoms / cm ³ .

Next, after removing the resist pattern 41 once, a photoresist is applied on the N ^- epitaxial film 3 and patterned to form a resist pattern 43 shown in FIG. 5C. Then, using the resist pattern 43 as a mask, phosphorus is ion-implanted to form the N ⁺ source region 7. The concentration of phosphorus is 10 ²⁰ atoms / cm
^{Is 3} .

Next, the resist pattern 43 is removed and the exposed surface is thermally oxidized. As a result, the insulating film 45 shown in FIG. 5D is formed on the entire surface. Next, as shown in FIG. 5E, a polycrystalline silicon film 47 is deposited on the insulating film 45 by, for example, a CVD (chemical deposition) method. Then, phosphorus is diffused into the polycrystalline silicon film 47 at a high concentration.

Next, the polycrystalline silicon film 47 and the insulating film 45 are patterned into a predetermined shape to form the gate electrode 11 and the gate insulating film 9 shown in FIG. 5 (f).
Next, as shown in FIG. 6A, PBSG (phosphoroborosilicate glass) is deposited on the entire surface to form the insulating film 17.

Next, as shown in FIG. 6B, the insulating film 1
7 is patterned to form the contact region 13c shown in FIG.
The insulating film 17 is opened. Next, as shown in FIG. 6C, amorphous silicon 49 is formed on the entire surface by a vacuum evaporation method. Then, by annealing at 600 ° C. for 5 hours, crystal growth is performed using the P well region 5 and the N ⁺ source region 7 as seeds, and the amorphous silicon 49 is deposited on the gate electrode 11 via the insulating film 17. Single crystal is formed including the part. As a result, FIG.
The single crystal silicon layer 51 shown in (d) is formed.

Next, as shown in FIG. 6E, the insulating film 1 is formed on the gate electrode 11 in the single-crystallized silicon layer 51.
Portion 5 to be a photovoltaic element of the portion formed via 7
The silicon layer 51 is removed, leaving 3. Then, boron is ion-implanted into the portion 53 at a dose amount so that the impurity concentration becomes 10 ¹⁷ atoms / cm ³ . Next, 1 phosphorus
Ion implantation is performed only on the upper portion of the N layer with a dose amount so as to obtain an impurity concentration of 0 ²⁰ atoms / cm ³ ,
Activated by heat treatment at ℃. In this way, the photovoltaic element 19 is formed.

Next, as shown in FIG. 7A, an aluminum film 55 is formed on the entire surface, and then, as shown in FIG. 7B, the source electrode 13 and the photovoltaic element electrode 21.
The aluminum film other than the above is removed by etching.
Next, as shown in FIG. 7C, the transparent insulating film 27 is formed on the entire surface.
To form the drain electrode 1 on the back surface of the N ⁺ drain substrate 1.
5 is formed.

In the above embodiment, the photovoltaic element 19
All the rows of are arranged so as to face the same direction.
As shown in, the element row 191 extending in the horizontal direction in the figure and the element row 192 extending in the vertical direction in the figure may be combined. Although the photovoltaic element 19 is made of single crystal silicon, it may be made of polycrystalline silicon. Further, as a photovoltaic element, P made of amorphous silicon is used.
You may use the solar cell comprised by the layer, I layer, and N layer.

Further, in the above-mentioned embodiment, the photovoltaic device 1
Although the PN junction is formed by changing the conductivity types of the upper part and the lower part of 9, the PN junction may be formed by changing the conductivity type in the lateral direction. As described above, according to this embodiment, since the photovoltaic element 19 can be formed prior to the formation of the source electrode 13 of the MOSFET, the photovoltaic element 19 is independent of the heat resistance of the source electrode 13. It can be formed under optimal conditions for the photovoltaic element. Further, a semiconductor device can be manufactured by using a metal electrode having a low resistance without using a heat resistant electrode as in the conventional case. Therefore, it is possible to provide a light input type semiconductor device having high photoelectric conversion efficiency and less heat generation.

Further, the source electrode 13 and the photovoltaic element 19
Are formed so that they do not overlap with each other, so that they have excellent effects such as relaxation of the multilayer structure. FIG. 9 shows the second
An example of is shown. In the first embodiment, the transistor of the light input type semiconductor device is a MOSFET, but in the second embodiment, the transistor is an insulated gate bipolar transistor (IGBT), and the drain substrate 101 is made of P or the like made of boron or the like. A dopant in which the shaped dopant is diffused in a high concentration is used.

The voltage generated by the photovoltaic element 19 is detected by
The application to the gate (G) is the same as in the first embodiment.
It FIG. 10 shows a third embodiment. In the first embodiment,
The power MOSFET had a vertical structure, as shown in FIG.
A horizontal structure may be used. In FIG. 10, N^-substrate
A P well region 205 is provided in 201
In the area 205, N ⁺Source region 207 and N⁺Drain territory
Area 208 is provided. N⁺In the source area 207,
The source electrode 213 is connected and N⁺Drain region 208
A drain electrode 215 is connected to. Gate electrode 2
11 is a P well region 205 and N⁺Source area 207
And N^-The gate insulating film 2 is formed on part of the drain region 208.
It is provided via 09. The photovoltaic element 219 has a first
Insulating film 217 is formed on gate electrode 211 in the same manner as in the above embodiment.
Is provided through. On the photovoltaic element 219, the photovoltaic
The force element electrode 221 is formed.

FIG. 11 shows a schematic structure of an optical input switch which is one of application examples of the optical input type semiconductor device of the above embodiment. This optical input switch is configured by combining an optical input type semiconductor device and a light emitting element. In FIG. 11, the optical signal generated from the light emitting element 63 mounted on the lead frame 61 passes through the optical waveguide 65 made of transparent synthetic resin and is incident on the photovoltaic element 19 of the light input type semiconductor device 10. .. In response to this signal, the power MOSF
The ET is turned on and off, and the switching operation is performed.

[Brief description of drawings]

FIG. 1 is a plan view showing a light input type semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA shown in FIG.

3 is a cross-sectional view taken along the line BB shown in FIG.

FIG. 4 is an equivalent circuit diagram of the light input type semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view for each step illustrating the steps from the beginning to the gate electrode manufacturing step in the manufacturing steps of the optical input type semiconductor device of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view for each step explaining the steps from the gate electrode manufacturing step to the photovoltaic element manufacturing step in the manufacturing steps of the light-input semiconductor device of the first embodiment.

FIG. 7 is a cross-sectional view of each step for explaining the photovoltaic element manufacturing step to the final step in the manufacturing steps of the optical input type semiconductor device of the first embodiment.

FIG. 8 is a diagram showing a pattern in which photovoltaic elements are combined so that their orientation directions differ from each other by 90 °.

FIG. 9 is a cross-sectional view showing a second embodiment of the present invention.

FIG. 10 is a sectional view showing a third embodiment of the present invention.

FIG. 11 is a diagram showing a schematic configuration of an optical input switch which is one of application examples of the optical input type semiconductor device of the present invention.

[Explanation of symbols]

1 ... N ⁺ drain substrate, 3 ... N ^- epitaxial film, 5 ...
P well region, 7 ... N ⁺ source region, 9 ... Gate insulating film, 11 ... Gate electrode, 13 ... Source electrode, 15 ... Drain electrode, 19 ... Photovoltaic element, 27 ... Transparent insulating film

Front page continuation (72) Inventor Kunihiko Hara 1-1, Showa-cho, Kariya city, Aichi Nihon Denso Co., Ltd.

Claims (1)

1. A semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate via an insulating film, and formed on the surface of the semiconductor substrate in the vicinity of the gate electrode. A source electrode connected to the source region and a drain electrode connected to the drain region formed on the semiconductor substrate, and the source region and the drain region are connected to each other by a voltage applied to the gate electrode. A light input type semiconductor device having an insulated gate transistor whose conduction between the electrodes is controlled, and a photoelectric conversion element formed on the surface of the semiconductor substrate and connected to the gate electrode and the source electrode, wherein the source electrode Is made of a low resistance metal, and the photoelectric conversion element is separately formed in a region different from the region where the source electrode is formed on the semiconductor substrate. Optical input type semiconductor device according to claim.