JPH05218272A - Manufacture of lead frame - Google Patents

Manufacture of lead frame

Info

Publication number
JPH05218272A
JPH05218272A JP4016743A JP1674392A JPH05218272A JP H05218272 A JPH05218272 A JP H05218272A JP 4016743 A JP4016743 A JP 4016743A JP 1674392 A JP1674392 A JP 1674392A JP H05218272 A JPH05218272 A JP H05218272A
Authority
JP
Japan
Prior art keywords
lead frame
insulating film
manufacturing
island
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4016743A
Other languages
Japanese (ja)
Inventor
Hiroko Otaki
浩子 大瀧
Yasushi Yamamura
康 山村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP4016743A priority Critical patent/JPH05218272A/en
Publication of JPH05218272A publication Critical patent/JPH05218272A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a manufacturing method of a lead frame wherein multipin structure of high precision is realized, excellent bondability is ensured, manufacturing process is simple and easy, and manufacturing cost containing device and equipment is low. CONSTITUTION:In a lead frame wherein extension electrodes 3 are arranged on an insulating film 2 which is formed at least on the peripheral end portion of an island 1, and individually insulated on the insulating film 2, the insulating film 2 is formed by a formation process.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、IC、LSI等の集積
回路からなる半導体装置に用いられるリードフレームの
製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a lead frame used in a semiconductor device composed of integrated circuits such as IC and LSI.

【0002】[0002]

【従来の技術】中継電極部が、アイランド上の少なくと
も周辺端部に設けられた絶縁性皮膜上にあり、しかも個
々に絶縁されている半導体装置用リードフレームの一例
を(図3)に示す。リードフレームの一部を成すアイラ
ンド1上の前記集積回路を搭載する面側をここで上面と
し、上面中央部には金Au又は銀Agからなる金属皮膜
8が形成され、前記金属皮膜8上には前記集積回路6が
搭載されてあるとともに、上面の周辺端部には気相成長
法により絶縁性皮膜9が形成され、前記絶縁性皮膜9の
面上には導電体からなる中継電極部3が形成されてあ
る。これにより前記IC、LSI等の集積回路の急速な
高集積化及び多機能化に対応したリードフレームの高精
細化や多ピン化の要求に対応していた。
2. Description of the Related Art An example of a lead frame for a semiconductor device, in which a relay electrode portion is provided on an insulating film provided on at least a peripheral end portion on an island, and is individually insulated, is shown in FIG. Here, the surface side on which the integrated circuit is mounted on the island 1 forming a part of the lead frame is the upper surface, and the metal film 8 made of gold Au or silver Ag is formed at the center of the upper surface. Is mounted with the integrated circuit 6, an insulating film 9 is formed on the peripheral edge of the upper surface by a vapor phase growth method, and a relay electrode part 3 made of a conductor is formed on the surface of the insulating film 9. Has been formed. As a result, the demand for higher definition and higher pin count of the lead frame corresponding to the rapid integration and multifunction of integrated circuits such as ICs and LSIs has been met.

【0003】ところが、前記従来技術に係わるリードフ
レームでは、前記絶縁性皮膜9の形成に際し主に気相成
長法が用いられている。前記気相成長法には代表的なも
のに真空蒸着法や陰極スパッタリング法があるが、両者
共に真空中で物理的作用により薄膜を形成する方法であ
る。そのため、製造装置には成膜用の真空状態を提供す
る装置や設備が必要であり、前記成膜を施すに際して、
高度でしかも複雑な技術を含む工程を必要とし、さらに
前記装置や設備はコストが非常に高くかかるという問題
があった。
However, in the lead frame according to the above conventional technique, the vapor phase growth method is mainly used for forming the insulating film 9. Typical vapor phase growth methods include a vacuum vapor deposition method and a cathode sputtering method, both of which are methods of forming a thin film by a physical action in a vacuum. Therefore, the manufacturing apparatus requires a device and equipment for providing a vacuum state for film formation, and when performing the film formation,
There is a problem in that a process including a sophisticated and complicated technique is required and the cost of the device and equipment is very high.

【0004】一方、前記従来の技術には、前記絶縁性皮
膜9の形成にポリイミド等からなる絶縁性シートを用い
る場合もあった。この場合にはワイヤボンディングの際
に施す加熱により前記ポリイミド等からなる絶縁性皮膜
9が若干の軟化を起こし、前記気相成長法による場合の
絶縁性皮膜9と比較してボンダビリティが劣ってしまう
という問題があった。
On the other hand, in the conventional technique, an insulating sheet made of polyimide or the like may be used for forming the insulating film 9. In this case, the insulating coating 9 made of polyimide or the like is slightly softened by the heating applied during the wire bonding, and the bondability is inferior to the insulating coating 9 obtained by the vapor phase growth method. There was a problem.

【0005】[0005]

【発明が解決しようとする課題】本発明は前記問題点に
鑑みなされたものであり、リードフレームの多ピン化、
高精細化に対応でき、良好なボンダビリティを確保しつ
つ、しかも製造工程が簡便で容易であり、さらに装置及
び設備を含めて製造費用が低コストでもあるリードフレ
ームの製造方法を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a multi-pin lead frame,
It is possible to provide a lead frame manufacturing method capable of accommodating high definition, ensuring good bondability, and having a simple and easy manufacturing process and a low manufacturing cost including equipment and facilities. To aim.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
に本発明が提供する手段は、すなわち、中継電極3が、
アイランド1上の少なくとも周辺端部に設けられた絶縁
皮膜2上にあり、しかも該中継電極3が該絶縁皮膜2上
で個々に絶縁されているリードフレームにおいて、該絶
縁性皮膜2が化成処理法により形成されることを特徴と
するリードフレームの製造方法である。
Means provided by the present invention for solving the above-mentioned problems are as follows:
In a lead frame on the insulating film 2 provided at least at the peripheral end of the island 1, and the relay electrodes 3 are individually insulated on the insulating film 2, the insulating film 2 is treated by a chemical conversion treatment method. And a lead frame manufacturing method.

【0007】ここで化成処理法とは、試料に対してその
表面に化学的作用により化合物皮膜を形成する方法であ
り、特に本発明中では、金属板を基材となす前記リード
フレームを化成処理浴中に浸漬するという簡便な操作に
より、絶縁性能に優れ且つボンディングワイヤとの密着
性も良好な化合物皮膜を均一に形成できる方法である。
Here, the chemical conversion treatment is a method of forming a compound film on the surface of a sample by a chemical action, and particularly in the present invention, the chemical conversion treatment of the lead frame having a metal plate as a base material is performed. This is a method capable of uniformly forming a compound film having excellent insulation performance and good adhesion with a bonding wire by a simple operation of immersing in a bath.

【0008】尚、前記リードフレーム上への前記絶縁性
皮膜2の形成に際しては、前記化成処理法による絶縁性
皮膜2が不要な部分を、前記化成処理用の液に侵されな
い材質のもので予めマスキングしておき、次に前記化成
処理浴中に浸漬して前記絶縁性皮膜2を設け、しかる後
に前記のマスキングを除去すると処理が容易である。例
えば、前記アイランド1部を除く全ての部分をマスキン
グしておくか、あるいは場合によっては、さらにアイラ
ンド1上の中央部をもマスキングしておくことが好まし
い。
When forming the insulating coating 2 on the lead frame, the portion not requiring the insulating coating 2 formed by the chemical conversion treatment is previously made of a material that is not attacked by the chemical conversion treatment liquid. Masking is performed, and then the insulating coating 2 is provided by immersing in the chemical conversion treatment bath, and then the masking is removed, whereby the treatment is easy. For example, it is preferable to mask all parts except the island 1 part, or, in some cases, further mask the central part on the island 1.

【0009】[0009]

【作用】本発明に係わるリードフレームの製造方法によ
ると、アイランド1上に前記化成処理法により絶縁性皮
膜2を形成するために、製造工程が簡便で容易であり、
しかも装置及び設備が低コストでもあり、さらには絶縁
性能に優れ且つボンディングワイヤとの密着性も良くボ
ンダビリティに優れた化合物皮膜を均一に形成できる。
しかも絶縁性皮膜上に中継電極を膜の形態で形成するた
め、面積の狭い領域に多数の高精細な前記中継電極を設
けることができる。
According to the lead frame manufacturing method of the present invention, since the insulating film 2 is formed on the island 1 by the chemical conversion treatment, the manufacturing process is simple and easy.
In addition, the cost of the equipment and facilities is low, and the compound film having excellent insulation performance, good adhesion to the bonding wire and excellent bondability can be uniformly formed.
Moreover, since the relay electrode is formed in the form of a film on the insulating film, it is possible to provide a large number of highly precise relay electrodes in a region having a small area.

【0010】これにより従来技術中の前記気相成長法に
より絶縁性皮膜9を形成する場合と比較すると、製造工
程が簡便で容易であり、また製造のための装置及び設備
が低コストでもある。そしてこのとき、ボンダビリティ
や絶縁性も十分であり、特に絶縁性に関しては均一で性
能が高く且つピンホールが極めて少ない良質な絶縁性皮
膜を得られる。また、従来技術中の前記樹脂による絶縁
性皮膜9と比較した場合、ボンダビリティが向上する。
これは前記樹脂による絶縁性皮膜9では、ワイヤボンデ
ィング時の加熱による絶縁性皮膜9の若干の軟化のため
に、超音波振動を付与した際のエネルギーの分散及び集
積回路のずれが発生しワイヤボンディングを効果的に施
すことが困難なためにボンダビリティが劣っていたもの
であるが、本発明に係る絶縁性皮膜2ではそれが未然に
防止でき良好なボンダビリティを確保できる。
As a result, as compared with the case of forming the insulating film 9 by the vapor phase growth method in the prior art, the manufacturing process is simple and easy, and the apparatus and equipment for manufacturing are also low in cost. At this time, bondability and insulation are also sufficient, and in particular, a high-quality insulation film having uniform insulation performance, high performance, and extremely few pinholes can be obtained. Also, bondability is improved when compared with the insulating film 9 made of the resin in the prior art.
This is because in the insulating film 9 made of the resin, energy is dispersed when ultrasonic vibration is applied and the integrated circuit is displaced due to slight softening of the insulating film 9 due to heating during wire bonding, which causes wire bonding. Although the bondability was inferior because it was difficult to apply effectively, the insulating film 2 according to the present invention can prevent it in advance and ensure good bondability.

【0011】[0011]

【実施例】以下、図面を参照して本発明の実施例につい
て説明する。(図1)には本発明の一実施例に係わるリ
ードフレームの平面図を示してあり、また(図2)には
(図1)のA−A断面図を示してある。尚、ここではリ
ードフレーム用Fe−Ni系合金として多く使用され一
般に42合金と称される材質に本発明を適用した場合を
示す。
Embodiments of the present invention will be described below with reference to the drawings. 1 is a plan view of a lead frame according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG. Here, a case where the present invention is applied to a material which is often used as an Fe-Ni alloy for lead frames and is generally called 42 alloy is shown.

【0012】まずアイランド1の上面のみに前記化成処
理法により絶縁皮膜2を形成するため、処理するリード
フレームにフォトレジストを塗布した後、所定のマスク
を介して露光、現像を行なうことにより、アイランド1
の上面以外の部分に前記化成処理用のマスキングを施し
ておいた。
First, since the insulating film 2 is formed only on the upper surface of the island 1 by the chemical conversion treatment method, a photoresist is applied to the lead frame to be processed, and then exposure and development are performed through a predetermined mask to form the island. 1
The portion other than the upper surface of the above was masked for the chemical conversion treatment.

【0013】次に227リットルのH3 PO4 (純度7
5%)中へMnCO3 を107kg添加し、さらにH2
Oを227リットル加えた組成の溶液5リットルを、水
455リットル中に溶かした水溶液を用意しこれを化成
処理浴とする。前記化成処理浴を93℃に加熱してある
中へ処理を施すべき前記リードフレームを5分間浸漬し
引き上げることにより前記絶縁性皮膜2を形成した。こ
のとき促進剤を適量添加(例えばZn(NO3 2 を2
0g/リットル)すると、前記絶縁性皮膜2をより短時
間で形成できた。このときの前記絶縁性皮膜2の膜厚は
1μm程度のものが得られる。その後、前記マスキング
材を除去しておいた。
Next, 227 liters of H 3 PO 4 (purity 7
5%) to which 107 kg of MnCO 3 was added, and further H 2
An aqueous solution prepared by dissolving 5 liters of a solution containing 227 liters of O in 455 liters of water is prepared and used as a chemical conversion treatment bath. The insulating coating 2 was formed by immersing the lead frame to be treated in the chemical conversion bath heated to 93 ° C. for 5 minutes and pulling it up. At this time, an appropriate amount of accelerator is added (for example, Zn (NO 3 ) 2 is added to 2
0 g / liter), the insulating film 2 could be formed in a shorter time. At this time, the film thickness of the insulating film 2 is about 1 μm. Then, the masking material was removed.

【0014】次にアイランド1の絶縁性皮膜2上の周辺
端部に気相成長法を用いて薄膜からなる前記中継電極3
を形成した。このとき前記中継電極3はインナーリード
先端部4と相対位させた配置に形成した。前記アイラン
ド1中央部の絶縁性皮膜2上にAgペースト層5を設
け、さらにAgペースト層5を介して集積回路6を搭載
した。しかる後に前記集積回路6と前記中継電極3との
間、及び前記中継電極3とインナーリード先端部4との
間に、それぞれワイヤボンディングを施した後に封止樹
脂7を用いて封止した。尚、ボンディングワイヤの材質
として通常使用されるAl又はAuを用いた。
Next, the relay electrode 3 made of a thin film is formed at the peripheral end portion on the insulating film 2 of the island 1 by the vapor phase growth method.
Formed. At this time, the relay electrode 3 was formed so as to be positioned relative to the tip 4 of the inner lead. An Ag paste layer 5 was provided on the insulating film 2 in the center of the island 1, and an integrated circuit 6 was mounted via the Ag paste layer 5. Then, wire bonding was performed between the integrated circuit 6 and the relay electrode 3, and between the relay electrode 3 and the inner lead tip portion 4, and thereafter, sealing was performed using a sealing resin 7. In addition, Al or Au which is usually used as the material of the bonding wire was used.

【0015】これは製造工程が簡便で容易であり、また
製造のための装置及び設備が低コストでもあった。そし
てこのとき、ボンダビリティや絶縁性も十分であり、特
に絶縁性に関しては均一で性能が高く且つピンホールが
極めて少ない良質な絶縁性皮膜を得られた。
This is because the manufacturing process is simple and easy, and the apparatus and equipment for manufacturing are low in cost. At this time, the bondability and the insulating property were sufficient, and in particular, the insulating film was uniform in terms of the insulating property and high in performance, and a good quality insulating film with very few pinholes was obtained.

【0016】[0016]

【発明の効果】以上、詳細に説明してきたように、本発
明に係わるリードフレームの製造方法によると、ワイヤ
ボンディング時の加熱にも耐え十分に良好なボンダビリ
ティを確保しており、且つ高品質の絶縁性皮膜を、製造
工程が簡便で容易であり、また製造のための装置及び設
備は低コストであった。これは従来の気相成長法による
場合や樹脂を材料に用いた場合と比較して、形成方法が
容易であり、また複雑で高価な装置や設備を必要とせ
ず、より低コストで製造することが可能となった。すな
わち本発明によると、IC、LSI等の集積回路の高集
積化、多機能に伴うリードフレームの多ピン化、高精細
化への要求に十分対応することができ、また良好なボン
ダビリティを確保しつつ、しかも製造工程が簡便で容易
であり、さらに装置及び設備を含めて製造費用が低コス
トでもあるリードフレームの製造方法を提供することが
できた。
As described above in detail, according to the lead frame manufacturing method of the present invention, it is possible to withstand the heating during wire bonding and to secure sufficiently good bondability and to obtain high quality. The manufacturing process of the insulating film of No. 3 was simple and easy, and the apparatus and equipment for manufacturing were low cost. Compared with the conventional vapor phase growth method and the case of using resin as the material, this method is easier to form, does not require complicated and expensive equipment and facilities, and can be manufactured at lower cost. Became possible. That is, according to the present invention, it is possible to sufficiently meet the demands for higher integration of integrated circuits such as ICs and LSIs, higher pin count of lead frames due to multiple functions, and higher definition, and to secure good bondability. At the same time, it is possible to provide a method for manufacturing a lead frame, which has a simple and easy manufacturing process and has a low manufacturing cost including the apparatus and equipment.

【0017】[0017]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係わる製造方法を施したリ
ードフレームの平面を示す説明図である。
FIG. 1 is an explanatory view showing a plane of a lead frame which has been subjected to a manufacturing method according to an embodiment of the present invention.

【図2】(図1)中のA−A断面を示す説明図である。FIG. 2 is an explanatory view showing a cross section taken along the line AA in FIG.

【図3】従来技術の一例に係わるリードフレームを側方
からみた断面を示す説明図である。
FIG. 3 is an explanatory view showing a cross section of a lead frame according to an example of a conventional technique as viewed from the side.

【符号の説明】[Explanation of symbols]

1・・・アイランド 2・・・絶縁性皮膜 3・・・中継電極 4・・・インナーリード先端部 5・・・Agペースト層 6・・・集積回路 7・・・封止樹脂 8・・・Au又はAgから成る皮膜 9・・・気相成長法による(または樹脂からなる)絶縁
性皮膜 10・・・Alまたは貴金属からなる皮膜
1 ... Island 2 ... Insulating film 3 ... Relay electrode 4 ... Inner lead tip part 5 ... Ag paste layer 6 ... Integrated circuit 7 ... Encapsulating resin 8 ... Film made of Au or Ag 9 ... Insulating film by vapor phase growth method (or resin) 10 ... Film made of Al or noble metal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】中継電極(3)が、アイランド(1)上の
少なくとも周辺端部に設けられた絶縁皮膜(2)上にあ
り、しかも該中継電極(3)が該絶縁皮膜(2)上で個
々に絶縁されているリードフレームにおいて、該絶縁性
皮膜(2)が化成処理法により形成されることを特徴と
するリードフレームの製造方法。
1. A relay electrode (3) is on an insulating coating (2) provided on at least a peripheral edge of the island (1), and the relay electrode (3) is on the insulating coating (2). A method of manufacturing a lead frame, wherein the insulating film (2) is formed by a chemical conversion treatment method on the lead frame which is individually insulated by the method.
JP4016743A 1992-01-31 1992-01-31 Manufacture of lead frame Pending JPH05218272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4016743A JPH05218272A (en) 1992-01-31 1992-01-31 Manufacture of lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4016743A JPH05218272A (en) 1992-01-31 1992-01-31 Manufacture of lead frame

Publications (1)

Publication Number Publication Date
JPH05218272A true JPH05218272A (en) 1993-08-27

Family

ID=11924753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4016743A Pending JPH05218272A (en) 1992-01-31 1992-01-31 Manufacture of lead frame

Country Status (1)

Country Link
JP (1) JPH05218272A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110892A (en) * 2000-09-27 2002-04-12 Rohm Co Ltd Multi-chip semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110892A (en) * 2000-09-27 2002-04-12 Rohm Co Ltd Multi-chip semiconductor device

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