JPH05218020A - Method of forming thin film wiring - Google Patents

Abstract

PURPOSE:To prevent thinning of wiring due to side-etching and a formation of plating other than a wiring forming part and enhance a close adhesive characteristic of a film in the case where a wiring is formed by a nonelectrolytic plating method on an insulating or semiconductive substrate. CONSTITUTION:There are provided a step in which photoresist 8 is applied and a necessary wiring region 11 is transferred, a step in which, by using the resist pattern as a mask, a catalyzer of electroless plating or the material of an activating agent is ion-implanting, and a step in which, after photoresist is removed, a catalyzer 12 remaining is removed by sputter-etching and, after a catalyzer ion-implanting layer 10 is left only in a wiring forming region, electroless plating is performed to form a wiring by an electroless plating layer 13. As the etching is not performed after plating, an influence of side etching is not exerted and the catalyzer does not adhere to a part other than a wiring pattern part, whereby growth of an unnecessary plating layer is prevented, and also as the catalyzer ion-implanting layer 10 is buried in the substrate surface, a close adhesive characteristic of a film is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a thin film wiring, and more particularly to a method for forming a thin film wiring using electroless plating.

[0002]

2. Description of the Related Art Conventionally, in order to form a thin film wiring on an insulating substrate, a semi-insulating substrate or a substrate having an insulating film, a conductive undercoat film is previously formed by vapor deposition, sputtering or electroless plating. .. Next, in order to further reduce the resistance of the wiring on the underlying coating, a thick coating is formed by electrolytic plating or electroless plating, and then a desired wiring pattern is formed by photolithography.

4A to 4D are sectional views showing a conventional method of forming a thin film wiring in the order of steps. FIG. 4 shows an example of forming a base film by electroless plating. As shown in FIG. 4A, a catalyst layer 2 containing, for example, palladium (Pd) is used as a reaction catalyst for electroless plating on the substrate 1.
Apply and form on top.

Next, as shown in FIG. 4B, the catalyst layer 2
The baking catalyst layer 3 is firmly fixed on the substrate 1 by baking.

Next, when immersed in an electroless plating solution, for example, a mixed solution of water-soluble nickel (Ni) salt and hypophosphite (NaH ₂ PO ₂ ), the catalyst layer 3 acts so that the electroless plating solution Ni ions are reduced and deposited on the catalyst layer 3, and the reduction reaction proceeds with the reduced Ni as the nucleus. as a result,
As shown in FIG. 4C, the electroless plating layer 4 having a thickness of about 1 μm is formed by heating at about 80 ° C. for 20 minutes.

Next, a photoresist 5 is applied on the electroless plating layer 4 and the photoresist 5 is patterned by photolithography to form a resist pattern corresponding to the wiring pattern.

Next, as shown in FIG. 4D, the exposed portions of the electroless plating layer 4 and the catalyst layer 3 are removed by etching using the photoresist 5 as a mask, and the resist layer 5 is further removed. A desired wiring pattern is completed by the electroless plating layer 4.

[0008]

However, the above-mentioned wiring forming method has the following drawbacks. First, the etching solution for the electroless plating layer 4 and the etching solution for the catalyst layer 3 largely corrode the electroless plating layer 4 immediately below the resist 5, and a so-called side etching phenomenon appears. Therefore, there is a drawback that it is difficult to form fine wiring. As a forming method for reducing the side etching, as shown in FIG. 5A, there is a method of patterning the resist 5 so that the wiring portion is opened and then depositing the catalyst layer 2. When the catalyst layer 2 on the resist 5 is also removed by dissolving and removing the resist 5 thereafter, the catalyst layer 2 remains only at the bottom of the opening, and if the catalyst layer 2 is dipped in the electroless plating solution, the catalyst layer 2 shown in FIG. As shown in b), the electroless plating layer 4 is formed, and the substrate having a desired wiring pattern is completed.

However, according to this method, the catalyst layer 2 on the resist 5 may stick to the substrate 1, and if plating is performed as it is, as shown in FIG. 5B, the catalyst layer 6 on the substrate 1 is stuck. However, there is a drawback that the electroless plating layer 7 is formed. Further, each coating is only physically attached to the surface of the substrate, and there is a drawback that the adhesion is poor.

The present invention has been made in view of the above problems, and it is possible to prevent side etching and form fine wiring, and to prevent the formation of an electroless plating layer in an unnecessary portion. At the same time, it is an object of the present invention to provide a method for forming a thin film wiring having good adhesion of a film.

[0011]

A method of forming a thin film wiring according to the present invention comprises a step of forming a wiring on a semiconductor substrate or an insulating substrate, a step of applying a photoresist and transferring a required wiring pattern, Using this wiring pattern as a mask, a step of ion-implanting a substance that serves as a catalyst or activator for electroless plating into a wiring formation region, a step of performing sputter etching after removing the photoresist, and a step of performing electroless plating are performed. It is characterized by having.

Since a substrate having an insulating film formed on its surface has the same function and effect as the substrate itself having an insulating property, it is included in the present invention as an insulating substrate.

[0013]

In the present invention, the electroless plating catalyst is ion-implanted on the surface of the substrate in a predetermined wiring pattern to form the underlying catalyst layer, and then the electroless plating is performed. Wiring can be formed.
Further, since the photoresist is removed and then the sputter etching is performed, the catalyst layer remaining other than the wiring formation portion can be completely removed, and the formation of the electroless plating layer in an unnecessary portion can be prevented. .. Furthermore, since the catalyst serving as the core is embedded in the surface of the substrate, good adhesion of each film can be obtained.

[0014]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIGS. 1A to 1D are sectional views of a substrate showing a method of an embodiment of the present invention in the order of steps. As shown in FIG. 1A, a photoresist 8 is applied on the substrate 1 so that an opening is formed in a required wiring formation region 11,
The photoresist 8 is patterned by photolithography. Further, using the photoresist 8 as a mask, electroless plating, for example, a catalyst palladium (Pd) for nickel (Ni), for example, with an energy of 100 to 200 Kev and about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^-2 is used. Ion implantation is performed under the condition of the dose amount to form the ion implantation layer 10 on the surface of the substrate 1 in the wiring formation region 11. At this time, Pd has a Gaussian type concentration distribution having a peak at a position of about 0.03 to 0.06 μm from each surface, and the ion implantation layer 9 of the photoresist 8 and the ion implantation layer of the substrate 1 are Forming 10. In this case, if the thickness of the photoresist 8 is set to 1 μm or more, Pd does not reach the substrate 1 below the photoresist 8. However, in the subsequent step of removing the photoresist 8, a stripping process is usually performed with an organic solvent or an acid, so that Pd existing in the ion implantation layer 9 in the photoresist 8 is eluted. Most of this Pd remains in the solvent, but some Pd redeposits on the substrate surface, and the catalyst 12 remains on the substrate surface as shown in FIG. 1 (b).

Next, as shown in FIG. 1C, the substrate 1 is sputter-etched to remove the unnecessary catalyst 12 remaining on the surface. If the catalyst layer 12 remains in a small amount other than the wiring forming region 11, the electroless plating layer is deposited by this catalyst, and therefore it is necessary to completely remove the catalyst layer 12. At the time of sputter etching, a part of the substrate surface is also removed, but the concentration peak of the catalyst layer injected into the injection layer 10 is slightly deeper than the surface, so sputter etching for cleaning has no effect. It is preferable that the catalyst concentration on the surface of the substrate is increased without receiving the reaction. Although the residual catalyst 12 and the surface of the substrate 1 can be removed by wet etching, a part of the catalyst adheres to various parts of the surface, resulting in an adverse effect, which is not preferable.

Thereafter, as shown in FIG. 1 (d), the obtained substrate 1 is dipped in an electroless plating solution to take advantage of the feature of electroless plating to deposit only on the catalyst layer (ion implantation layer 10). , The plating layer 13 is deposited. As a result, the wiring pattern having the desired wiring is completed.

2 (a) to 2 (c) and FIGS. 3 (a) and 3 (b) are sectional views showing the method of the second embodiment of the present invention in the order of steps.

As shown in FIG. 2A, a photoresist 23 is applied on a semiconductor substrate 21 whose surface is previously covered with a thin insulating film 22, a wiring forming region 26 is patterned, and then electroless plating is performed. The catalyst is ion-implanted to form an injection layer 24 on the surface of the photoresist 23 and an injection layer 25 on the surface of the substrate 21.
To form. In this case, the depth of ion implantation is the insulating film 2
It is adjusted so that the peak of the Pd concentration comes to the interface between the substrate 2 and the substrate 21.

Next, as shown in FIG. 2B, the insulating film 22 in the wiring formation region 26 is removed, and further the photoresist 23 is removed. Hereinafter, as in the first embodiment, FIG.
As shown in (c), the unnecessary residual catalyst 27 is removed by the sputter etching method.

Then, as shown in FIG. 3A, the wiring layer of this embodiment is formed by immersing in an electroless plating solution and depositing an electroless plating layer 28 on the ion implantation layer 25. It In addition, in FIG. 1A and FIG. 2A, the electroless plating catalyst is ion-implanted and the implantation layers 9, 10, and 2 are formed.
Although Nos. 4, 25 are formed, the same effect can be obtained by using a catalyst activator such as tin (Sn) instead of the catalyst. In this case, FIG. 1 (a) and FIG. 2 (a)
The difference is that a step of injecting Sn is provided in place of the step of injecting the catalyst ions of the first and second examples, respectively, and the subsequent steps of removing the resist and removing the remaining activator are Similar to the first and second embodiments, FIG.
As shown in (b), an ion-implanted layer 29 of activator is formed instead of the catalyst.

Next, prior to the electroless plating in the subsequent step,
Catalyst solution such as 0.01 of palladium chloride (PdCl ₂ )
% -1% solution, immersing the substrate in activator (eg Sn)
And the catalyst (for example, Pd) are replaced, the replaced catalyst layer 30 is formed on the surface of the activator ion implantation layer 29. Next, by dipping in an electroless plating solution and depositing a plating layer on the catalyst layer 30, desired wiring is formed.

Although the above description has focused on Ni plating, the present invention is not limited to this, and various methods can be applied. Further, it goes without saying that the catalyst is not limited to Pd, and elements of Group 8 such as platinum and nickel may be used.

[0024]

As described above, according to the present invention,
After forming the underlying catalyst layer by ion implantation on the substrate surface,
Since electroless plating is performed, fine wiring can be formed without wiring erosion due to side etching. Further, since the catalyst layer remaining other than the wiring forming portion is completely removed by sputter etching, it is possible to prevent the electroless plating layer from being formed in an unnecessary portion. Furthermore, since the catalyst serving as the core is embedded in the surface of the substrate, good adhesion of the film can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing the first half of the steps of the method according to the second embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing the latter half of the steps of the method according to the second embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a conventional forming method in the order of steps.

FIG. 5 is a cross-sectional view showing another conventional forming method in the order of steps.

[Explanation of symbols]

 1; substrate 2; catalyst layer 3; baked catalyst layer 4, 13, 28; electroless plating layer 5, 8, 22; photoresist 6; stuck catalyst layer 7; electroless formed on catalyst layer 6 Plating layer 9, 24; Ion implantation layer in resist 10, 25; Ion implantation layer in substrate 11, 26; Wiring formation region 12, 27; Remaining catalyst 21; Semiconductor substrate

Claims (1)

[Claims] 1. A method for forming a wiring on a semiconductor substrate or an insulating substrate, the step of applying a photoresist to transfer a desired wiring pattern, and a catalyst or activator for electroless plating using this wiring pattern as a mask. And a step of performing sputter etching after removing the photoresist, and a step of performing electroless plating.