JPH05217385A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To perform stable read-out by comparing potential of two dummy bit lines with potential of a bit line, in all combinations of two dummy bit lines whose set values of mutual conductance are close each other. CONSTITUTION:A column selecting circuit 2 connects a bit line B1 to a data line D, while a charging circuit 3 previously charges the line D and the line B1 at potential of V0 by making a CP signal activated state. If the transistor 11 of a memory 1 is set to a prescribed threshold value, a reference voltage VRFF2 is neglected and a comparison result SA1 is outputted by comparing with a reference voltage VRFF1 in a first comparator 5. The reference voltage VRFF2 is neglected and a comparison result SA2 is outputted by only comparing with a reference voltage VRFF3 in a second comparator 6 too. Therefore, since these potential differences in comparison have the range more than the least set pitch among threshold values of at least three kinds, the comparison margin can be enlarged, and stable read-out can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for storing multi-valued information of three or more values depending on the difference in threshold value of a memory cell transistor.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a mask ROM,
In many cases, information is stored depending on the difference in the threshold value of the memory cell transistor.

When binary information is stored in this memory cell transistor, a gate voltage between two threshold values is applied to this memory cell transistor at the time of selection to turn it on or off. Since it is sufficient to saturate it, reading can be performed with a sufficient margin.

However, in the case of storing multi-valued information of three or more values, three or more kinds of threshold values are required, and the output voltage of the memory cell transistor to which a predetermined gate voltage is applied is referred to by two or more kinds. It is necessary to read the information by comparing with the voltage.

FIG. 3 shows a read circuit of a conventional semiconductor memory device for storing three-valued information. For example, when reading data from the memory cell transistor Q11, first, the column selection circuit 11 is selected based on the column address.
Connects the bit line B1 to the data line D, and activates the CP signal, so that the charging circuit 12 precharges the bit line B1 to the V0 potential via the data line D. Also, the word line WL1 is selected based on the row address, and the gate voltage of the power supply voltage VCC level is applied to the memory cell transistor Q11.

When the CP signal is returned to the inactive state and the charging circuit 12 is stopped in the above state, the potential of the bit line B1 changes according to the setting of the threshold value of the memory cell transistor Q11. That is, for example, when the memory cell transistor Q11 is set to a low threshold value Vth1 (about 0.5 V), it is turned on and the transconductance becomes sufficiently large. A large discharge current flows through. Therefore, the potential of the bit line B1 drops rapidly as shown by the discharge characteristic E1 in FIG. Further, even when the memory cell transistor Q11 is set to the intermediate threshold value Vth2 (about 2.5V), it is turned on, but the transconductance does not increase so much, so that the discharge current also becomes the threshold value Vth.
Less than in the case of th1. Therefore, the potential of the bit line B1 decreases relatively gently as indicated by the discharge characteristic E2. Further, when the memory cell transistor Q11 is set to the threshold value Vth3 higher than the power supply voltage VCC level, the transconductance becomes extremely small and the discharge current hardly flows.
Therefore, the potential of the bit line B1 remains the V0 potential as indicated by the discharge characteristic E3.

In this way, the potential of the bit line B1 which changes according to the setting of the threshold value of the memory cell transistor Q11 is input to the first comparison circuit 13 and the second comparison circuit 14 via the data line D. To be done. Further, the reference voltages VREF1 and VREF2 from the reference voltage generation circuit 15 are input to the first comparison circuit 13 and the second comparison circuit 14, respectively. As shown in FIG. 4, the potential of the reference voltage VREF1 drops from the V0 potential at an intermediate speed between the discharge characteristic E1 and the discharge characteristic E2. Further, the potential of the reference voltage VREF2 decreases more gently than the discharge characteristic E2. Therefore, from time t1 to time t in FIG.
During the period up to 2, the potential of the data line D is changed by the first comparison circuit 13 and the second comparison circuit 14 to the reference voltages VREF1 and VRE.
When compared with F2, respectively, the threshold value set in the memory cell transistor Q11 can be judged based on the comparison results SA1 and SA2, and the stored information can be read.

[0008]

However, in the above-mentioned conventional read circuit, when the memory cell transistor Q11 is set to the threshold value Vth2, the discharge characteristic E2 is set.
The difference between the reference voltage VREF1 and the reference voltage VREF1 is 2 between the discharge characteristics E1 and E2.
In addition, the potential difference from the reference voltage VREF2 is less than half the discharge characteristics E2 and E3, and the comparison margin between the first comparison circuit 13 and the second comparison circuit 14 is reduced. In addition, the threshold value actually set in the memory cell transistor Q11 has an error, and the parasitic capacitance of the bit line B1 also varies. Therefore, such a small comparison margin is not always sufficient. ..

Therefore, in the conventional semiconductor memory device, when multi-valued information is stored in the memory cell transistor as a threshold value, there is a problem that the comparison margin may be insufficient and stable reading may not be possible. there were.

In view of the above circumstances, the present invention compares the output potential of a selected memory cell transistor with the output potential of a dummy cell transistor having the same characteristics,
It is an object of the present invention to provide a semiconductor memory device capable of increasing the comparison margin and performing stable reading.

[0011]

According to the semiconductor memory device of the present invention, a bit line which is precharged to a constant potential when reading data has any one of a plurality of predetermined transconductances of three or more values. And a semiconductor memory device having a memory cell array in which a large number of memory cell transistors to which a predetermined gate voltage is applied and which is selected when data is read are connected to bit lines. , A plurality of dummy cell transistors which are set so as to show different values among the plurality of transconductances and to which a predetermined gate voltage is applied at the time of data reading, and any one of the dummy cell transistors. Transistors are connected, and each dummy cell transistor connected when reading data For all combinations of a plurality of dummy bit lines that generate potentials according to the star and at least two dummy bit lines whose mutual conductance setting values are adjacent to each other, for each combination, at least two bit lines and at least two dummy bit lines are used. A dummy bit line is inputted and a comparison circuit for outputting a comparison result is provided, whereby the above object is achieved.

[0012]

When one of the memory cell transistors is selected and a predetermined gate voltage is applied at the time of reading data, the bit line that has been precharged to a constant potential becomes
The power supply is discharged to or charged from the power supply via the selected memory cell transistor. However, since the magnitude of the discharge current or the charge current through the memory cell transistor differs depending on the preset value of the transconductance of the memory cell transistor, the change of the potential of the bit line with time also depends on this setting. There will be differences accordingly.

Further, since a predetermined gate voltage is applied to all the dummy cell transistors at the time of data reading, the dummy cells to which the potentials of the dummy bit lines which have been precharged to a constant potential are respectively connected, as described above. • It shows different changes over time depending on the transistor settings. Then, the dummy bit line connected to the dummy cell transistor having the same setting as the selected memory cell transistor shows almost the same potential change as the bit line.

The comparison circuit compares the potential of each dummy bit line with the potential of the bit line. However, this is because the set values of transconductance are adjacent to each other.
For all combinations of the dummy bit lines of one book, the potentials of the two dummy bit lines and the potentials of the bit lines in each combination are compared. Moreover, in each combination, only the comparison result between the potential of the dummy bit line having the larger potential difference from the potential of the bit line and the potential of this bit line is output.

Then, when the setting of the selected memory cell transistor is not one of the values at both ends of the plurality of transconductances, the dummy cell of the same setting is set.
The comparison results of the two combinations in which the potentials of the dummy bit lines connected to the transistors are compared are opposite to each other. Then, for other combinations, the potentials of both dummy bit lines are either higher or lower than the potentials of the bit lines, and the comparison result is output accordingly. Also, if the selected memory cell transistor settings are the values at both ends of multiple transconductances, the combination of the dummy bit line potential to which the dummy cell transistors with the same settings are connected is compared. Is only one set, and the comparison results for this combination match the comparison results for all other combinations.

Therefore, when all the comparison results in each combination of the comparison circuits do not match, the selected memory cell transistor is connected to one dummy bit line which is a common comparison target among the combinations having different comparison results. It can be judged that the same setting as the dummy cell transistor to be connected is made. Further, when the comparison results of all the combinations of the comparison circuits match, it is possible to determine that the set value of the selected memory cell transistor is one of the values at both ends according to the comparison result.
Moreover, the margin at the time of these comparisons has a width of at least the minimum set pitch when the transconductance is set to a plurality of values.

As a result, according to the semiconductor memory device of the present invention, the output potential of the selected memory cell transistor is compared with the output potential of the dummy cell transistor, and
Since the comparison with the output potential of the dummy cell transistor having the same setting can be ignored, the comparison margin can be increased and stable reading can be performed.

Since a normal semiconductor memory device is provided with a plurality of bit lines for connecting the above-mentioned large number of memory cell transistors, only one of the bit lines is used as one data line by the selection circuit when data is read. The potential of the data line is connected to the potential of the selected bit line for comparison. Further, since the bit line and the dummy bit line are normally connected to the ground power source via the memory cell transistor or the dummy cell transistor, the precharged potential is lowered by the discharge.

[0019]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 shows an embodiment of the present invention. This embodiment is a mask ROM that stores ternary information (1.5 bits).
Is. The memory cell 1 connects the bit line B1 to the memory cell
It is configured by a circuit grounded through the transistor Q11. This memory cell transistor Q11 has a low threshold value Vth1 in accordance with ternary information to be stored in advance.
(About 0.5V), intermediate threshold Vth2 (about 2.5V)
Alternatively, the threshold voltage Vth3 is set higher than the power supply voltage VCC level. If the threshold to be set is different, the transconductance that shows the ratio of the drain current to the gate voltage will be different accordingly. Therefore, even if the same gate voltage is applied, the magnitude of the current flowing between the drain and the source will differ. Occurs. Memory cell / transistor Q
The gate of 11 is connected to the word line WL1. The bit line B1 is connected to the data line D via the column selection circuit 2. The column selection circuit 2 includes an NMOS transistor Q1 inserted between the bit line B1 and the data line D.
And is turned on when the CSel1 signal for selecting the bit line B1 is activated. In addition, a larger number of memory cells are actually connected to the bit line B1, and the gates of the memory cell transistors of each memory cell are connected to different word lines. Further, in reality, a large number of such bit lines are also provided, and the column selection circuit connects only one of the bit lines to the data line D based on the column address.

A charging circuit 3 and a load circuit 4 are provided on the data line D.
And are connected. The charging circuit 3 reads C at the time of reading.
This is a circuit for precharging the bit line B1 to the V0 potential when the P signal is activated. The data line D is
It is connected to one input of the first comparison circuit 5 and the second comparison circuit 6, respectively. The load circuit 4 is a circuit for setting the load of the data line D.

In this embodiment, three dummy bit lines BD
1, BD2, BD3 are provided, and the dummy cells 7, respectively
8 and 9 are connected. The dummy cells 7 to 9 have dummy bit lines BD1 to BD3 connected to the dummy cell transistor QD1.
.About.QD3, each of which is constituted by a circuit grounded. The dummy cell transistor QD1 has a threshold voltage V
The dummy cell transistor QD2 is an NMOS transistor having the same characteristics as the memory cell transistor set to th1 and the dummy cell transistor QD2 is set to the threshold voltage Vth2.
It is an NMOS transistor having the same characteristics as the transistor, and the dummy cell transistor QD3 has a threshold voltage Vth3.
N with the same characteristics as the memory cell transistor set to
It is a MOS transistor. The gates of these dummy cell transistors QD1 to QD3 are also connected to the word line WL1.
It is connected to the. In addition, each dummy bit line BD1 to BD3
In reality, a larger number of dummy cells are connected, and the gates of the dummy cell transistors of each dummy cell are connected to different word lines. The charging circuit 3 and the load circuit 4 are connected to the dummy bit lines BD1 to BD3, respectively. In addition, dummy bit lines BD1 and B
D2 is connected to the other input of the first comparison circuit 5, and is connected to the load circuit and the dummy cell transistor QD.
1. Reference voltage VREF1 and reference voltage VR generated by QD2
It is designed to input EF2. Further, the dummy bit lines BD2 and BD3 are respectively connected to the other inputs of the second comparing circuit 6 so that the reference voltage VREF2 and the reference voltage VREF3 generated by the load circuit and the dummy cell transistors QD2 and QD3 are inputted. Has become. It should be noted that these dummy bit lines BD1 to BD3 are always connected to the first comparison circuit 5 and the second comparison circuit 6 by NMOS transistors Q2 to Q4 which are always on regardless of the column address.

In the first comparison circuit 5, a PMOS transistor QC1 and a PMOS transistor QC2 as one input transistor are connected in parallel, and a PMOS transistor QC3 and a PMO as another input transistor are connected.
It is composed of a differential amplifier circuit in which the S transistor QC4 is connected in parallel. The data line D is connected to the PMOS transistor Q that constitutes one input transistor.
The dummy bit lines BD1 and BD2 connected to the gates of C1 and QC2, respectively, constitute the other input transistor PM.
The gates of the OS transistors QC3 and QC4 are respectively connected. In addition, P that constitutes one of the input transistors
The comparison result SA1 is output from the drains of the MOS transistors QC1 and QC2.

In the second comparison circuit 6, a PMOS transistor QC5 and a PMOS transistor QC6 as one input transistor are connected in parallel, and a PMOS transistor QC7 and a PMO as another input transistor are connected.
It is composed of a differential amplifier circuit in which the S transistor QC8 is connected in parallel. The data line D is connected to the PMOS transistor Q that constitutes one input transistor.
Dummy bit lines BD1 and BD2 connected to the gates of C5 and QC6, respectively, constitute the other input transistor PM.
The gates of the OS transistors QC7 and QC8 are respectively connected. In addition, P that constitutes one of the input transistors
The comparison result SA2 is output from the drains of the MOS transistors QC5 and QC6.

The first comparison circuit 5 and the second comparison circuit 6 perform the amplification operation only when the CE (chip enable) bar signal is active.

The operation of the read circuit having the above configuration will be described.

Here, the case of reading data from the memory cell 1 will be described. First, the CSel1 signal is activated based on the column address, the column selection circuit 2 connects the bit line B1 to the data line D, and the CP signal is activated so that the charging circuit 3 activates the data line D and the bit line. Precharge B1 to V0 potential. Further, the word line WL1 is selected based on the row address, the power supply voltage VCC level voltage is applied to the gate of the memory cell transistor Q11 of the memory cell 1, and the dummy cell transistors QD1 of the dummy cells 7, 8 and 9 are also applied.
A voltage of the power supply voltage VCC level is also applied to the gates of QD3.

When the CP signal is returned to the inactive state and the charging circuit 3 is stopped in the above-mentioned state, the dummy bit lines BD1 to BD1.
The potential of D3 changes according to the threshold values of the dummy cell transistors QD1 to QD3 in the dummy cells 7 to 9. That is, since the dummy cell transistor QD1 is set to the threshold value Vth1, the dummy cell transistor QD1 is turned on by the application of the gate voltage at the power supply voltage VCC level, and the large mutual conductance causes a large discharge current to flow. Therefore, the potential of the dummy bit line BD1, that is, the reference voltage VREF1
Rapidly drops from the V0 potential as shown in FIG.
The dummy cell transistor QD2 has a threshold voltage Vth.
Since it is set to 2, it is turned on by applying a gate voltage of the power supply voltage Vcc level, but since the mutual conductance does not increase so much, the discharge current also reaches the threshold value V.
Less than in the case of th1. Therefore, the dummy bit line BD
The second potential, that is, the reference voltage VREF2, drops relatively slowly from the V0 potential. Furthermore, the dummy cell transistor Q
Since D3 is set to the threshold value Vth3, it remains in the OFF state even when the gate voltage of the power supply voltage VCC level is applied, and the mutual conductance becomes extremely small, so that the discharge current hardly flows. Therefore, the dummy bit line B
The potential of D3, that is, the reference voltage VREF3 remains V0 potential.

The potential of the bit line B1 also changes according to the setting of the threshold value of the memory cell transistor Q11 in the memory cell 1. That is, for example, when the memory cell transistor Q11 is set to the threshold value Vth1, the potential of the bit line B1 rapidly drops almost like the reference voltage VREF1 of the dummy bit line BD1. When the memory cell transistor Q11 is set to the threshold value Vth2, the reference voltage VREF2 of the dummy bit line BD2 is set.
Almost similarly, the potential of the bit line B1 drops relatively gently. Further, when the memory cell transistor Q11 is set to the threshold value Vth3, the potential of the bit line B1 remains the V0 potential, almost like the reference voltage VREF3 of the dummy bit line BD3.

In this way, the potential of the bit line B1 which changes according to the setting of the threshold value of the memory cell transistor Q11 is input to the first comparison circuit 5 via the data line D, and the potential of the dummy bit line BD1. It is compared with the reference voltage VREF1 and also with the reference voltage VREF2 of the dummy bit line BD2. If the memory cell transistor Q11 is set to the threshold value Vth1, the potential of the bit line B1 changes almost in the same manner as the reference voltage VREF1.
The drive currents of the transistor QC1 and the PMOS transistor QC3 are almost the same. However, since the reference voltage VREF2 is always at a higher potential than the bit line B1, the PMOS transistor QC2 has a larger drive current than the PMOS transistor QC4. Therefore, in this case, the first comparison circuit 5
The comparison result SA1 becomes H level. Further, the memory cell transistor Q11 has a threshold value Vth2 or a threshold value Vth3.
If set to, the comparison results SA1 of the first comparison circuit 5 are both at the L level.

The potential of the bit line B1 is also input to the second comparison circuit 6 via the data line D, compared with the reference voltage VREF2 of the dummy bit line BD2, and the dummy bit line B1.
It is also compared with the reference voltage VREF3 of D3. Here, if the memory cell transistor Q11 is set to the threshold value Vth1, the potential of the bit line B1 changes almost in the same manner as the reference voltage VREF1, and therefore the reference voltage VREF2 and the reference voltage VRE.
The potential of F3 is always higher, and the comparison result SA2 of the first comparison circuit 5 becomes H level. When the memory cell transistor Q11 is set to the threshold value Vth2 or the threshold value Vth3, the comparison result SA1 of the first comparison circuit 5 becomes H level and L level, respectively.

Therefore, the comparison results SA1 and SA2 of the first comparison circuit 5 and the second comparison circuit 6 with respect to the set threshold value of the memory cell transistor Q11 are as shown in Table 1 and are selected based on this. It is possible to determine the stored information of the memory cell 1 that has been stored.

[0033]

[Table 1]

As a result, according to this embodiment, for example, the memory cell transistor Q11 of the memory cell 1 has the threshold voltage V.
If it is set to th2, in the first comparison circuit 5,
The second comparison circuit 6 outputs the comparison result SA1 only by comparing the reference voltage VREF2 with the reference voltage VREF2.
However, the reference voltage VREF2 is ignored and the comparison result SA2 is output only by comparison with the reference voltage VREF3. Therefore, the potential difference in these comparisons has a width equal to or larger than the minimum set pitch of at least three types of threshold values,
The comparison margin can be doubled compared to the conventional one.

[0035]

As is apparent from the above description, according to the semiconductor memory device of the present invention, it is possible to increase the comparison margin of the multi-valued information stored in the memory cell and perform stable reading. become.

[Brief description of drawings]

FIG. 1 is a block diagram of a read circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing changes in reference voltage in the example.

FIG. 3 is a block diagram of a read circuit in a conventional semiconductor memory device.

FIG. 4 is a time chart showing changes in the potential of a bit line in the conventional example.

[Explanation of symbols]

 5 First Comparison Circuit 6 Second Comparison Circuit B1 Bit Line Q11 Memory Cell Transistor QD1 to QD3 Dummy Cell Transistor BD1 to BD3 Dummy Bit Line

Claims (1)

[Claims] 1. A bit line which is precharged to a constant potential at the time of reading data is set so as to indicate any one of a plurality of predetermined transconductances of three values or more, and at the time of reading data. What is claimed is: 1. A semiconductor memory device having a memory cell array in which a plurality of memory cell transistors to which a predetermined gate voltage is applied are connected to a bit line and which are different from each other among the plurality of transconductances. Of the dummy cell transistors to which a predetermined gate voltage is applied at the time of data reading, and one of the dummy cell transistors is connected to each of the dummy cell transistors. Multiple dummy cells that generate potentials according to the dummy cell transistors And a bit line, for all combinations of at least two dummy bit lines set value of transconductance adjacent,
A semiconductor memory device comprising, for each combination, a bit line and at least two dummy bit lines as inputs, and a comparator circuit for respectively outputting a comparison result.