JPH05217300A - System for transmitting video signal - Google Patents

Abstract

PURPOSE:To increase the amount of data to be restored in the case of occurring an error or a variable-speed reproduction. CONSTITUTION:A synchronizing area S is provided with a synchronizing pattern, an area Q# which shows the quantizer used in a transformation, an ADR 1 which shows the position of the picture of a first block and the data of an ADR 2 which shows a first cut position in the high frequency signals that follow a first important word in terms of a fixed length. Moreover, a DC level signal DC[n] after a discrete cosine transformation(DCT) is provided in a fixed length. Furthermore, a fixed length HV[n] is provided showing a quantized object region in a DCT block at a fixed location and signals AC0[n], AC1[n] and AC2[n], which are equivalent to the low frequency levels after the DCT of the corresponding blocks, are provided with variable lengths. In the area between the end of the signal AC2[n] and the beginning of a next HV[n+1], signals corresponding to the higher frequency levels followed signal AC3 after DCT are orderly and closely arranged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal transmission system used for digitizing a video signal for recording and reproduction.

[0002]

2. Description of the Related Art For example, when a video signal is digitized and recorded and reproduced, a huge amount of data is compressed as much as possible. In that case, conventionally, a video signal transmission method has been used in which a video signal is divided into blocks, discrete cosine transform (DCT) is performed, and the converted signals are variable-length coded and recorded and reproduced.

That is, in FIG. 5, the video signal is divided into blocks, for example, every 8 × 8 64 pixels as shown in A of FIG. 5, and DCT is performed on the blocked signal. As a result, the signal DC having the DC level as shown by B in the figure and the signals AC0, AC1 ... AC62 corresponding to the levels of the respective frequencies are sequentially extracted from the low frequency side.
Here, the signals AC0 to AC62 have a level of a signal corresponding to a high frequency after a certain frequency is "0" or a value close to it, which can be ignored. Therefore, a certain amount of data can be compressed by deleting a signal corresponding to a high frequency after that frequency.

However, at this level, the amount of data is still too large. Therefore, the DCT-processed signal is further subjected to variable-length coding (Huffman coding) for converting it into data having different bit lengths according to the probability of occurrence of the signal. As a result, for example, it is possible to compress the data amount that can be recorded and reproduced by a consumer digital VTR, for example. However, in the case of recording / reproducing (transmitting) such a variable-length coded signal, if an error occurs in the variable-length coded signal, all the subsequent data cannot be restored.

Therefore, as shown in FIG. 6, for a plurality of blocks constituting one synchronization period, for example, a signal DC of these DC levels and a signal A corresponding to the level of each frequency are provided.
Collect C0, AC1 ... Then, the signal DC has a fixed length, and the signals DC, AC0,
A method of recording / reproducing (transmitting) in the order of AC1 ... has been proposed. Note that S is a synchronization area and P is a parity area. According to this, even if an error occurs on the way, the DC level signal DC of each block and the low-frequency signal before the error can be restored, and thereby an image can be reproduced to some extent.

However, even with this method, all the data after the error within the synchronization period cannot be restored, and there is a possibility that a considerable amount of data cannot be restored depending on the position where the error occurs. Further, when variable speed reproduction is performed, the data that can be restored is limited only when the data is reproduced from the position of the DC signal DC, so that the amount of data to be restored is extremely small and a good image cannot be obtained. The present invention has been made in view of these points.

[0007]

The problem to be solved is that a considerable amount of data cannot be restored depending on the position of the error occurrence. Further, when variable speed reproduction is performed, the amount of data to be restored becomes small and a good image cannot be obtained.

[0008]

DISCLOSURE OF THE INVENTION The present invention is a video signal transmission system in which a video signal is subjected to discrete cosine transform, the signal after the discrete cosine transform is quantized, and data is compressed and transmitted. The signals AC0, AC1 and AC2 corresponding to the low frequency level in the signal are placed from the position where the synchronization period is defined as an important word, and the signal AC3 ...
It is a video signal transmission method characterized in that the transmission signals are arranged in sequence.

[0009]

According to this, since the signal corresponding to the low frequency level is arranged from the position where the synchronization period is determined, the data arranged from the determined position can be restored even after the occurrence of the error. It is possible to obtain a good image.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the form of a signal during one synchronization period, and the left side of this figure is the signal start side. A synchronization area S is provided at the beginning of this signal. In this synchronization area S, a synchronization pattern consisting of a predetermined bit array, Q # indicating the quantizer used for conversion, ADR1 indicating the position on the screen of the first block constituting the synchronization period, first described later. AD indicating the position of the first break of the high-frequency signal following the key word of the, the block to which it belongs, and its frequency band
Data of R2 is provided with a fixed length.

Following this synchronization area S, a synchronization period is set up.
Directly after the discrete cosine transform (DCT) of each block
Flow level signal DC_[0], DC_[1], DC_[2], DC
_[3]... (_[n]Is a fixed number.
Be done. A fixed position after the area of this signal DC (Fig.
() Shows a fixed length indicating the range to be quantized in the DCT block.
HV_[0], HV_[1], HV_[2], HV_[3]... is set
And each of these HVs _[n]For each corresponding block
Signal AC0 corresponding to the low frequency level after DCT _[n],
AC1_[n], AC2_[n]Is provided with a variable length.

Further, in the area (shown by hatching) from the end of the signal AC2 _[n] to the start of the next HV _{[n + 1]} , the higher frequency level after the signal AC3 after DCT is applied. Corresponding signals are arranged in a so-called right-justified sequence. That is, the signals after the signal AC3 are targeted for, for example, all blocks constituting one field,
These signals are provided for each block in order from the low frequency side. Further, data indicating the position of the first break (shown by a thick line) of the high-frequency signal following this first area HV _[0] , the block to which it belongs, and its frequency band are formed, and this data has a fixed length as the above ADR2. It is provided in the synchronization area S.

In this way, the signals DC and AC after DCT
0 to AC2, AC3 ... Are provided in respective areas of the synchronization period. Further, a parity area P is provided after these signal areas. A transmission signal is formed in such a form, and this signal is recorded and reproduced (transmitted).

Further, FIG. 2 is a block diagram of a circuit device for forming a transmission signal of such a form. In this figure, 1 is an input terminal to which a video signal is supplied. The signal from the input terminal 1 is supplied to the memory 2, the signal from the memory 2 is supplied to the blocking circuit 3, and the above-described block formation is performed for each 64 × 8 × 8 pixels, for example.
The signal from the blocking circuit 3 is supplied to the DCT circuit 4.

The signal from the DCT circuit 4 is the switch 1
0, and only the AC component is supplied to the buffer memory 5. Further, the signals from the buffer memory 5 are supplied to the quantizers 61, 62 ... 6m having different levels, and the signals from the quantizers 61, 62 ... 6m are supplied to the selector 7. Further, the signal from the DCT circuit 4 is supplied to the data amount estimating circuit 8, and in this estimating circuit 8, the quantizers 61, 62, ... 6m for which the total amount of quantized data for one field becomes a predetermined value, for example. Selected.
The selector 7 is switched so that the selected quantizers 61, 62 ... 6m are selected and variable length coding (V
LC) circuit 11.

Further, 12 is a synchronizing pattern generating circuit having a predetermined bit arrangement. Reference numeral 13 is a Q # memory indicating the quantizers 61, 62 ... 6m selected by the estimation circuit 8. Reference numeral 14 denotes a counter which is reset by, for example, a vertical synchronizing signal and is counted every period of the number of pixels forming the above block, and the count value indicates the position on the screen of the first block forming the synchronizing period. AD
It is supplied to the memory 15 of R1.

Reference numeral 16 is a memory of ADR2 data indicating the position of the first break of a high-frequency signal following the first area HV, the block to which it belongs, and its frequency band. Reference numeral 17 is a memory of the signal DC from the DCT circuit 4 separated by the switch 10. A detection circuit 18 is supplied with the signal passed through the detection circuit 9 and detects the above-described HV value. The HV value is supplied to the memory 19.

Further, of the signals from the VLC circuit 11, signals corresponding to the signals AC0 to AC2 are supplied to the memory 20, and signals corresponding to the signals AC3 ... Are supplied to the memory 21. Here, the memory 20 has addresses corresponding to the number of blocks described above, and the capacity of each address is the signal AC0.
~ AC2 maximum bit length is assumed to be included. The memory 21 is a so-called first-in first-out type memory.

Then, these generation circuit 12 and memory 1
The signals from 3, 15, 16, 17, 19, 20, and 21 are selected by the selector 22. The generation circuit 12 and the memories 13, 15, 16, 17, 19, 20 are controlled by addresses generated by the memory control circuit 23. Further, the memory 21 is read out in the order in which the supplied signals are supplied. This forms the data portion of the transmission signal described above.

Further, the signal from the selector 22 is supplied to the adder 24 and the parity arithmetic circuit 25. Then, the calculated horizontal parity P _H is added to the data portion to form the above-mentioned transmission signal. Further, the transmission signal is supplied to the adder 26 and the parity arithmetic circuit 27. As a result, for example, a product code vertical parity P _V as shown in FIG. 3 is formed, added to the transmission signal, and taken out to the output terminal 28.

Therefore, in this video signal transmission system,
When the transmitted (recorded) signal is restored (reproduced), the error occurrence position is detected using the parities P _H and P _V, and error correction such as complementation is performed based on the detection result.

In this case, when the error occurrence position is in the area of ADR1 to DC _[x] , these signals are fixed length data, so that the error does not propagate,
Other signals can be restored. If an error occurs in the ADR2 area, the data such as the position of the first break (shown by the thick line) of the high-frequency signal following the first HV _[0] cannot be restored, but the signal of the previous synchronization period If is restored normally, no problem will occur.

On the other hand, the error occurrence position is, for example, as shown in FIG.
In the case of HV _[0] as shown in A of FIG. 7, the important word data of HV _{[0] to} AC2 _[0] cannot be restored as shown in B of FIG. However, if there is no error in ADR2, HV _[0]
It is possible to recover data other than the low-frequency signal that follows.
Further, the error occurrence position is, for example, as shown in C of FIG.
_In the case of the high-frequency signal area following _[0] , D in the figure
As shown in, the subsequent high frequency signal data cannot be restored. However, it is possible to recover the data of the low frequency signal following each HV.

Thus, according to the above-mentioned method, since the signal corresponding to the low frequency level is arranged from the position where the synchronization period is determined, the data HV _{[ n] to} AC2 _[n] can be restored and a good image can be obtained.

Further, according to the above method, it is possible to restore the data of the low-frequency signal following each HV even when variable speed reproduction is performed, and it is possible to obtain a good image by increasing the amount of restored data. it can.

In the above example, the data of the first break position (indicated by a thick line) of the high-frequency signal following the first HV _[0] is provided as ADR2.
Data of the first break position of the high-frequency signal following V _{[n ]} is provided as ADR3, ADR4, .... This makes it possible to more restore the high-frequency signal data when an error occurs in the high-frequency signal area.

By using the data HV _{[n] to} AC2 _[n] as important words and adding an error correction code having a high correction rate to this portion, the restoration rate of these data can be increased. Further, along with HV _{[n] to} AC2 _[n] , AC3
The data of _{[n] to} AC7 _[n] may also be arranged from a predetermined position as an important word.

Furthermore, instead of arranging DC immediately after the synchronization area, DC may be arranged immediately after each HV. Even when transmitting 64 DC-AC63 coefficients without using HV data, for example, DC-AC3 is used as an important word,
It may be arranged as described above.

[0029]

According to the present invention, since the signal corresponding to the low frequency level is arranged from the position where the synchronization period is defined, the data arranged from the defined position is restored even after the occurrence of the error. It is possible to obtain a good image.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an example of a video signal transmission system according to the present invention.

FIG. 2 is a block diagram of an example of an apparatus for realizing it.

FIG. 3 is a diagram for explaining the explanation.

FIG. 4 is a diagram for explaining the explanation.

FIG. 5 is a diagram for explaining discrete cosine transform.

FIG. 6 is a diagram for explaining a conventional video signal transmission system.

[Explanation of symbols]

S synchronization area Q # area indicating quantizer used for conversion ADR1 area indicating on-screen position of first block constituting synchronization period ADR2 position of first break of high frequency signal following first HV and its Area DC indicating the block to which it belongs and its frequency band DC _[n] DC level signal after discrete cosine transform (DCT) of each block constituting the synchronization period HV _[n] Area indicating the range of quantization in the DCT block AC0 _{[ n]} , AC1 _[n] , AC2 _[n] Signal corresponding to low frequency level after DCT of corresponding block AC3 Signal corresponding to higher frequency level after DCT P Parity area ↓ _Specified position

Claims (1)

[Claims] 1. A low-frequency level in the signal after the discrete cosine conversion, wherein the signal is subjected to the discrete cosine transform, the signal after the discrete cosine transform is quantized, and the data is compressed and transmitted. A video signal transmission characterized in that a signal corresponding to is placed as a key word from a position where a synchronization period is determined, and a signal corresponding to a high frequency level is sequentially arranged in the remaining area. method.