JPH05216777A - High-speed direct memory access address parity generator - Google Patents

Abstract

PURPOSE: To provide an address parity generator in which the address parity of a memory bus can be generated at a high speed by the shortest transmission delay, and the applicable range of diagnosis for the error protection of an overall system can be improved with the least logic addition. CONSTITUTION: A parity generator 20 is moved to an inside bus side, the applicable range of the diagnosis is validated to both an outside bus signal and an inside bus signal. when an address register is loaded, the parity value is latched, and a DMA parity bit is updated by a state machine 26 which predicts the parity value based on the value of a present DMA counter 10 and the next address parity value.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to electronic data processing systems, and more particularly to a high speed direct memory access parity generator with minimum propagation delay and maximum parity protection range.

[0002]

2. Description of the Prior Art In a system for transferring data between a host device and a target device, direct memory access (DMA) for transferring data from the host to the target device.
A buffer interface controller with a device is used. Such data transfer systems typically include a buffer memory having matrix storage locations for storing digital data. The data transfer between the host device and the buffer memory is asynchronous with the data transfer between the buffer memory and the external peripheral device.

The first host direct memory access device is
Access a set of defined discontinuous buffer memory storage locations to store data transferred from the host device according to a predetermined buffer format. There is storage for error code characters in the direct memory access device to ensure that no errors occur in the transfer of data.

An error in the address used to access the memory may retrieve the incorrect data from the memory. Also, the error detection logic is an error of the memory itself,
Or it may not detect an error in the address line of the memory. Parity checking is used to prevent erroneous memory address locations. The parity check circuit counts the number of logical 1 bits in a word and adds 1 or 0 parity bits to the count to bring it to the odd or even count selected for the error detection system.

Adding bit 1 is odd to even,
Or, changing the parity from even to odd and adding bit 0 is to keep the parity unchanged.
The parity function is the exclusive OR function of the data word from the point of view of the logic circuit, and the parity check of the bits is usually a tree or tree structure of binary exclusive OR circuits. If the parity circuit adds one bit to each word to give odd parity before storing the word in memory,
The circuit is called an odd parity circuit.

In an odd parity system, all valid words are words of odd parity and all words with even parity are invalid. Therefore, a single error is by increasing or decreasing the number of bits 1,
You have changed the word parity. If two errors occur in the same word, the word retains its original parity and the error is undetectable.

[0007]

Conventionally, each storage location is provided with a parity bit position. The generation of a parity bit for a direct memory access device address requires a propagation delay because the address bus is incremented. When address parity occurs, direct memory
To speed up access, it is desirable to reduce the propagation delay, which is typically 17-25 nanoseconds.

Therefore, it is an object of the present invention to provide a direct memory
Providing parity generation that does not introduce additional propagation delay cycles on the access bus.

It is a further object of the present invention to provide a high speed direct memory access address parity generator that is independent of the delay time inherent in the technology.

It is a further object of the present invention to provide a parity generator between the direct memory access bus and the internal bus to provide error protection for both the internal and direct memory access buses. ..

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention uses the function of a state machine to minimize and minimize the propagation delay of the parity bit generated for an incremented address bus. To provide a high speed direct memory access address parity generator with improved diagnostic coverage overall. The high speed direct memory access address parity generator moves the parity generator to the internal bus and latches its parity value when the address register is loaded, and the current direct memory access counter value and the next The object was achieved by updating the direct memory access parity bit signal by a state machine that predicts the parity value based on the state of the value.

This eliminates the propagation delay of the direct memory access bus so that the parity bits are
It is possible to exhibit the same register propagation delay as the access address bus itself. Therefore, the cycle time of the direct memory access bus does not increase because the parity output is maintained as in the typical direct memory access address parity generation analysis solution. Parity generator has internal bus and direct memory access
Performs internal parity check on both buses.

[0013]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows a typical conventional direct memory access address parity generator, which has four internal bus lines 12-15, a load (+ LOAD), a count (+ COUNT), and a clock (+ CLOCK) 16, respectively. 1
A 4-bit loadable counter 10 having 7, 18 cycle inputs. The 4-bit loadable counter 10 has a technology-dependent cycle time of X nanoseconds. The output of the 4-bit loadable counter 10 is the input to the parity generator 20, which may be a Texas Instruments chip 74F280 or equivalent.

Four address signal lines 22, to the data memory via the counter 10 which can be loaded from the bus,
23, 24, 25 are output. In addition, the output of parity generator 20 provides a direct memory access bus odd parity output signal via signal line 27 '.
The parity generator 20 completes its processing 17-2
It takes anywhere from 5 nanoseconds, which slows the direct memory access time for each address request in memory.

The parity generator 20 shown in FIG. 2 is arranged in front of the 4-bit loadable counter 10 and is connected to the internal bus. A 4-bit loadable counter 10 is located downstream of the internal bus and receives as input the load 16, count 17, and clock 18 input pulses. 4-bit loadable counter 1
0 is 4 more direct memory access addresses
Combinatorial logic 2 controlling the input of each of the bus bits A3-A0 and the output of the toggle (+ TOGGLE) signal 29 to the direct memory access parity output state machine 26.
Including 1. Combinatorial logic 21 implements the logic shown in FIG.

The present embodiment, using a 4-bit bus as an example, illustrates an analytical solution for a direct memory access address parity generator according to the present invention. However, the concept of a high speed direct memory access address parity generator and its logical equations can easily be extended to n bits in a manner similar to an n bit counter.

The direct memory access parity output state machine 26 outputs a direct memory access odd parity output (bit) signal 30. This direct memory access odd parity output (bit) signal 30 has four direct memory access address bus bits A3-.
Supply odd parity for A0. Direct memory
The access odd parity output (bit) signal 30 provides a direct memory access odd parity generator (Texas Instruments integrated circuit 74 when the initial address is loaded into the 4-bit loadable counter 10.
An initial odd parity value (such as F280) is loaded.

The initial address is the load active,
When the count is inactive it is loaded into the 4-bit loadable counter 10. This bit is updated in the direct memory access parity output state machine 26 when the direct memory access address bus bits A3-A0 are incremented. This increment is a load (+ LO
AD) is inactive and the count (+ COUNT) is active. This update function consists of either maintaining the current state of the direct memory access bus odd parity output (ie, toggle inactive) or inverting the current state (ie, toggle active).

The DMA parity output state machine 26 includes a multiplexer 28 which receives a parity out signal 27 and an input toggle (+ TOGGLE) signal 29 in either inverted or non-inverted form.

The state table for the direct memory access parity output state machine is shown in FIG. All signals are shown with activity "high" (ie logic "1") and the symbol X means indifferent value. The logical equation for the toggle (+ TOGGLE) signal is created from FIG. This active "high" signal is inactive whenever + LOAD is 1 (load mode), and is also inactive when + LOAD is 0 and + COUNT is 0 (hold mode). + LOAD is 0, +
When COUNT is 1 (count and update parity mode), + TOGGLE is active depending on the state of 4 address bits, as shown in Figure 3 and the Carnot diagram below (Figure 4). .. Note that the + TOGLE signal is a combined (unregistered) signal.

Detailed logic equations for the state machine logic table are derived from the Carnot diagram shown in FIG. The output of the toggle signal of FIG. 4 is equal to the inverse of the load signal AND'ed with respect to the count AND'ed with the quantity [A0 + / A2 ^* A1]. The symbol "/" is a logical knot (NO
T) state, the symbol "*" is a logical AND state, and the symbol "+" is a logical OR state. To obtain the direct memory access bus odd parity output signal 30, the truth table shown in FIG. 5 is used. The logical equation for the parity out signal 27 is created from FIG.

This odd parity output signal is a registered output whose inputs are multiplexed based on the state and mode of the + TOGGLE signal. When + LOAD is 1 and + COUNT is 0 (load mode), the initial parity from the 74F280 parity generator is clocked out on the parity out signal. + LOAD is 0 and + COUNT is 0
, (Hold mode), the parity out signal is multiplexed onto the input of the direct memory access parity output state machine 26 to hold the initial parity and to the first transfer of the 16 word direct memory access operation. used.

When + LOAD is 0 and + COUNT is 1 (count and update parity mode), the parity
The out signal depends on the state of the + TOGGLE signal. ＋ TO
When GGLE is 1, the current state of the parity out signal is inverted and multiplexed onto the input of the direct memory access parity output state machine 26. When + TOGGLE is 0, the current state of the parity out signal is unchanged and multiplexed onto its input.

Thus, the equation for the odd parity output signal for the incoming parity out signal is: Parity output = Load ^* / Count ^* Parity in + + / Load ^* / Count ^* Parity out + / Load ^* / Count ^* toggle ^* / Parity out + / Load ^* Count ^* / Toggle ^* Parity out

Therefore, the logic for the parity out latch is as shown in FIG. FIG. 6 is a hardware implementation of the logic of the state table of FIG.

The parity prediction function essentially looks at the current counter state and moves to the next state (ie, current state + 1).
Determines whether it contains the same parity as the current state, and thus updates the toggle signal. By moving the parity generator upstream from the 4-bit loadable counter 10 and adding the parity output state machine,
Direct memory access address parity could be generated with the shortest propagation delay, and minimal additional logic could improve diagnostic coverage for error protection of the entire system.

Although one embodiment of the present invention has been described above, it is obvious that the present invention is not limited to this and can be changed and modified according to the idea and scope of the present invention.

[0028]

As described above, according to the present invention, the address parity of the memory bus can be generated at a high speed with the shortest propagation delay and the error of the whole system can be reduced by adding the minimum logic. The scope of diagnosis for protection could be improved.

[Brief description of drawings]

FIG. 1 is a schematic explanatory diagram of a conventional typical direct memory access address parity generator.

FIG. 2 is a schematic diagram of a high speed direct memory access address parity generator according to an embodiment of the present invention.

FIG. 3 is a diagram of the state machine's I / O table providing the correct parity out signal for the direct memory access bus.

FIG. 4 is a logical diagram for deriving a direct memory access parity algorithm.

Figure 5: Truth table diagram for direct memory access bus odd parity output

FIG. 6 illustrates an implementation of state machine logic hardware.

[Explanation of symbols]

10 4-bit loadable counter 12-15 Internal bus line 16 Load signal 17 Count signal 18 Clock signal 20 Parity generator 21 Combinatorial logic 22-25 Direct memory access address bus bit 26 Direct memory access parity Output State Machine 27 Parity Out Signal 28 Multiplexer 29 Toggle Signal 30 Direct Memory Access Odd Parity Output Signal

Claims (4)

[Claims] 1. A parity generator electrically connected to an internal memory bus for outputting an initial parity value; a data register including a memory address location; and inputting an initial parity value from the parity generator, Current direct memory access address and next memory
A high-speed direct memory characterized by including a state machine for updating the parity value based on the parity value of the address
Access address parity generator. 2. The steps of initializing a state machine with an initial parity value, predicting a next parity value for an incremented memory address based on a logic algorithm, and updating the parity value for the incremented memory address. A method of generating a parity bit for a direct memory access address characterized by: 3. A register for latching a memory address and an initial parity value, a state machine for predicting a parity value of an incremented memory address, and an incremented direct memory access address for updating the parity value. A data processing system having a direct memory access address parity generator comprising update means. 4. The system of claim 3, wherein the state machine uses a combinatorial algorithm to predict the parity value of an incremented memory address.