JPH05216555A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the supply power by providing a changeover switch for switching between the clock generator side and the power reducing circuit side and performing the oscillating operation in an LC oscillating circuit at the time of switching to the power reducing circuit side. CONSTITUTION:When an information processor is used normally, a changeover switch 6 is connected to the A' side, and a switch 7 is in the turning-off state, and the clock signal of a clock generator 9 is supplied to a clock terminal 10. When the changeover switch 6 is switched to the A side and the switch 7 is turned on, an interlocking switch 13 is turned off to stop the power supply to the clock generator 9, and the output from the clock generator 9 to the clock terminal 10 is switched to the output from an LC oscillating circuit 11, and this circuit 11 starts oscillation. A variable reverse voltage is applied to a PN junction diode 8 by this oscillating operation to change the capacitance, and the oscillation frequency is reduced by this change, thereby reducing the power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used to reduce power consumption in information processing. INDUSTRIAL APPLICABILITY The present invention is used in an information processing device such as a notebook computer that needs to reduce power consumption.
The present invention relates to a low power consumption circuit for an information processing device capable of reducing the frequency of a clock supplied to the circuit to reduce power consumption.

[0002]

2. Description of the Related Art Depending on when a battery (battery) is used as a power source for a notebook computer or the like, it is necessary to reduce power consumption in order to prolong the usage time. As a countermeasure for this, a power reduction circuit is used, but the conventional power reduction circuit of this type divides a clock frequency in a digital circuit to select a necessary frequency when the CPU is not processing anything. As a result, the frequency of the clock signal is lowered and supplied to the logic circuit to reduce the power consumption.

[0003]

The low power consumption circuit in the above-mentioned conventional information processing apparatus has a drawback that the circuit is complicated because the clock frequency is usually lowered in several stages.

An object of the present invention is to solve such a problem, and an object thereof is to provide an information processing apparatus capable of supplying a low-frequency clock with a simple circuit configuration to reduce power consumption.

[0005]

According to the present invention, in an information device having a clock generator for generating a constant frequency and supplying it as a basic clock signal, an LC oscillator circuit for generating a frequency lower than the constant frequency, and The basic clock signal is output from the clock generator and the L
A selector switch for selectively switching to the output of the C oscillation circuit,
Means for stopping the operation of the clock generator when the LC oscillating circuit is selected in conjunction with the changeover switch.

It is desirable that the LC oscillating circuit includes a variable capacitance diode in at least a part of the capacitance that determines the frequency, and has a voltage control circuit that changes the bias voltage applied to the variable capacitance diode.

[0007]

In order to improve the performance of the information processing apparatus, it is necessary to increase the processing speed, and to increase the processing speed, it is necessary to increase the clock frequency, which consumes a lot of power. On the other hand, it is necessary to reduce the power consumption as much as possible and prolong the usage time. In order to satisfy these two contradictory requirements, the power consumption is reduced by lowering the clock frequency to reduce the processing speed when the CPU is not processing anything or when the temperature exceeds a predetermined level. However, when the CPU performs processing, it is necessary to increase the clock frequency to increase the processing speed.

Therefore, in the present invention, a changeover switch for switching between the clock generator side and the power reduction circuit side is provided,
When this switch is switched to the low power circuit side,
A current is supplied to the transistor and the transformer of the LC oscillation circuit, and the oscillation operation is performed. This oscillation operation causes PN
A variable reverse voltage is applied to the junction diode to change the electrostatic capacitance, and the oscillation frequency changes with the change.

By lowering the clock frequency to the clock terminal and supplying it in this manner, it is possible to reduce the power supply. The present invention is effective when applied to a portable personal computer.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

In the embodiment of the present invention, the clock generator 9 which generates a constant frequency and supplies it as a basic clock signal.
An LC oscillating circuit 11 for generating a frequency lower than the fixed frequency, a changeover switch 6 for selectively changing the basic clock signal between the output of the clock generator 9 and the output of the LC oscillating circuit 11, and the changeover switch 6. An interlock switch 13 that interlocks to stop the operation of the clock generator 9 when the LC oscillation circuit 11 is selected,
Further, the LC oscillation circuit 11 includes a variable capacitance diode (PN junction diode) 8 in at least a part of the capacitance that determines the frequency, and includes a voltage control circuit 12 that changes the bias voltage applied to the PN junction diode 8. ..

Next, the operation of the embodiment of the present invention thus constructed will be described. FIG. 2 is a diagram showing a temporal change of a potential difference of a power source which is changed by a capacitor in the embodiment of the present invention, FIG. 3 is a diagram showing a voltage-capacitance characteristic of a PN junction diode in the embodiment of the present invention, and FIG. 6 is a diagram showing a clock output waveform in FIG.

Normally, when using the information processing device,
The changeover switch 6 is connected to the A'side, and the switch 7 is OF
In the F state, the clock signal of the clock generator 9 is supplied to the clock terminal 10 and the frequency at that time is Fk.
Is.

The changeover switch 6 is set to the A side, and the changeover switch 7
When the switch is turned on, the interlock switch is turned off, the power supply to the clock generator 9 is stopped, and the output from the clock generator 9 to the clock terminal 10 is switched to the output from the LC oscillation circuit 11, whereby the LC The oscillator circuit 11 starts oscillating.

The oscillation frequency of the circuit is

[0016]

[Equation 1] (L: inductance of the coil, C _A: PN capacitance of the junction diode) is calculated by the initial value of V _A is the voltage characteristics shown in FIG. 2

[0017]

[Outer 1] And the capacitance of the PN junction diode 8 at that time is determined from the characteristics shown in FIG.

[0018]

[Outside 2] Becomes

Therefore, the initial oscillation frequency is

[0020]

[Equation 2] However

[0021]

[Outside 3] Becomes The oscillation frequency after the lapse of time T ₁ second is as shown in FIG.

[0022]

[Outside 4] As shown in FIG.

[0023]

[Outside 5] When

[0024]

[Outside 6] Becomes

Therefore, the oscillation frequency is

[0026]

[Equation 3] And the initial oscillation frequency

[0027]

[Equation 4] Compared with

[0028]

[Outside 7] By

[0029]

[Outside 8] Therefore, the frequency changes with time as shown in FIG. Further, when the clock output from the clock generator 9 is desired, the clock output from the clock generator 9 can be obtained by switching the changeover switch 6 from A to A'and turning off the switch 7.

[0030]

As described above, according to the present invention, a frequency switchable clock is generated with a simple circuit configuration,
There is an effect that power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a time change of a potential difference of a power source which changes according to a capacitor in an embodiment of the present invention.

FIG. 3 is a diagram showing voltage-capacitance characteristics of a PN junction diode according to an embodiment of the present invention.

FIG. 4 is a diagram showing a clock output waveform in the embodiment of the present invention.

[Explanation of symbols]

 1 Transistor 2 Resistance 3 Transformer 4 Power Supply 5 Capacitor 6 Changeover Switch 7 Switch 8 PN Junction Diode 9 Clock Generator 10 Clock Terminal 11 LC Oscillation Circuit 12 Voltage Control Circuit 13 Interlocking Switch

Claims (2)

[Claims] 1. An information device comprising a clock generator which generates a constant frequency and supplies it as a basic clock signal, wherein an LC oscillating circuit which generates a frequency lower than the constant frequency, and the basic clock signal of the clock generator. An output switch and an output of the LC oscillator circuit are selectively switched, and means for interlocking with the switch and stopping the operation of the clock generator when the LC oscillator circuit is selected are provided. Information processing device. 2. The LC oscillating circuit includes a variable-capacitance diode in at least a part of a capacitor that determines a frequency, and a voltage control circuit for changing a bias voltage applied to the variable-capacitance diode is provided. Information processing equipment.