JPH05216465A - Picture display device - Google Patents

Abstract

PURPOSE:To reduce latch steps for adjusting the time for a synthesized parts. CONSTITUTION:In a device for synthesizing plural faces constituted of dual port memories 5-8, since the processing such as the decision of transparent color during one clock cycle read from the dual port memories does not performed at the time of the deciding the transparent colors, pixel data read from the dual port memories are requirerd to be delayed by means of latches 14, 15, 16.... Consequently, the pixel data not requiring the processing such as the decision of transparent colors requirers the latches only to be delayed until the synthesization. By delaying the clock timing read from the dual port memories concerning with the surfaces unneccesary to be processed such as the decision of tarnsparent colors, the delay operation of pixel data by the latches is eliminated. By reducing the number of latches, the area of a substrate is reduced and the generation of heat is surpressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying a plurality of images in an overlapping manner.

[0002]

2. Description of the Related Art The structure of a conventional image display device will be described with reference to FIGS. FIG. 4 is a block diagram showing a conventional image display device, and FIG. 5 is a circuit diagram showing a video composition circuit of the conventional image display device.

In FIG. 4, 1 is a CPU, 3 is a system bus 2 connected to the CPU 1, and is a CRT controller (C) for generating display timing and controlling drawing.
RTC), 5 is a frame memory (CGM) on the graphic side having an 8-bit look-up table, 6 and 7 are frame memories (FCM1 and FCM2) on the full-color memory plane of 8 bits each for one pixel RGB, and 8 is FCM.
1, a frame memory (CRM) on a control surface having a display priority of FCM2 and CGM in pixel units and a surface for displaying a cursor, and 9 indicates one of FCM1, FCM2 and CGM in pixel units according to CRM information. A video synthesizing circuit to be selected, 10 is a D / A converter for converting the synthesized digital data into an analog signal, and 11 is a CRT for displaying an image. Frame memory 5-8
Consists of dual port memory.

The image display device has two full-color memory planes (FCM1, FCM2) each of which has 8 bits for each pixel RGB.
And, the graphic side having an 8-bit lookup table has one side (CGM), and FCM1 is set for each pixel.
FCM2 and CGM can be combined and displayed by controlling the transparency / opacity of each and cursor display.

The CPU 1 uses the system bus 2 for CR
A display timing setting and drawing command is issued to TC3. C
The RTC 3 generates a display timing through the image bus 4 and accesses data to the FCM 1 and the like according to a command from the CPU 1. The frame memories 5 to 8 are composed of dual port memories. This dual port memory is a memory having a port for random access and a port for serial access. In FIG. 4, the random access port is connected to the image bus 4 side, and the serial access port is connected to the video synthesizing circuit 9 side.

From the random access port, in addition to data read / write access, the head address of the data to be output to the serial access port is specified. The data of the serial access port is read at a burst-like display system clock for the number of effective pixels.

FIG. 5 shows the data flow of even-numbered pixels. The latches 12, 13, 16, 18, 19, 20,
22, 24, 25, 26, 27, 28, 30, 32, 3
3 and 35 operate at a clock that is ½ of the display pixel clock. Pixel data read from the CGM serial access port at a clock half the display pixel clock is once latched by the latch 28, and the transparency determining unit 29 compares the pixel data with a transparent color.

The data for which the transparent color of CGM is determined is latched by the latch 30, and then the data is further determined to be transparent at 31 by the CGM surface control bit of CGM. This is CG
This is because the CGM plane control bit may be designated as transparent in order to make a part of the CGM plane transparent when the M plane window is displayed. The final transparent color judgment result of the CGM surface is latched by the latch 20 and
It is input to the output determination unit 21 together with the transparent color determination results of CM1 and FCM2.

The transparent color determination of FCM1 and FCM2 is performed when the least significant bit of each R is 1 or 0. This is because when the transparent color is specified in the data of 8 bits for each RGB such as FCM1, 8 bits for each RGB (total 24 bits).
This is because it does not make much sense to compare all the (bit) data and make it a transparent color.

In addition to the above-mentioned transparency determination result, the output determination section 21 is provided with information on the display mode (interlace / non-interlace, etc.) such as FCM two-face control bit, cursor bit, display / non-display of each face. Is entered. As the output determination result, any one of FCM1, FCM2, CGM, cursor surface, and raster surface becomes active and is latched by the latch 22. The output determination result is the latches 15, 27, 3
Input to the output enable of 5, 36, 37,
Only certain pixel data is latched by the latch 16. The data flow of even pixels is shown up to the latch 16. By switching the output enable of the latch 16 in pixel units, the latch 17 can latch data in display pixel units.

Now, consider the required number of latch stages. In the case of 1024 × 768 pixel non-interlaced display, the display clock is about 65 MHz (15.4 nsec / pixel). If the TTL element AS574 is used as the latch, if the setup time and hall time (total 6 n seconds) of AS 574 are satisfied, the output determination or the like must be performed in about 9 n seconds. In the output determination, as described above, about 9 kinds of information are input, so that the processing cannot be performed by the random logic by the TTL element. Further, the B version (15 ns) of the programmable array logic (PAL) cannot be processed.

Therefore, the system is divided into two systems of even-numbered pixels and odd-numbered pixels, and processing is performed with a clock half the display clock. As a result, the output determination may be performed at about 30 ns / pixel, and the processing itself can be performed with the B version of PAL. Further, since the PAL has a limited number of input pins, the transparency determination unit 23 of the FCM 1 and the transparency determination unit 2 of the CGM 2
In No. 9, processing is further performed in the previous stage.

In the configuration of FIG. 5, the number of latches (AS574) is calculated as follows. FCM1 → 4 × 3 × 2 FCM2 → 4 × 3 × 2 CGM → (3 + 3) × 2 CRM → 4 After synthesis → 3 × 2 final → 3 total → 70 (pieces)

[0014]

The conventional image display device as described above has a problem that the number of stages to be latched must be increased as shown in FIG.

The present invention has been made in order to solve the above-mentioned problems, and an object thereof is to obtain an image display device capable of reducing the number of stages to be latched.

[0016]

An image display device according to the present invention comprises the following means. [1] Display control is performed on each of a plurality of frame memories composed of dual port memories, and a read clock for serial access port output that differs for each dual port memory is generated according to the delay time caused by this display control. Display control means. [2] Video synthesizing means for synthesizing the outputs of the serial access ports of the plurality of frame memories based on the read clock.

[0017]

In the present invention, the display control means allows
Display control is performed on each of a plurality of frame memories configured by dual port memories, and a different read clock for serial access port output is generated for each dual port memory according to the delay time caused by the display control. .. Also, by the video synthesizing means,
The outputs of the serial access ports of the plurality of frame memories are combined based on the read clock.

[0018]

【Example】

Example 1. The configuration of the first embodiment of the present invention will be described with reference to FIGS. 1 is a block diagram showing a first embodiment of the present invention, which is the same as the conventional device except for a video synthesizing circuit 9A. FIG. 2 is a circuit diagram showing a video synthesizing circuit according to the first embodiment of the present invention. In the drawings, the same reference numerals indicate the same or corresponding parts.

In FIG. 2, reference numeral 34 is a look-up table (LUT), and the CGM finally becomes RGB 8-bit data by the look-up table 34. Reference numeral 29 is a CGM transparent color transparency determination section, 31 is a section for determining CGM transparent opacity based on the transparent color determination result and the CGM control bit, and 23 is FCM1 R LS.
This is a part for determining the transparency and opacity of FCM1 by B and the control bit for FCM1. RG like FCM1
When specifying a transparent color for each 8-bit data of B, it does not make much sense to compare all 8-bit RGB data (total of 24 bits), so if the LSB of R is 1 or 0, the transparent color is I decided to.

Further, 21 is R LSB and FC of FCM2
Performs transparent opaque determination FCM2 by the control bits for M2, CGM and transparent determination result and each surface of the display hidden FCM1, priority than the raster, the output judging unit determines whether to display which faces including cursor Is.
36 and 37 are registers for displaying the cursor color and the raster color, respectively, and 17 is a latch operated by the display clock.

Next, the operation of the above-described first embodiment will be described with reference to FIG. FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.

Clock C for reading out pixel data of CGM
K1 lags behind the clock CKH because it masks the clock CKH that is half the display clock for the period of the number of effective pixels. This is when the display clock is fast (about 6
5 MHz), it may not be possible to latch with the clock CKH while processing the data read with the clock CK1. Therefore, as shown in FIG.
It is latching once with KH. The timing of the re-latched output is shown in FIG. After that, FIG.
Each process proceeds with the clock CKH until the surface synthesis shown in (h).

The waveforms shown in FIGS. 3D to 3H show the output timings of the latch 28, the latch 30, the latch 20, the latch 22 and the latch 16 of FIG. 2, respectively.
Since the reading of R of FCM1 is necessary for the transparent / opaque determination result of FCM1, the timing is as shown in FIG. 3 (k).
Hereinafter, similarly, CRM, R of FCM2, FCM1 and F
The timing of the GB read clock of the CM2 is as shown in FIGS. 3 (k), (l), and (m), respectively. The clocks CK1, CK2, CK3, and CK4 are obtained by applying four types of gates to the clock CKH so that they are valid for a desired period. By controlling the output enable of the latch 16 of the surface-synthesized data, the result latched by the display clock of FIG. 3 (j) becomes the timing shown in FIG. 3 (i) which is a pixel unit.

Here, in the configuration of FIG. 2, the latch (AS57
The number of 4) is calculated as follows. FCM1-R → 3 × 2 FCM1-GB → 1 × 2 × 2 FCM2-R → 2 × 2 FCM2-GB → 1 × 2 × 2 CGM → (3 + 3) × 2 CRM → 3 After synthesis → 3 × 2 final → 3 Total → 39 (pieces) This is 56% of the number of latches shown in the conventional example.

The first embodiment of the present invention, as described above,
By controlling the timing of the read clock from the serial access port of the dual port memory so that it differs for each display surface, it is possible to reduce the number of stages to be latched for data that does not require processing until immediately before composition. .. Also, the device can be manufactured at low cost,
A device with low power consumption can be obtained.

In other words, the first embodiment aims to reduce the number of stages of the time adjustment latches of the combined portion in the image display device which combines and displays a plurality of surfaces. In a device that synthesizes multiple surfaces composed of dual port memories 5 to 8, when performing transparent color determination, it is not possible to perform transparent color determination in one cycle of the dual port memory read clock. It is necessary to delay the read pixel data with the latches 14, 15, 16, .... For this reason, pixel data that does not require processing such as transparency determination requires a latch to simply delay until it is combined. By delaying the timing of the read clock of the dual-port memory on the surface that does not require processing such as transparency determination, the delay processing by latching pixel data is unnecessary. Therefore, by reducing the number of latches, it is possible to reduce the substrate area and suppress heat generation.

[0027]

As described above, according to the present invention, display control is performed on each of a plurality of frame memories composed of dual port memories, and each of the dual port memories is controlled according to the delay time caused by the display control. Since the display control means for generating a different read clock of the serial access port output and the video synthesizing means for synthesizing the outputs of the serial access ports of the plurality of frame memories based on the read clock are provided,
This has the effect of reducing the number of stages to be latched.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a video synthesizing circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional image display device.

FIG. 5 is a circuit diagram showing a video synthesizing circuit of a conventional image display device.

[Explanation of symbols]

1 CPU 3 CRT controller 5 Dual port memory for 8-bit color graphic memory 6 Dual port memory for RGB 8-bit full color memory 7 RGB dual port memory for 8-bit full color memory 8 Dual port memory for control memory 9A Video composition circuit

Claims (1)

[Claims] 1. Display control is performed for each of a plurality of frame memories composed of dual port memories,
A display control unit that generates a read clock of a serial access port output that differs for each of the dual port memories according to a delay time generated by the display control, and an output of the serial access ports of the plurality of frame memories based on the read clock. An image display device comprising a video synthesizing means for synthesizing.