JPH05211484A - Digital audio processing circuit - Google Patents

Abstract

PURPOSE:To reduce conversion error of a ternary/binary value when noise is included in a MUSE audio signal and to improve the reproduction characteristic by providing a threshold level variable section varying two threshold levels so that a code error is less than a prescribed object value based on the result of detection of a code error of a binary audio signal after the conversion to the processing circuit. CONSTITUTION:A threshold level variable section 36 is added to the processing circuit and a threshold level setting device of RAM structure is provided to a comparison section of a ternary/binary conversion circuit 19 in place of a conventional threshold level setting device of ROM structure. The threshold level variable section 36 is made up of a counter, a memory and an arithmetic operation circuit. Even when noise is included in a MUSE signal due to deterioration in the C/N or the like at the reception, two threshold levels are automatically corrected respectively by an increase in a code error of a binary audio signal attended with the increase in conversion error of the ternary/binary conversion circuit 19, and conversion error of the ternary/ binary conversion circuit 19 is reduced and a code error in the binary audio signal is kept to be less than an object. Or a microcomputer 17 is used for the threshold level variable section 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio processing circuit for reproducing MUSE audio signals.

[0002]

2. Description of the Related Art Conventionally, a MUSE signal for high-definition broadcasting is a digital audio signal (M
(USE audio signal) is multiplexed in the vertical blanking period, and in order to reproduce the audio signal, the MUSE-NTSC converter, MUSE decoder, etc. are provided with a digital audio processing circuit (MUSE audio processing circuit) described later. For example, MU
In the case of the SE-NTSC converter, its entire circuit is constructed as shown in FIG.

In the figure, 1 is a BS antenna for reception, 2 is a BS tuner, 3 is a MUSE-NTSC converter, and 4 is A for digitizing a MUSE signal into 8 bits.
An A / D converter 5 is an audio processing block, and has a digital audio processing circuit 6, a RAM 7 for audio processing, a digital filter 8 and a D / A converter 9 for outputting an analog audio signal.

Reference numeral 10 is a video processing block, which is MUSE.
MUS that digitally converts video signals to NTSC signals
E-NTSC video processing circuit 11, RAM 1 for video processing
2 and D / A converters 13, 14, 15 for analog-converting NTSC signals of Y, BY, and RY, composite signals of NTSC system, component signals, and video signals of Y / C signal structure are reconstructed. It has a video encoder circuit 16. Reference numeral 17 is a microcomputer that controls the operation (processing) of the converter 3.

Then, a satellite broadcast signal (BS signal) of high-definition broadcasting is received by the BS antenna 1, the received BS signal of this antenna 1 is detected by the BS tuner 2, and an analog MUSE signal is formed as a detection signal. This MUSE signal is the A / D converter 4 of the converter 3.
Is sampled at 16.2 MHz, linearly quantized, converted into a digital signal having an 8-bit structure, and this digital signal is supplied to the audio processing circuit 6 and the video processing circuit 11 as a digitized MUSE signal.

Then, the voice processing circuit 6 extracts the MUSE voice signal multiplexed from the digitized MUSE signal in the vertical blanking period of this signal, and outputs to this signal the ternary / ternary value described later.
A 16-bit binary audio signal (serial signal) is reconstructed by performing binary conversion, time axis expansion, audio decoding (DPCM decoding), and the like. This binary audio signal is supplied to the D / A converter 9 via the digital filter 8, and this converter 9
An analog audio signal is reproduced by the analog conversion of.

Further, the video processing circuit 11 decodes the digitized MUSE signal by the video decoding of the MUSE system and NTS.
By performing signal conversion to the C system and the like, the Y, BY, and RY digital signals converted to NTSC signals are decoded and formed.
These digital signals are analog-converted by the D / A converters 13 to 15 and supplied to the encoder circuit 16, and the encoder circuit 16 processes the Y, BY, and RY analog signals to perform NTSC composite. A video signal having a signal, a component signal, and a Y / C signal (Y / C separated signal) is reproduced.

By the way, the MUSE voice signal is formed on the transmitting side as described below and multiplexed with the MUSE signal. That is, analog voice signal (original signal)
Is binarized into 16-bit data by linear quantization, and is then subjected to quasi-instantaneous compression 8-bit DPCM encoding to obtain a sampling frequency of 18.225 MHz as shown in FIG.
It is converted into a binary audio signal of (= 1 / t1).

Further, this binary audio signal is binary /
Based on the ternary conversion rule, each 3 bits are converted into ternary data of 2 symbols and time-compressed, and each ternary data is resampled at 12.15 MHz.
Sampling frequency shown in (b) of 12.15 MHz
(= 1 / t2) MUSE audio signal. Then, this MUSE audio signal is multiplexed in the vertical blanking period of the MUSE signal.

On the other hand, on the receiving side, the A / D converter 4
MUS to 16.2MHz output signal (MUSE signal)
Since the E audio signal is multiplexed at 12.5 MHz, the audio processing circuit 6 is configured as shown in FIG. And
The digitized MUSE signal of the A / D converter 4 is first supplied to the level converter 17, and the level conversion is performed by the converter 17 so as to eliminate the level difference between the modes of AM / FM and the low-pass filter 18 is supplied. Is supplied to.

The filter 18 receives an input signal of 12.5M.
It is converted into a sampling frequency of Hz, the MUSE audio signal is extracted and supplied to the ternary / binary conversion circuit 19. As shown in FIG. 8, the conversion circuit 19 includes a digital comparison unit 20 for ternary discrimination and a ternary / binary conversion unit 21, and each bit B1 of the input MUSE audio signal (MUSE input signal) Si. Are converted into 8-bit data D1, D2, D3, D4, ... By an A / D converter 4 and supplied to a comparison unit 20.

As shown in FIG. 9, the comparing section 20 includes comparators 20a and 20b and a threshold value setting unit 20 having a ROM structure.
c, 20d, an exclusive OR gate 20e, AND gates 20f, 20g, and an inverter 20h.
0c and 20d are pre-written 2 for ternary discrimination in FIG.
8-bit data Dh and Dl having threshold values h and l are generated. Then, the input data Di (= D1, D2, D3, D
4, ...) and the data Dh and Dl of the threshold values h and l, the comparator 20a outputs 1 only when Dh <Di, and the comparator 20b outputs only when Di <Dl. Becomes 1.

Further, by the logic gate processing of the outputs of the comparators 20a and 20b, the output H of the AND gate 20g becomes 1 when Dh <Di, and the output M of the OR gate 20e becomes 1 when Dl≤Di≤Dh. When Di <Dl, the output L of the AND gate 20f becomes 1. And
The comparator 20 is MUS by the alternative 1 of the outputs H, L and M.
The three values of each bit of the E audio signal are judged and the outputs H, L, M are output.
The 3-bit discrimination result is supplied to the conversion unit 21 as ternary data.

The conversion unit 21 has a look-up table memory of ternary / binary conversion rules corresponding to the binary / ternary conversion rules of FIG. 6, for example. The value data is converted back to binary data, that is, a binary audio signal. Further, the binary audio signal of the conversion unit 21 is supplied to the time expansion circuit 22, which uses the memory 23 of the dual port RAM configuration to convert the speed of the binary audio signal to expand its time axis.

Further, the output signal of the time axis expansion circuit 22 is supplied to the interframe deinterleave circuit 24, and the circuit 24 performs interframe deinterleave processing on the input signal by using the memory 25 having a dual port RAM structure. 2 of 1.35 Mbit / sec audio bitstream
A value voice signal is formed. This binary audio signal is supplied to the control code detection circuit 26, the frame synchronization detection circuit 27 and the bit deinterleave circuit 28, and the control code detection circuit 2
Reference numeral 6 detects the code of control information such as the audio mode being received from the audio bit stream, and supplies the detected control information to the microcomputer 17 and the like.

The frame sync detection circuit 27 detects the audio frame period from the audio bit stream to form a frame sync signal which serves as a reference signal for the timing generation circuit 29 and the like, and the bit deinterleave circuit 28 makes the bits of the audio bit stream. The array is returned to the original and supplied to the BCH error correction circuit 30.

The error correction circuit 30 detects and corrects a code error, which is mainly a random error, in the audio bit stream generated by the transmission, and corrects the binary audio signal.
The erroneous data, the range data, etc. are supplied to the word deinterleave circuit 31 and the range correction circuit 32. Further, the word deinterleave circuit 31 corrects a continuous error in the audio word of the binary audio signal, and the range correction circuit 32 corrects an error in the range bit data included in the binary audio signal.

Then, the word deinterleave circuit 31,
The binary audio signal and range bit data corrected by the range correction circuit 32 are supplied to a quasi-instantaneous expansion circuit 33, which uses the range bit data to expand the binary audio signal into a 16-bit structure. , And releases the quasi-instantaneous compression at the time of transmission and supplies it to the DPCM decoder 34. In addition, the expansion circuit 33 uses a stereo (LR) signal included in the binary audio signal.
The switching signal and the like are extracted and supplied to the digital filter 8, the D / A converter 9 and the like in the subsequent stage of the processing circuit 6.

Further, the decoder 34 decodes the inputted binary audio signal to form a 16-bit baseband binary audio signal, and supplies this audio signal to the digital filter 8. The timing generation circuit 29 is the PLL circuit 3
Various timing signals and clock signals are formed under the control of 5, and each part in the processing circuit 6 and the digital filter 8,
It is supplied to the D / A converter 9 and the like.

[0020]

In the conventional digital audio processing circuit, the ternary / binary conversion circuit 19 is erroneously converted due to deterioration of C (carrier power) / N (noise) during reception. Due to this erroneous conversion, a noise sound is finally generated and the reproduction characteristic is deteriorated. That is, when the C / N at the time of reception is deteriorated due to bad orientation of the BS antenna 1, bad weather, etc., the MUSE voice signal is changed as shown in FIG.
A waveform a with no noise when the C / N is good is distorted from a waveform a with noise when the C / N is deteriorated.

At this time, as is clear from the relationship between the waveform 1 and the threshold values h and l for ternary discrimination, the conventional threshold values h and l are fixed and the MUSE voice signal distorted by noise is generated. A situation in which the threshold values h and l are erroneously exceeded easily occurs. Therefore, erroneous determination of three values of the MUSE voice signal occurs, and as a result, the error correction circuit 30 exceeds the correction capability of 3 values.
Value / binary erroneous conversion occurs and noise sound is output.

According to the present invention, the MU is deteriorated due to deterioration of C / N at the time of reception.
It is an object of the present invention to reduce ternary / binary erroneous conversion when SE audio signal contains noise and improve reproduction characteristics.

[0023]

In order to achieve the above object, in the digital voice processing circuit of the present invention, the code error is a predetermined target value based on the detection result of the code error of the converted binary voice signal. A threshold varying unit that varies two thresholds is provided as follows.

[0024]

In the case of the digital voice processing circuit of the present invention having the above-mentioned configuration, the binary voice signal after conversion by the threshold variable unit has a ternary value of 1/2 so that the code error of the binary voice signal becomes less than a predetermined target value. Since the two thresholds for changing values are corrected, even if noise is included in the MUSE audio signal due to deterioration of C / N at the time of reception, erroneous conversion of ternary / binary does not increase and binary The code error of the audio signal is suppressed and the generation of unpleasant noise sound is prevented,
Playback characteristics are improved.

[0025]

EXAMPLE One example will be described with reference to FIGS. FIG. 1 and FIG. 2 show the case where the present invention is applied to a digital audio processing circuit of a MUSE-NTSC converter, and in those drawings, the same reference numerals as those in FIGS. 4 to 10 indicate the same or corresponding ones.

A difference from the conventional circuit is that a threshold variable section 36 is added and the comparison section 2 of the ternary / binary conversion circuit 19 is added.
0 is the threshold value setter 20c, 20d of the conventional ROM configuration.
Instead of RAM, threshold setting devices 20α, 20β
This is the point where The threshold variable unit 36 is a counter 36
a, a memory 36b, and an arithmetic circuit 36c.

The counter 36a is reset at a frame cycle by the frame synchronization signal of the frame synchronization detection circuit 27, and an error detection pulse generated every time a code error is detected by the error correction circuit 30 is used as a clock pulse in each frame. Count the number. Further, the RAM 36 memory 36b is written with the counting result of each frame of the counter 36a by the timing control (time management) of the frame synchronization signal, and always holds the latest N frame counting result.

Further, the arithmetic circuit 36c takes in the counting results of the latest N frames of the memory 36b at the end of each one frame by the timing control of the frame synchronization signal and averages them, thereby eliminating the code error due to transient fluctuation. The code error of the binary audio signal of each frame is detected.

If the detected value of the code error is larger than the predetermined target value, the data Dh and Dl of the threshold values h and l of the threshold value setters 20α and 20β are rewritten.

By this rewriting, the threshold h of the setter 20α is lowered by a unit amount, and the threshold l of the setter 20β is raised by a unit amount. The initial value corresponding to the target value is written in the memory 36b by the initial setting based on the power-on of the converter, and the arithmetic circuit 36c corresponds to the target value in the threshold value setters 20α and 20β. Threshold h, l
Write the initial data of.

Since the threshold values h and l are repeatedly rewritten by the arithmetic circuit 36c, the threshold values h and l are set so that the code error of the binary audio signal is equal to or less than the set target value. It is changed by the cycle and corrected.

Therefore, even if noise is included in the MUSE voice signal due to deterioration of C / N at the time of reception and the like, the code error of the binary voice signal increases as the erroneous conversion of the ternary / binary conversion circuit 20 increases. As a result, as shown in FIG. 3, the threshold values h and l are automatically corrected to decrease and increase respectively, the erroneous conversion of the conversion circuit 19 is reduced, and the code error of the binary audio signal is held below the target value. Generation of noise noise is prevented. Note that FIG.
10A and 11B are waveforms of the MUSE voice signal when C / N is good and when it is deteriorated, as in FIGS.

Although the frame synchronization signal of the frame synchronization detection circuit 27 is used for resetting the counter 36a in the above embodiment, for example, the timing signal of the timing generation circuit 29 may be used for resetting the counter 36a. Furthermore, the configuration of the threshold variable unit 36 is not limited to the embodiment, and the counter 36a and the memory 36
b, the arithmetic circuit 36c can be realized by software processing of a computer, and in this case, the microcomputer 17 may be used for the threshold value changing unit 36.

[0034]

Since the present invention is configured as described above, it has the following effects. Since the threshold value changing unit 36 corrects the two threshold values h and l for three-value / two-value conversion so that the code error of the converted two-value audio signal becomes less than or equal to a predetermined target value, Even if noise is included in the MUSE voice signal due to the deterioration of C / N, the erroneous conversion of ternary / binary does not increase, and the code error of the binary audio signal is suppressed to generate an unpleasant noise sound. It is possible to prevent and improve reproduction characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a digital audio processing circuit of the present invention.

2 is a detailed block diagram of a portion of FIG. 1. FIG.

FIG. 3 is an explanatory diagram of a threshold change of FIG.

FIG. 4 is a block diagram of a MUSE-NTSC converter.

5A and 5B are waveform diagrams of a binary audio signal and a ternary audio signal.

FIG. 6 is an explanatory diagram of binary / ternary conversion on the transmission side.

FIG. 7 is a block diagram of a conventional example.

FIG. 8 is an explanatory diagram of a configuration of the three-value / two-value conversion circuit in FIG.

FIG. 9 is a detailed connection diagram of a comparison unit in FIG.

FIG. 10 is an explanatory diagram of threshold values in a conventional example.

[Explanation of symbols]

 19 2-value / 3-value conversion circuit 27 Frame synchronization detection circuit 30 BCH error detection circuit 36 Threshold variable part h, l 3-value / 2-value conversion two-threshold value

Claims (1)

[Claims] 1. A digitally converted ternary MUSE audio signal is compared with a binary threshold value to determine the ternary value of the MUSE audio signal, and the MUSE audio signal is converted into a binary audio based on the result of the determination. In a digital voice processing circuit for decoding into a signal and reproducing the signal, the threshold value is varied so that the code error becomes equal to or less than a predetermined target value based on the detection result of the code error of the binary audio signal. A digital audio processing circuit having a value varying section.