JPH05210971A - Multi port memory - Google Patents

Abstract

PURPOSE:To eliminate a passing noise by synchronizing the storage data of a first RAM with the frame rate of a display monitor, transferring it to a second RAM, reading the storage data of the second RAM and displaying it on the monitor. CONSTITUTION:A figure and character data formed on a computer are written in a RAMa 1-1 from a random data terminal 6 and video data from a seria1 data terminal 8 is transferred to on optional row in the RAMa 1-1 through a SAMa. Then the data written in the RAMa 1-1 is transferred to a RAMb 1-2 by a transfer signal 41 and read to a serial data terminal 9 by the address signal of an address terminal 7-2 through a SAM 5. Thus, the data of the entire memory are read from the other terminal 9 without depending on the write data from one side terminal 8. Thus, the passing noise is eliminated with simple constitution since the data of one screen fixed regardless of the write of the video data is read and displayed on the monitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a multiport memory which is effective when used as an image memory.

[0002]

2. Description of the Related Art An image display device for displaying image data such as graphics and characters created on a computer on the screen of a raster scan type CRT requires a memory called a frame buffer for storing display image data. As a memory for displaying figures and characters created on a computer, a random access memory and a serial access memory are provided, and image data generated at an arbitrary position on a CRT created on a computer is transferred to the random access memory. A random port for writing and a row of data in the random access memory are transferred to the serial access memory, and CR
A dual port memory having a serial port for reading continuous data required for displaying on T from a serial access memory is generally used. With the recent improvement in information processing technology, such an image display device is required to have a multimedia display function of displaying a video signal and the like in combination with graphics and characters created on a computer. The image memory used in such a multimedia display device has a random port for writing graphics and character data created on a computer, a serial port for reading continuous data required for display on a CRT, a video signal, etc. A triple port memory with a serial port for writing is used.

This triple port memory is, for example, 19
May 24, 1990 "ELECTRONIC DESI
GN (Electronic Design) "P37-43, and has the configuration shown in FIG. In FIG. 1, reference numeral 1 denotes a random access memory (RAM) composed of memory cells for storing image data corresponding to a display screen. By applying an address signal from an address terminal 7 to a row decoder 2 and a column decoder 3, the RAM 1 Writing to and reading from the random data terminal 6 from the memory cell at any position in Reference numerals 4 and 5 are serial access memories (SAMa and SAMb) for storing data corresponding to one row in the RAM 1, and data transfer with any row in the RAM 1 is possible.

FIG. 5 shows the structure of the RAM 1.
Word lines 11 to 14 (WL1 to WLm) and bit lines 15 to 18 (BL1, / (BL1) to BLn, / (BL
A memory cell composed of a transfer gate and a capacitor is arranged at each intersection of n). Bit line 15
The signals of # 18 to # 18 are amplified by the sense amplifiers 10-1 to 10-n, and the column decoder 3, SAMa4 and SAM
It is supplied to b5.

When the triple port memory having the structure shown in FIG. 4 is used in the above-mentioned multimedia display device, the graphic and character data created on the computer are transferred via the random data terminal 6 to the address terminal 7 It is written in an arbitrary position in the RAM 1 designated by the address signal given to. In reading data from the RAM1 to the random data terminal 6, the stored data at an arbitrary position in the RAM1 designated by the address signal given to the address terminal 7 is read to the random data terminal 6 as in the case of writing. To be done.

In writing the video data from the serial data a terminal 8, the video data is written from the serial data a terminal 8 to the SAMa 4, and the address terminal 7
The data stored in the SAMa4 is transferred to any one row in the RAM1 designated by the row address given to the RAM1. When reading the display data from the serial data b terminal 9, the RA specified by the row address for the RAM 1 given to the address terminal 7 is read.
Any one row of data in M1 is transferred to SAMb5,
It is continuously read out to the serial data b terminal 9.

As described above, the random access memory (RA
M) and two serial access memories (SAMa, SA) capable of transferring data to the random access memory.
Mb) and data for random access memory
By providing a random data terminal for inputting / outputting data and two serial data terminals for inputting / outputting data to / from two serial access memories, a computer can be used as an image memory for a multimedia display device. It is possible to write video signals and the like together with the figures and characters created above and read out continuous data for display.

[0008]

[Problems to be Solved by the Invention] NT as a video signal
When the SC signal is written and displayed on a monitor such as a workstation, the frame rate for updating the image information is 59.94 Hz for the NTSC signal and 60 Hz for the monitor.
Since it is different from 77 Hz, what is called passing noise is generated. Overtaking noise is the difference in frame rate, and the display scanning line on the monitor overtakes the scanning line of the input image, so that images of different frames with different NTSC signals are displayed above and below the monitor display screen. The phenomenon that appears in Fig. 6 will be described with reference to Fig. 6.

In FIG. 6, reference numeral 45 is a monitor and an input N.
A TSC image is shown, and each line in the monitor and input NTSC image 45 is a scan line and corresponds to a word line representing a row in the memory forming the frame buffer. The scanning line of the input NTSC image is a and the scanning line of the monitor image is b. From the state in which the scanning line a of the NTSC image precedes the scanning line b of the monitor image due to the difference in frame rate, as shown in (6-1),
As shown in (6-2), the scanning line b of the monitor image is NTS.
A state occurs in which the scan line a of the C image is overtaken. (6-2)
In the state shown in, the image of the new frame of the input NTSC image is displayed above the scanning line Y on the monitor display screen.
Below the scanning line Y, an image one frame before is displayed, and the display screen is disturbed. This phenomenon is caused by the monitor and NTSC
It appears in the cycle of the frame rate difference of the image, and occurs once every 17 seconds when the frame rate of the monitor is 60 Hz.

As described above, when images of different frame rates are displayed on the monitor display screen, passing noise occurs due to the difference in frame rate.

The present invention has been made in view of the above problems.
An object of the present invention is to provide an image memory having a memory cell for storing data for one screen and transferring the stored data for one screen to another screen to eliminate passing noise. ..

[0012]

According to the present invention, in order to solve the above problems, memory cells arranged in an array form a first capacitor for storing data, and a first capacitor connected to the first capacitor. One transfer gate, a second capacitor for holding the data stored in the first capacitor, a second transfer gate connected to the second capacitor, and the first capacitor. The data stored in the capacitor
Random access memory constituted by transfer means for transferring the data to the second capacitor, a first bit line connected to the first transfer gate, and the second transfer gate. A second bit line connected to the first transfer gate and a first bit line connected to the first transfer gate.
, A second word line connected to the second transfer gate, and a first load / decoder for driving the first word line. A second load decoder for driving the second word line, a first sense amplifier for amplifying the signal of the first bit line, and a second
Second sense amplifier for amplifying the signal on the bit line of the first bit line and the first sense amplifier for transferring data between the first bit line and the first bit line.
Of the serial access memory and the second serial access memory for transferring data between the second bit line and the second bit line.

[0013]

According to the present invention, the storage data of the first capacitor for storing the written image data is transferred to the second capacitor in synchronism with the frame rate of the display monitor. It becomes possible to read the storage data of the second capacitor and display it on the monitor. Therefore, the image data stored in the second capacitor does not change within one frame display period of the monitor, and the overtaking noise can be eliminated.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION In order to prevent the read data from the frame buffer supplied to the display monitor from changing during one frame period of the display monitor, two capacitors for storing the data are used. And a memory cell provided with a data transfer means between the two capacitors.

FIG. 7 illustrates the multiport memory 51 of the present invention for use in a system environment having a color monitor 57 connected to a color map 56 via line 69. In this system, the color map 56 is
The multiport memory 51 of the present invention is connected via the video data bus 68, and the multiport memory 51 and the color map 56 are controlled by the serial port control circuit 55 via the lines 66 and 67.

The multi-port memory 51 has a data bus 62.
And the drawing hardware 53 via the address bus 63
It is connected to the. The random port control circuit 54 controls the drawing hardware 53 via a line 64 and the multiport memory 51 via a line 65. The drawing hardware 53 is connected via a line 61 to the interface 52 connected to the standard bus 60. In addition, the multi-port memory 51 receives the serial data writing circuit 7 via the serial data line 71.
It is connected to 0.

The multiport memory 51 of the present invention stores the image actually displayed on the color monitor 57.
The information stored in the multiport memory 51 is sequentially sent to the color map 56 via the video data bus 68 and displayed on the color monitor 57. The serial port control circuit 55 gives a row address 72 for serial reading to the multiport memory 51, and controls the transfer of information stored in the multiport memory 51 to the color map 56.

When the information stored in the multiport memory 51 is changed through the drawing hardware 53 in order to change the image displayed on the color monitor 57,
An appropriate command is sent from the standard bus 60 to the drawing hardware 53 via the interface 52. The random port control circuit 54 transfers the drawing hardware 53 from the bus 61.
Based on the information received by the multiport memory 51
Controls the modification of the information stored within. The address of the information to be changed is supplied via the address bus 63, and the data for the change is supplied via the data bus 62. The standard bus 60 is connected to the computer,
Characters and graphic data created by a computer are given to the drawing hardware 53 via the standard bus 60.

When the information stored in the multiport memory 51 is changed via the serial data write circuit 70, serial data is given from the serial data bus 73. Serial data writing circuit 7
0 transfers serial data into the multi-port memory 51 via the serial data line 71. In this way, the information stored in the multiport memory 51 is modified. The corrected information stored in the multi-port memory 51 is changed to a displayable state by the control signal 66 from the serial port control circuit 55, and transferred to the color map 56 via the video bus 68 to transfer it to the color monitor 5.
The image on 7 can be changed.

FIG. 1 shows an embodiment of the multiport memory configuration according to the present invention. In the figure, 1-1 and 1
-2 is a random access memory (RAMa, RA that includes memory cells for storing image data corresponding to a display screen).
Mb), the RAMa1-1 applies the address signal from the address terminal 7-1 to the row decoder 2-1 and the column decoder 3 so that the random data from the memory cell at an arbitrary position in the RAMa1-1. Writing to and reading from the terminal 6 are performed. RAMb1-2 is RA
It is a memory having a storage capacity equal to that of Ma1-1, and is controlled by the transfer control signal 41 to transfer the RA through the transfer gate 40.
It has a function of holding the storage data transferred from Ma1-1.

4 and 5 are RAMa1-1 and RAM
a serial access memory (SAMa and SAMb) for storing data corresponding to one row in b1-2,
SAMa4 is a RAM designated by the load decoder a2-1 according to the address signal from the address terminal 7-1.
For data transfer with an arbitrary row in a1-1, SAMb is an arbitrary row in RAMb1-2 designated by the load decoder b2-2 according to an address signal from the address terminal 7-2. Data transfer from the.

FIG. 2 shows the structures of the RAMa1-1, RAMb1-2 and the transfer gate 40, and FIG. 3 shows an example of a concrete circuit structure of the memory cell in FIG. RAMa1-1, RAMb1-2 and transfer gate TG are integrally formed in the memory cell in FIG.

Word lines 11-1 to 14-1 (WLa1 to
WLam), bit lines 15-1 to 18-1 (BLa1,
/ (BLa1) to BLan, / (BLan) and work
Line 11-2 to 14-2 (WLb1 to WLbm), bit line 15-2 to 18-2 (BLb1, / (BLb1) to
A memory cell mc as shown in FIG. 2 is arranged at each intersection of BLbn and / (BLbn).

Each memory cell mc, as shown in FIG.
Transfer gates T1 (30), T4 (33) and two capacitors C1 (34), C2 (35) and 2
The transfer gate (TG) is composed of individual transistors T2 (31) and T3 (32). Capacitor C1
The transfer gate T1 (30) is driven by the word line WLa into the state (34) to be in a conductive state, so that data is written and read out via the bit BLa. The transfer gate TG is a transistor T2 (31)
And T3 (32), the transistor T3 (32) is turned on under the control of the transfer control signal, so that the electric charge corresponding to the electric charge stored in the capacitor C1 (34) is transferred to the transistor T2 (31). And is stored in the capacitor C2 (35). The data stored in the capacitor C2 (35) is read out via the bit BLb when the transfer gate T4 (33) is driven by the word line WLb and becomes conductive.

The signals on the bit lines 15-1 to 18-1 are amplified by the sense amplifiers 10a-1 to 10a-n and supplied to the column decoder 3 and SAMa4, and the bit line 15-2.
18-2 are sense amplifiers 10b-1 to 10b-.
It is amplified by n and supplied to SAMb5.

When the triple port memory having the structure shown in FIG. 1 is used in the above-mentioned multimedia display device, the graphic and character data created on the computer are transferred via the random data terminal 6 and the address terminal 7 to each other. Kara Rod Deco a2-1
Further, the data is written in an arbitrary position in the RAMa1-1 designated by the address signal given to the column decoder 3. In reading data from the RAMa1-1 to the random data terminal 6, the RAMa designated by the address signal given to the address terminal 7 is used as in the writing.
The stored data at an arbitrary position in 1-1 is read out to the random data terminal 6.

In writing the video data from the serial data a terminal 8, the video data is written from the serial data a terminal 8 to the SAMa 4, and the address terminal 7
-1 to RAMa1-1, and the RAMa1-1 specified by the load decoder a2-1.
The data stored in SAMa4 is transferred to any one of the lines. The data written in the RAMa1-1 is transferred to the RAMb1-2 via the transfer gate 40 by the transfer control signal 41 synchronized with the frame rate of the display monitor connected to the serial data b terminal 9.

When reading display data from the serial data b terminal 9, the RAMb from the address terminal 7-2 is read.
Give row address to 1-2, load decoder b2-
Any one row of data in the RAMb1-2 designated by 2 is transferred to the SAMb5 and continuously read from the SAMb5 to the serial data b terminal 9.

Thus, the two random access memories (RAMa, RAMb), the data transfer means between the two random access memories, and the two serials capable of data transfer to the respective random access memories. It has an access memory (SAMa, SAMb), a random data terminal for inputting / outputting data to / from a random access memory, and two data input / outputs for two serial access memories. By providing the serial data terminal, it is possible to read the entire data of the random access memory from the other serial data terminal without depending on the write data from the one serial data terminal.

As described above, according to the present embodiment, a multimedia display device for displaying video data such as NTSC and the like on the same monitor screen at the same time as image data such as figures and characters created by a multiport memory on a computer. In this case, since the fixed one-screen data can be read and displayed on the monitor regardless of the writing of the video data, it is possible to realize a system having no overtaking noise with a simple configuration.

[0031]

INDUSTRIAL APPLICABILITY The multiport memory of the present invention is used on a computer to simultaneously generate image data such as figures and characters and NTSC.
When applying such video data to a multimedia display device that displays on the same monitor screen, it is possible to read out fixed one-screen data and display it on the monitor, regardless of the writing of the video data. Therefore, it is possible to realize a system that does not generate overtaking noise with a simple configuration.

An image display device for displaying image data such as graphics and characters created on a computer has two frame buffers, and one frame buffer stores image data such as graphics and characters. During the writing period, the display data is read from the other frame buffer, and when the image data such as figures and characters is written in the one frame buffer, the reading of the display data is started and the other frame buffer is started.
A function called a double buffer for writing image data such as figures and characters in a buffer is widely used for creating animations. In order to realize such a double buffer function, two frame buffers must be provided, so that a huge number of parts is required to configure the system. When the multiport memory of the present invention is used in a system requiring this double buffer function, image data such as graphics and characters created on a computer is written in one random access memory (RAMa), and when the writing is completed. The above double buffer function can be realized by transferring the data to the other random access memory (RAMb) and reading the display data from the random access memory (RAMb). Functions can be configured, and it is extremely effective in reducing the number of parts. Thus, the present invention is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multiport memory according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a random access memory in the memory.

FIG. 3 is a circuit configuration diagram of a memory cell in the memory.

FIG. 4 is a block diagram of a conventional multi-port memory

FIG. 5 is a block diagram of a random access memory in the same memory.

FIG. 6 is an explanatory diagram of passing noise.

FIG. 7 is an explanatory diagram of a system configuration using the multiport memory of the present invention.

[Explanation of symbols]

 1-1, 1-2 Random access memory 2-1, 2-2 Row decoder 3 Column decoder 4, 5 Serial access memory 6 Random data terminal 7 Address terminal 8, 9 Serial data terminal 40 Transfer gate 41 Transfer control signal

Claims (1)

[Claims] 1. A first capacitor in which memory cells arranged in an array store data, a first transfer gate connected to the first capacitor, and a first capacitor. A second capacitor for holding the stored data, a second transfer gate connected to the second capacitor, and a data stored in the first capacitor.
Random access memory constituted by transfer means for transferring the data to the second capacitor, a first bit line connected to the first transfer gate, and the second transfer gate. A second bit line connected to the first transfer gate and a first bit line connected to the first transfer gate.
, A second word line connected to the second transfer gate, and a first load / decoder for driving the first word line. A second load decoder for driving the second word line, a first sense amplifier for amplifying the signal of the first bit line, and a second
Second sense amplifier for amplifying the signal on the bit line of the first bit line and the first sense amplifier for transferring data between the first bit line and the first bit line.
And a second serial access memory for transferring data between the second serial access memory and the second bit line.