JPH0520911B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to semiconductor integrated circuit devices, and particularly to area-efficient master slice LSIs (large scale LSIs).
The present invention relates to a semiconductor integrated circuit device suitable for an integrated circuit. [Background of the Invention] Master slice LSI is a method of manufacturing LSIs that have the desired electrical circuit behavior by creating only the mask corresponding to the wiring out of the 10-odd masks used when manufacturing LIS according to the product being developed. That's what I do. FIG. 4 shows the configuration of a conventional masker slice LSI. A semiconductor chip 1 has a bonding pad and an input/output circuit area 2 on its outer periphery, and has basic cells 3 consisting of functional elements such as transistors inside.
A configuration is adopted in which a large number of basic cell rows 4 arranged in the axial direction are repeatedly arranged in the y-axis direction with a wiring region 5 in between. In order to obtain the desired electrical circuit operation, one or several adjacent basic cells 3 may be connected together.
Forms logic blocks such as NAND gates and flip-flops. After arranging various logic blocks formed by a plurality of basic cells 3, a desired LSI is manufactured by connecting the logic blocks according to the logic diagram. Note that the placement and wiring are automated by a computer using a DA system (Design automation system). By the way, in integrated circuit devices including logic circuits, it is determined whether various elements can obtain the desired functions and performance by applying test pattern input signals from the outside, and this is generally called diagnosis. . Here, the input test pattern must be one that can diagnose all internal elements, and the ratio of diagnosable elements to the total number of elements is defined as the diagnostic rate.
Therefore, when creating this input test pattern, it is necessary to achieve a practically sufficient diagnostic rate with as few steps as possible, but normal logic integrated circuit devices usually require several thousand steps. . Furthermore, with the recent trend toward higher integration,
Achieving a diagnosis rate of nearly 100% involves tens of thousands of steps, making it difficult. Previously, input test patterns had to be obtained and created, resulting in a huge amount of work. especially,
In products like Master Slice LSI, where most of the design work is automated and the design period is shortened to around one month, the period for creating input test patterns for diagnosis inevitably increases, shortening the development period. This has become the biggest obstacle to doing so. In order to solve the above problems, a circuit for communication diagnosis is added at the time of logic design. As shown in Japanese Patent Publication No. 57-3107, flip-flops in the internal circuit are connected in series to form a shift register, an input signal is given to the integrated circuit through the shift register to operate it, and the result is transferred to the integrated circuit. As shown in JP-A No. 57-133644, a shift register for testing is provided around the semiconductor substrate, and each bit of the register is It is known that desired parts of a master slice LSI mounted on a semiconductor substrate are connected by wiring, and the output states of the parts are input in parallel to the register, and then output in series using a shift clock. In the former example, the shift register's clock signal line must be commonly connected to almost all registers in the chip. Furthermore, in the latter example, it is necessary to form diagnostic wiring from internal nodes to peripherally arranged registers. These wirings will hereinafter be referred to as diagnostic wirings. Therefore, when forming the diagnostic circuit in the master slice LSI, general logic connection wiring and diagnostic wiring are required, and the wiring area 5 becomes insufficient. Therefore, it was necessary to secure a wiring area for diagnostic wiring, which resulted in an increase in chip size. Furthermore, since the wiring is automatically done by the DA system, the wiring length becomes long, and the wiring length changes for each product LSI, resulting in a reduction in the speed and fluctuation of the diagnostic signal, increasing the diagnostic time and making the diagnosis difficult. I came across a problem. [Object of the Invention] An object of the present invention is to provide a semiconductor integrated circuit device that can reduce the wiring area and chip size, improve the speed of diagnostic signals, and reduce their fluctuations. be. [Summary of the Invention] The present invention that achieves the above object is characterized by arranging a large number of basic cells made of functional elements on one main surface in one direction to form a basic cell row, and forming the basic cell row. A plurality of semiconductor chips arranged in parallel in a direction perpendicular to the basic cell row, and first and second semiconductor chips arranged across all the basic cells constituting the basic cell row and substantially parallel to the basic cell row. In a semiconductor integrated circuit device having two power supply lines, the functional element is connected across all the basic cells constituting the basic cell array and substantially parallel to the first and second power supply lines. Diagnostic control signal wiring for diagnosis is provided, and at least one basic cell of the basic cell array constitutes a driver cell that connects the diagnostic control signal wiring and the input buffer circuit. In a preferred embodiment of the present invention, the driver cells are composed of multiple stages, and the driver cells in the previous stage are connected to multiple driver cells in different basic cell rows. Furthermore, in a preferred embodiment of the present invention, the driver cell is provided at one end of the basic cell column. Furthermore, in a preferred embodiment of the present invention, at least one basic cell of the basic cell array has three basic cells connecting the wiring and the output buffer circuit.
Configure the state buffer cell. Furthermore, in a preferred embodiment of the present invention, the three-state buffer cell is provided at the other end of the basic cell column. [Embodiments of the Invention] Diagnosis, which is the basis of the present invention, will be explained. Although the present invention can be applied to the above-mentioned diagnostic circuit system, the most suitable example is the
A diagnostic method using a flip-flop with a diagnostic latch proposed as No. 58-211355 will be described. Figure 5 shows a D-type flip-flop with a diagnostic latch 10 (hereinafter the flip-flop will be referred to as FF).
This shows the configuration of In this case, type D
This is an example of FF, but Edge Trigger FF and JK type
FF etc. can also be realized with a similar configuration. The D-type FF 10 with a diagnostic latch consists of a main FF section 11 and a diagnostic latch section 12. Normal logic operation signals, that is, the latch timing signal CK of the main FF section 11,
Input data signal D and Q output data signal Q1 are transferred to signal lines 13, 14, and 15, respectively. Furthermore, the Q output data signal Q2 of the diagnostic latch 12,
The Q output data signal 2 is connected to signal lines 16 and 16, respectively.
Transferred to 17. Other signal lines 18, 19, 2
Reference numerals 0, 21, and 22 are diagnostic control signal lines for writing (scan-in) and reading (scan-out) diagnostic data. The main FF section 11 basically has a normal FF function from the diagnostic bus line 22.
It has the added function of independently writing diagnostic data. For write operation, the diagnostic mode signal MC ₁ is set to “0” level, inhibiting the input of normal logic operation signals, and at the same time
This is done in synchronization with the timing of SW's "1" level. The diagnostic latch section 12 is a latch circuit dedicated to diagnosis, and the Q output data signal Q of the main FF section 11
1 at the "1" level timing of the latch timing signal _C2 , and sends the captured data to the diagnostic bus line 22 in synchronization with the read signal SR on the signal line 21. FIG. 6 is a CMOS circuit that embodies FIG. 5, and the same components as those in FIG. 6 are given the same reference numerals. This circuit is a CMOS switch 100 to 10
3. Inverters 105-108, 110, 11
It consists of a 1- and 2-input NAND gate 109, a clocked gate inverter 104, and NMOS switches M20 and M21. The circuit of the clocked gate inverter 104 is shown in FIG.
It consists of PMOS transistors M22, M23 and NMOS transistors M24, M25. M22 and M
25 gate electrodes are commonly connected, and the signal line 11
Connected to 2. Note that items that are the same as or equivalent to those described above are indicated by the same reference numerals. Write signal SW=
When it is "1"(="0"), both the PMOS transistor M23 and the NMOS transistor M24 are turned off, so the output 113 is in a high impedance state. Next, write signal SW="0"
(SW="1"), PMOS transistor M2,
Since both NMOS transistors M24 are turned on, the output of the output line 113 becomes an inverter signal at the signal level on the signal line 112. Next, the operation will be explained. Diagnostic mode signal
When MC ₁ is at the "1" level, the signal line 18 of the 2-input NAND gate 109 is at the "1" level, so the signals φ ₁ and ₁ have the same logic value as the latch timing signal CK and the inverted logic of CK, respectively. Takes a value. In the logical formula, φ ₁ =CK, ₁ =.
From now on, we will use this same notation. In this state, write signal SW = “0”, read signal SR =
By setting the latch timing signal C ₂ to "0" and the latch timing signal C 2 to "1", the FF 10 with a diagnostic latch performs a normal logical operation. Main FF section 11 on signal line 15
Q output signal Q1 of CMOS switch 102
(Since C ₂ = “1”, φ ₂ = 1, ₂ = 0,
(DC on state), inverter 1
The signals are output from signal lines 16 and 17 via lines 07 and 108. On the other hand, when the diagnostic mode signal _MC1 becomes "0" level, read and write operations can be performed. Since MC ₁ = “0” level, the output ₁ of the 2-input NAND gate 109 becomes “1”, and the inverter 11
The output φ ₁ of 0 is fixed at "0", and the CMOS switch 100 and the CMOS switch 101 are turned on. This means that the normal logic input signal is cut off. First, the write operation will be explained. The write signal SW is set at "1" level for a certain period of time, and diagnostic data is transferred to the diagnostic bus line 22 in synchronization with this.
At this time, the output of the clocked gate inverter 104 is in a high impedance state and the NMOS switch M20 is turned on, so that diagnostic data is written via the inverter 106 and the CMOS switch 101. Next, a read operation is performed according to the following procedure.
First, the latch timing signal _C2 is set to “1” for a certain period of time.
level, and place the front main unit on the diagnostic latch part 12.
The Q output data signal Q1 of the FF section 11 is transferred, and then the read signal SR is kept at the "1" level for a certain period of time and the NMOS switch M21 is turned on. Output data signal 2 on signal line 17 is sent to diagnostic bus line 22 via NMOS switch M21. Table 1 shows the truth table for the above operation modes.

〔Effect of the invention〕

As described above, according to the present invention, the wiring area,
It is possible to obtain a semiconductor integrated circuit device in which the chip size can be reduced, the speed of diagnostic signals can be improved, and variations thereof can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a basic cell according to an embodiment of the invention, FIG. 2 is a wiring diagram of a logic cell according to an embodiment of the invention, and FIG. 3 is a circuit showing the overall configuration of an embodiment of the invention. 4 is a chip plan view showing a conventional example, FIG. 5 is a block diagram of an FF with a diagnostic latch, FIG. 6 is a circuit diagram of the FF, and FIG. 7 is a circuit diagram supplementing FIG. 6. , FIG. 8 is a circuit configuration diagram showing the divided diagnosis method, and FIG. 9 is a circuit diagram supplementing FIG. 8. 3...Basic cell, 4...Basic cell column, 26...
Power supply potential line, 27... Ground potential line, 304, 30
5...Diagnostic control signal line.

Claims (1)

[Scope of Claims] 1. A large number of basic cells made of functional elements are arranged in one direction on one main surface to form a basic cell row, and a plurality of the basic cell rows are arranged in parallel in a direction perpendicular to the basic cell row. A semiconductor integrated circuit device comprising: a semiconductor chip formed by a semiconductor chip; and first and second power supply lines extending across all the basic cells constituting the basic cell string and provided substantially parallel to the basic cell string. A diagnostic control signal wiring for diagnosing the functional element is provided across all the basic cells constituting the basic cell array and approximately parallel to the first and second power supply lines, and A semiconductor integrated circuit device, wherein at least one basic cell in the cell array constitutes a driver cell that connects the diagnostic control signal wiring and the input buffer circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the driver cells are comprised of multiple stages, and the driver cells in the previous stage are connected to multiple driver cells in different basic cell rows. Device. 3. The semiconductor integrated circuit device according to claim 1, wherein the driver cell is provided at one end of the basic cell row. 4. Claim 1 provides that at least one basic cell in the basic cell array constitutes a 3-state buffer cell that connects the diagnostic control signal wiring and the output buffer circuit. Features of semiconductor integrated circuit devices. 5. The semiconductor integrated circuit device according to claim 4, wherein the three-state buffer cell is provided at the other end of the basic cell row.