JPH0520896A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To output correct data from an ECC so that data read from blocks except blocks including a defective word line of a plurality of data to be applied to the ECC are all correct if a defective position occurs only in each one block even if a disconnection and a short-circuit of a word line occur in a either of a plurality of blocks. CONSTITUTION:In a mask ROM with an error correcting function, in which 32-bit data to be simultaneously read externally and 32-bit parity data necessary to correct an error of one bit occurring in the data are input to an ECC 9, memory cell arrays l, 2 are divided to a plurality of blocks DB0-DB7, DP0-DP3 corresponding to a plurality of data D0-D7, P0-P3 to be input to the ECC9. And, each block has a plurality of word lines WL independent from all other blocks. One word line WL is activated by the plurality of blocks at the time of reading data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an error correction circuit.

[0002]

2. Description of the Related Art In a semiconductor memory device, when data is read from a memory cell array, if an error occurs in the read data, an error correction circuit (ErrorCor).
There is a device in which a direction circuit (hereinafter abbreviated as ECC) is built in.

Generally, whether or not there is an error in data of an arbitrary bit length can be detected by adding 1-bit data called a parity bit to this data.
Such a detection method is called a parity check. According to the parity check, the data of the parity bit is set such that the number of bits of the data “1” is even (or odd) among the data of which an error is to be detected and the data of the parity bit. Therefore, it is possible to detect the presence or absence of a 1-bit error by checking the number of bits that are data “1” among all the bits including the parity bit.

However, since the parity check cannot detect which bit has an error, the error cannot be corrected. Therefore, in order to detect and correct an error, a plurality of bits of data are added to the data in which the error is to be detected.
This multi-bit data is a redundant bit for detecting and correcting an error and is called a check bit. Hereinafter, the check bit data will be referred to as parity data.
Data to which a parity bit is added is called an error correction code.

In general, 1 generated in 32-bit data
To correct a bit error, 6-bit parity data needs to be added, and to correct a 1-bit error that has occurred in 8-bit data, 4-bit parity data is required.

The ECC corrects an error in the read data by performing a predetermined operation on the read data and the parity data corresponding to the read data, and corrects the corrected data into the final read data. Output as. The principle of error correction in ECC and its implementation method are well known, and are described in, for example, the document “Interface”, August 1984, pp. 236 to 250, detailed description is omitted here.

Such an ECC has the following problems during its manufacturing process.
Data is written in advance and only data can be read out after manufacturing, so-called mask ROM (Read Only).
Currently, it is often applied to Memory). recently,
ECC is an EEPROM (Electrically
Erasable and Programmable
It has been proposed to apply it to a storage device such as an e ROM) in which data can be rewritten after manufacturing.

FIG. 5 shows a conventional mask RO having an ECC.
It is a schematic block diagram which shows an example of the whole structure of M. Next, the configuration of a conventional mask ROM having an ECC will be described with reference to FIG.

The mask ROM is a memory cell array (hereinafter, referred to as a memory cell array) in which original data to be read out is stored.
It includes a normal memory cell array) 1 and a memory cell array (hereinafter referred to as a parity memory cell array) 2 in which parity data necessary for correcting an error in data read from the memory cell array 1 is stored.

The normal memory cell array 1 includes eight blocks DB0 to DB7 corresponding to 8-bit data.
Similarly, the parity memory cell array 2 has four blocks DP0 to DP corresponding to 4-bit parity data.
Including 3.

A plurality of (for example, 1024) word lines WL
Are provided commonly to the normal memory cell array 1 and the parity memory cell array 2. Multiple (eg 128
Bit line BL of 12 blocks DB0 to DB
7, DP0 to DP3.

These word lines WL are connected to the X decoder 3, and these bit lines BL are connected to the Y gate 7.

The address buffer 5 waveform-shapes and amplifies the address signal externally supplied to the address input terminals A0 to An, and supplies it to the X decoder 3 and the Y decoder 4.

The X decoder 3 decodes the address signal from the address buffer 5 to generate the word lines W.
Of L, only one corresponding to this address signal is activated.

The Y decoder 4 decodes the address signal from the address buffer 5 and controls the Y gate 7.

Specifically, the Y gate 7 includes eight blocks YGD0 to YGD7 corresponding to the eight memory cell array blocks DB0 to DB7 and four blocks YGP0 corresponding to the four parity memory cell array blocks DP0 to DP3. ~ YGP3. Each of the eight blocks YGD0 to YGD7 in the Y gate 7 responds to the decode output of the Y decoder 4 to electrically connect only one of the bit lines BL of the corresponding normal memory cell array block to the sense amplifier group 8. Connect to each other. Similarly, each of the remaining four blocks YGP0 to YGP3 in the Y gate 7 is
In response to the decoded output of the Y decoder 4, only one of the bit lines BL of the corresponding parity memory cell array block is electrically connected to the sense amplifier group 8.

The sense amplifier group 8 includes eight Y gate blocks YGD0 to YDG7 and four YT gate blocks Y.
Eight sense amplifiers SAD0 to SAD7 and four sense amplifiers SA corresponding to GP0 to YGP3, respectively.
P0 to SAP3 are included. These twelve sense amplifiers SAD0 to SAD7 and SAP0 to SAP3 in total sense and amplify a signal on one bit line BL electrically connected by the corresponding Y gate block, and EC
Give to C9.

Regular memory cell array blocks DB0-D
B7 and parity memory cell array block DP
Each of 0 to DP3 includes memory cells MC arranged in a matrix of a plurality of rows and a plurality of columns. The memory cells MC arranged in the same row are connected to the same word line WL, and the memory cells MC arranged in the same row are connected to the same bit line BL.

When one word line WL is activated, a potential change according to the storage data of each memory cell MC connected to this word line WL is applied to the bit line BL connected to that memory cell MC. Appears. Therefore, assuming that the number of memory cell columns included in each of the normal memory cell array blocks DB0 to DB7 and each of the parity memory cell array blocks DP0 to DP3 is N columns, the Y gate 7 is connected to the same word line WL (12 The storage data of the (× N) memory cells MC are simultaneously given. However, each Y provided corresponding to the regular memory cell array 1
The gate blocks YGD0 to YGD7 electrically connect only one bit line BL in the corresponding memory cell array block to the corresponding sense amplifier, and each Y gate block YG provided corresponding to the parity memory cell array 2 is provided.
P0 to YGP3 connect only one bit line BL in the corresponding parity memory cell array block to the corresponding sense amplifier. As a result, the sense amplifier group 8 includes the memory cell array block DB0 to the Y gate block YG.
One of the N data signals applied to D0, the memory cell array block DB1 to the Y gate block YG
One of the N data signals given to D1,
And one of the N data signals provided to the memory cell array blocks GB7 to Y gate block YGD7, the parity memory cell array blocks DP0 to Y
One of the N data signals supplied to the gate block YGP0, ..., And one of the N data signals supplied from the parity memory cell array block DP3 to the Y gate block YGP3 are amplified, respectively. ,
Input signals D0, D1, ..., D7, D0 to the ECC9,
..., P3.

In this way, the storage data of one memory cell MC connected to the same word line WL is read to the ECC 9 from each of the normal memory cell array blocks DB0 to DB7 and each of the parity memory cell array blocks DP0 to DP3. ..

Therefore, 12-bit data D0 to D7 and P0 to PO3 to be simultaneously read from the normal memory cell array 1 and the parity memory cell array 2 to the ECC 9 are provided.
1-bit error detection and correction
Predetermined parity data, which is realized by the arithmetic operation executed by 9, is written in the parity memory cell array 2 in advance at the time of manufacturing. Of course, the parity data to be written in the parity memory cell array 2 is determined according to the storage data in the memory cell array 1.

Data to be externally read is written in the regular memory cell array 1 in advance at the time of manufacture. However, the data read from the memory cell array 1 may not always be the correct data to be read due to various causes. In such a case, the operation of the ECC 9 corrects the data read from the memory cell array 1 to correct data.

Therefore, the ECC 9 is simultaneously provided with 8-bit data which should originally be read out and 4-bit parity data P0 to P3 necessary for correcting a 1-bit error occurring in the 8-bit data. Be done. EC
The C9 performs a predetermined operation on the 8-bit data D0 to D7 and the 4-bit parity data P0 to P3 to obtain any one of the read 8-bit data D0 to D7. If there is an error, correct it. If there is no error, the output buffer 10
Give to. The output buffer 10 outputs the output signal of the ECC 9,
That is, the corrected 8-bit data D0 'to D7'
Is amplified and supplied to the data output terminals DT0 to DT7.

The output buffer 10 includes eight buffer circuits OUT0 to OUT7 corresponding to the 8-bit data D0 'to D7' output from the ECC 9. These eight buffer circuits OUT0 to OUT7 are respectively connected to eight data output terminals DP0 to DP7.

The control circuit 6 controls the operations of the address buffer 5 and the output buffer 10 in response to a control signal externally supplied to the control signal input terminal CTL.

FIG. 6 is a partial circuit diagram showing a specific configuration example of the memory cell array of the mask ROM. Next, a typical memory cell array structure of the mask ROM will be described with reference to FIG.

FIG. 6 shows the case of a so-called NAND type ROM in which the data stored in the memory cell connected to the word line is read when the potential of the word line becomes low level.

In FIG. 6, the MOS transistors to which the depletion type is always applied are shaded. 1 between each bit line BL1, BL2 and ground GND
Eight N-channel MOS transistors MT, STD, S
A plurality of TD series connection circuits are connected in parallel with each other.
Of these 18 transistors, each of 16 transistors MT connected to the side close to the ground GND functions as one memory cell MC.

Two serial connection circuits connected to the same bit line are connected to a common word line in units of two. That is,
Each of the word lines WL1 to WL32 is commonly connected to the gates of the two memory transistors MT connected to the bit line BL1, the gates of the two memory transistors MT connected to the bit line BL2, ....

As described above, actually, in the normal memory cell array and the parity memory cell array, the plurality of memory transistors MT are arranged in a matrix of rows and columns, and the memory transistors M arranged in the same column.
Ts are connected in series to each other in units of a predetermined number (16 in the above example), while memory transistors MTs arranged in the same row are connected to the same bit line in units of 2. That is, actually, two memory cell columns are provided corresponding to each bit line. Further, two signal lines SG1 to SG4 different from the word lines and extending in the row direction are provided for every 16 memory cell rows. Hereinafter, this signal line is referred to as a select gate line.

The gates of the two transistors STE and STD, which are connected in series with each other, respectively have corresponding gates of 2
It is connected to one and the other of the select gate lines SG1 to SG4. Two memory cell columns adjacent to each other have different types (depletion type or enhancement type) of memory cells connected to the same select gate line.

The type of memory transistor MT is determined according to the data to be stored therein. Specifically, the memory transistor MT in which the data “0” is to be stored is set to the enhancement type, and the memory transistor MT in which the data “1” is to be stored is set to the depletion type. The type of each memory transistor MT is set by adjusting the impurity concentration in the channel region of the memory transistor MT by ion implantation during manufacturing.

Each of the bit lines BL1 and BL2 and each of the word lines WL1 to WL32 in FIG. 6 corresponds to one bit line BL and one word line WL in FIG. 5, respectively.

The X decoder 3 of FIG. 5 actually activates one word line and one select gate line in response to the address signal from the address buffer 5. In the case of the NAND type ROM, the potentials of the activated select gate line and the activated word line are high level (higher than the threshold voltage of the enhancement type transistor used as the memory transistor), and Low level, that is, 0V.

The enhancement type MOS transistor is in the OFF state when the gate voltage is 0V, and the depletion type MOS transistor gate voltage is 0V.
Is in the ON state. Therefore, for example, in FIG. 6, when the potential of the word line WL1 is set to the low level and the potentials of all the other word lines are set to the high level, the memory transistor MT connected to any word line other than the word line WL1. Is also turned on. On the other hand, ON / OFF of each memory transistor MT connected to the word line WL1
OFF is determined according to the type of the transistor. That is, the enhancement type memory transistor MT connected to the word line WL1 is turned off, but the depletion type memory transistor MT connected to the word line WL1 is turned on.

On the other hand, the potential of one of the select gate lines SG1 and SG2, SG1, is at the high level,
If the potentials of all the other select gate lines are low level, only the enhancement type STE among the transistors connected to the select gate lines other than the select gate line SG1 is turned off, and the depletion type STD. Is turned on. On the other hand, all the transistors STD and STE connected to the select gate line SG1 are turned on.

Therefore, the potential of each bit line BL1, BL2 is the same as that of the two memory cell columns connected to it.
Included in the one to which the enhancement type transistor STE is connected to the select gate line SG1, and
It changes according to the type of the memory transistor MT connected to the activated word line WL1. That is, if this memory transistor MT is an enhancement type, no current flows between the corresponding bit line and the ground GND. On the contrary, if the memory transistor MT is a depletion type, a current flows from the corresponding bit line to the ground GND. The case where a current flows through the bit line corresponds to data "1", and the case where no current flows through the bit line corresponds to data "0". Therefore, the storage data of one memory cell connected to the activated word line WL1 is read to each bit line.

On the contrary, if the potential of the select gate line SG2 is high level and the potentials of all other select gate lines are low level, both the transistors STD and STE connected to the select gate line SG2 are in the ON state. , The enhancement type transistor of the two types of transistors STD and STE connected to the select gate line other than the select gate line SG2 is turned off, and the depletion type transistor S
TD is turned on. Therefore, in this case, contrary to the above case, the presence / absence of a current flowing in each bit line BL1, BL2 is determined by the depletion type in the select gate line SG1 of the two memory cell columns connected thereto. Of the memory transistor MT connected to the word line WL1 and included in the memory cell column connected to the transistor STD.

Each sense amplifier SAD0 to SAD in FIG.
Specifically, AD7 and SAP0 to SAP3 detect the presence / absence of current flowing in the bit line electrically connected via the Y gate 7.

In this way, by activating one word line and one of the two select gate lines provided corresponding to this word line, each bit line is Stored data in either one of the two memory cells MT connected to the bit line and the one word line appears.

In the above-mentioned mask ROM, the output of the X decoder 3 is given only in one direction, but the memory cell array is divided into two blocks, and the X decoder has these two blocks.
It may be placed between these two blocks to provide the output to one block. FIG. 7 is a schematic block diagram showing the overall configuration of a mask ROM with an error correction function having such a configuration.

FIG. 7 exemplifies a case where the data to be simultaneously read to the outside is 8-bit data.

Referring to FIG. 7, when the mask ROM is manufactured, original data and parity data to be externally read are both prewritten in memory cell array blocks 10a and 10b.

Memory cell array blocks 10a and 1
0b is a plurality (here, four) of sub-blocks 10a-0 to 10a-3 and 10b-0 to 10b-3, respectively.
including.

Each of the sub blocks 10a-0 to 10a-3,
Reference numerals 10b-0 to 10b-3 correspond to a total of 12-bit data of 8-bit data to be simultaneously read externally and 4-bit parity data necessary to correct an error in the 8-bit data. It includes 12 memory cell columns. That is, each sub-block 10a-0 to 10a-
3, 10b-0 to 10b-3, the first column, 2
The memory cells in the 8th column, ...
The data of the least significant bit, the data of the second most significant bit, ..., The data of the most significant bit of the data originally to be read out are stored, and the ninth column, the tenth column ,.
The memory cell in the second column stores the least significant bit data, the second most significant bit data, ..., And the most significant bit data of the 4-bit parity data corresponding to the 8-bit data. ing.

In the memory cell array block 10a, the word lines WL are sub-blocks 10a-0 to 10a-.
3 are provided in common, and similarly, in the memory cell array block 10b, the word line WL has
It is commonly provided to -0 to 10b-3. The word lines WL of the memory cell array block 10a and the word lines WL of the memory cell array block 10b have a one-to-one correspondence.

Memory cell array blocks 10a and 1
The circuit configuration inside 0b is the same as that of the above-mentioned mask ROM, and therefore its explanation is omitted. In addition, in FIG.
As in the case of, the select gate line is not shown for simplicity.

Further, the address buffer 5, the control circuit 6,
Sense amplifier group 8, ECC 9, and output buffer 10
The operation of is similar to that of the mask ROM described above.

In the mask ROM of this example, the X decoder 3
Responds to an address signal from address buffer 5 to select and activate one word line WL from one of memory cell array blocks 10a and 10b. As a result, in one of the memory cell array blocks 10a and 10b, the storage data of the memory cells MC arranged in the same row corresponds to the corresponding bit line B.
Appears in L.

The Y gates 7a and 7b are connected to the Y decoder 4
Of the sub-blocks 10a-0 in the memory cell array block 10a under the control of the decode output of the sub-blocks 10a-0.
12-bit lines BL included in any one of 10 to 10-a-3 and the memory cell array block 10
Twelve bit lines BL included in any one of the sub-blocks 10b-0 to 10b-3 in b are selectively electrically connected to the sense amplifier group 8. Specifically, Y
The decoder 4 is arranged so that the 12 bit lines BL and the sense amplifier group 8 are electrically connected to each other only through one of the Y gates 7a and 7b.
And 7b.

Therefore, the sense amplifier group 8 includes sub-blocks 10a-in the memory cell array block 10a.
0-10a-3 or memory cell array block 10b
Only the 12-bit data D0-D7 and P0-P3 appearing on the 12 bit lines BL of any one of the sub-blocks 10b-0 to 10b-3 in the sub-blocks are supplied to the sense amplifier group 8. .. Of the 12-bit data, 8-bit data D0 to D7 read from a memory cell provided for storing the original data to be externally read and an error of the 8-bit data are corrected. The 4-bit data P0 to P3 read from the memory cells provided for storing the parity data necessary for the data are amplified by the sense amplifier group 8 and given to the ECC 9 as 8-bit data D0.
-D7 and parity data P0-P3.

As a result, the data output terminals DT0 to DT7
Even if any one bit of the 12-bit data read from the memory cell arrays 10a and 10b to the sense amplifier group 8 has an error, the original data D0 to D
7 is supplied with the correct logic value.

Next, the structure of the X decoder 3 in the conventional mask ROM will be described with reference to FIGS. 8 and 9. FIG. 8 is a block diagram showing a schematic configuration of the X decoder 3 in the figure. FIG. 9 is a partial circuit diagram showing the configuration of the X decoder 3 in FIG. 7 in more detail.

Referring to FIG. 8, X decoder 3 includes predecoder 30 and a plurality of decoder blocks 31 provided commonly to memory cell array blocks 10a and 10b.
Including and Memory cell array blocks 10a and 10
If b is configured as shown in FIG. 6, one decoder block 31 is provided corresponding to every 16 memory cell rows.

The predecoder 30 includes the address buffer 5
The address signal from the decoder is decoded to match the input to the decoder block 31. In response to the decoder output of the predecoder 30, any one of the plurality of decoder blocks 31 has one word line (not shown) connected to one of the corresponding 16 memory cell rows. No)
And one of the two select gate lines provided corresponding to the 16 memory cell rows are activated.

Referring to FIG. 9, each decoder block 31
Is a main decoder unit 310 and a sub-decoder unit 311.
And 312.

Each main decoder section 310 is, for example,
The NAND gate 400 and the NAND gate 4 which receive some of the outputs of the predecoder 30 of FIG.
An inverter 410 for inverting the output of 00 is included. In each decoder block 31, the output of the inverter 410 of the main decoder unit 310 is commonly applied to the sub decoder units 311 and 312.

Each of the sub-decoder units 311 and 312 receives, for example, the output of the corresponding main decoder unit 310 at its gate by 16 N-channel MOS transistors 420.
And two 2-input NAND gates 430 and 440
And two inverters 450 and 460 that invert the outputs of these two NAND gates 430 and 440, respectively. Each of these two NAND gates 430 and 440 has a corresponding main decoder unit 310.
Is received at one input end, and the output of the predecoder 30 is received at the other input end. 16 transistors 420
Are corresponding 16 word lines WL1 to WL3, respectively.
2 and 16 outputs of the predecoder 30. The outputs of the two inverters 450 and 460 respectively correspond to the two corresponding select gate lines SG to S.
Given to G4.

The predecoder 30 includes a subdecoder section 31.
In either one of 1 and 312, only one of the two signals provided from predecoder 30 to NAND gates 430 and 440 respectively, and
Only one of the signals provided from predecoder 30 to transistor 420 is high and low, respectively, and on the other hand, predecoder 30
To NAND gates 430 and 440 are both at a low level, all signals provided from predecoder 30 to transistor 420 are at a high level, and any one of NAN
The address signal from the address buffer 5 is decoded so that only the signal supplied from the predecoder 30 to the D gate 400 becomes high level.

Therefore, only in one of the decoder blocks 31, the sub-decoder sections 311 and 3 are provided.
16 transistors 42 in one of the 12
One of the 0s applies a high level potential to one select gate line, and two inverters 450 and 46 are provided.
One of 0s gives a low level potential to one word line. In each of the other sub-decoder sections, the 16 transistors 420 apply high-level potentials to the 16 word lines, respectively, and the two inverters 45
0 and 460 apply a low level potential to the two select gate lines.

As a result, the memory cell array block 10
In one of a and 10b, stored data of a plurality of memory cells arranged in the same row appears on the corresponding bit line. On the other hand, however, all enhancement-type transistors (transistor STE in FIG. 6) connected to the select gate line are turned off, so that the stored data of any memory cell does not appear on the bit line.

[0062]

As described above, in the conventional mask ROM having the error correction function, the data of a plurality of bit lengths read from the memory cells connected to the same word line has only a 1-bit error. It is configured to be input to the ECC as a correctable error correction code. Therefore, the error correction function of the conventional mask ROM works effectively only when there is a 1-bit error in the data read simultaneously from a plurality of memory cells arranged in the same row.

Next, a conventional mask ROM with an error correction function
A situation in which a correctable error occurs due to will be specifically described with reference to FIG.

First, in FIG. 5, a total of 12 memory cell array blocks DB0 to DB7 in which original data to be read out are stored and four memory cell array blocks DP0 to DP3 in which parity data is stored. Only one of the blocks contains a memory cell in which an element having a characteristic according to the data to be originally stored is not used (so-called bit defect), or the use environment or the time-dependent 12 signal transmission paths (Y gate blocks YGD0 to YGD7, YGP0 to YGP3) for transmitting 12-bit data from the ECC from the normal memory cell array 1 and the parity memory cell array 2 due to a failure of an internal circuit due to deterioration.
And sense amplifiers SAD0 to SAD7, SAP0 to SAP
It is assumed that a failure has occurred in the signal transmission path of any one of (3, etc.).

In such a case, 1 read by the ECC 9
It is considered that only one of the 2-bit data D0 to D7 and P0 to P3 has an error, and the other 11-bit data is all correct. Therefore, E
CC9 can detect and correct this one bit error.

Next, in FIG. 5, only in any one of the 12 memory cell array blocks DB0 to DB7 and DP0 to DP3, the bit line BL
In addition, it is assumed that a disconnection or a short circuit has occurred at the manufacturing stage or in the use process (so-called bit line defect).

In such a case, when any of the plurality of memory cells MC connected to the defective bit line is selected as the memory cell to which data is to be read, this defective bit line is selected by the corresponding Y gate block. Sense amplifier group 8
Electrically connected to. Therefore, the ECC from the memory cell array block having the defective bit line BL
No data is read at 9. However, it is considered that the data is read to the ECC 9 from each of the remaining 11 memory cell array blocks. Therefore, also in this case, the ECC 9 can output correct 8-bit data.

In other words, among the failures in the memory cell array and its peripheral circuits, the ECC that causes a random 1-bit error in the 12-bit data D0 to D7 and P0 to P3 to be given to the ECC 9 is ECC.
9 can correct this error. Ie EC
The C9 can enable such a defective mask ROM as a normal mask ROM.

As can be seen from the above, according to the conventional mask ROM with an error correction function, an error in read data due to a failure in the bit line direction in the memory cell array can be corrected with a considerably high probability. However, it is impossible to correct the read data error due to the word line direction failure (so-called word line defect) with a high probability.

For example, in FIG. 5, it is assumed that one word line WL is broken at the position P in the figure.

In such a case, even if the memory cell row connected to this broken word line WL is selected as the memory cell row from which data is to be read, this word line WL is not activated. Therefore, the stored data of any of the memory cells included in the selected memory cell row does not appear correctly on the corresponding bit line BL. As a result, ECC9
12-bit data D0 to D7, P0 to P
ECC9 is correct 8 because all 3 are incorrect
It becomes impossible to output the bit data D0 'to D7'.

Further, in FIG. 5, one word line WL
It is assumed that there is a disconnection at position Q in the figure.

In such a case, when the memory cell row connected to this broken word line WL is selected as the memory cell row from which data is to be read, this word line WL is selected.
Of these, the portions included in the five memory cell array blocks DB0 to DB4 close to the X decoder 3 are supplied with a potential for activating them from the X decoder 3, but the remaining 7
Memory cell array blocks DB5 to DB7, DP0
The part contained in ~ DP3 is not activated. Therefore, among the memory cells MC connected to the word line WL, the seven memory cell array blocks DB5 to DB
7, data is not newly read from those included in DP0 to DP3. As a result, 12 is input to the ECC 9.
Of the bit data D0 to D7 and P0 to P3, seven memory cell array blocks DB5 to DB7 and DP0 to D
7-bit data D5 to D7, P0 obtained from P3
P3 is all wrong. Therefore, even in such a case, the ECC 9 cannot output correct data.

When one word line WL is short-circuited with another adjacent word line, data cannot be correctly read from any memory cell MC connected to this word line WL.

As described above, if the word line WL is defective, error correction by the ECC 9 becomes almost impossible.

Also in the mask ROM of FIG. 7, if any of the word lines WL is disconnected for some reason or short-circuited with the adjacent word line, the memory cell row connected to this word line starts , ECC9, it is extremely unlikely that all 11 data out of 12 data D0 to D7 and P0 to P3 to be given to ECC9 will be correctly read.

On the other hand, since the number of memory cells arranged in one row is increasing with the increase in capacity of semiconductor memory devices in recent years, the length of each word line is also increasing. Such an increase in the length of the word line increases the risk of the word line being broken or short-circuited during the manufacturing process.

Therefore, with the increase in capacity of semiconductor memory devices in recent years, it is almost impossible to remedy errors that occur in read data due to word line defects, so the yield is low, which is a problem of the conventional mask ROM. Will become more serious.

Therefore, an object of the present invention is to solve the above problems and provide a high yield semiconductor memory device capable of sufficiently relieving not only a bit defect and a bit line defect but also a word line defect. It is to be.

[0080]

In order to achieve the above object, a semiconductor memory device according to the present invention includes a first plurality of data which simultaneously stores a first plurality of data to be externally read. And a second plurality of blocks each storing a second plurality of parity data predetermined according to the first plurality of data. Each block has a plurality of memory cells arranged in a plurality of rows and a plurality of word lines provided corresponding to the plurality of rows and connected to the memory cells arranged in a corresponding row. Including. The semiconductor memory device according to the present invention further selects one word line from each of the first plurality of blocks, reads the data stored in the memory cell connected to the selected word line, and Means for selecting one word line from each of the second plurality of blocks and reading the stored data of the memory cells connected to the selected word line, and the first plurality of means based on the read data. Correction unit for detecting and correcting an error in the data read from each of the blocks.

[0081]

As described above, in the semiconductor memory device according to the present invention, a plurality of data to be given to the correction means are stored in the individual memory cell array blocks, and the word lines are individually provided in the plurality of blocks. It is configured to be.

Therefore, even if any one of the plurality of blocks includes a defective word line such as a disconnection or a short circuit, data is correctly read from the other blocks. Therefore, of the first plurality of data and the second plurality of data supplied from the reading means to the correcting means, all data except at least one data read from the block having the defective word line are correct data. ..

[0083]

1 is a schematic block diagram showing the overall construction of a mask ROM with an error correction function according to an embodiment of the present invention.

Referring to FIG. 1, like the conventional mask ROM shown in FIG. 5, this mask ROM has a memory cell array in which original data to be externally read and parity data for error correction are different from each other. Pre-stored in 1 and 2. The memory cell array 1 includes eight block DB0 corresponding to 8-bit data to be simultaneously read out.
~ It is divided into DB7. The memory cell array 2 is
It is divided into four blocks DP0 to DP3 corresponding to 4-bit parity data corresponding to bit data.

However, in this mask ROM, unlike the prior art, word lines WL are individually provided for each of these memory cell array blocks DB0 to DB7 and DP0 to DP3, and these word lines WL are arranged in one memory cell array. A main X decoder 3a and sub X decoders 3b-1 to 3b- for individually driving each block.
6 is provided.

Since the structure and operation of the other parts of this mask ROM are the same as those of the mask ROM shown in FIG. 5, description thereof will be omitted.

Main X decoder 3a decodes the address signal from address buffer 5 and outputs a signal for instructing from which memory cell row the data is read. The output signal of the main X decoder 3a is given to all the sub X decoders 3b-1 to 3cb-6.

Four sub X decoders 3b-1 to 3b-4
Are provided corresponding to two adjacent blocks in the memory cell array 1. Similarly, the remaining two sub-X decoders 3b-5 and 3b-6 are provided corresponding to two blocks adjacent to each other in the parity memory cell array 2.

Sub X-decoder 3b-1 responds to the output signal of main X-decoder 3a and the address signal from address buffer 5 and word line WL included in one of the corresponding two memory cell array blocks DB0 and DB1. From the word line WL included in the other,
One of the memory cell rows designated by the main X decoder 3a is activated.

Similarly, sub X decoder 3b-2 responds to the address signals from main X decoder 3a and address buffer 5 in response to memory cell array block DB2.
One of the word lines WL in the memory cell array DB3 and the word line WL in the memory cell array DB3 corresponding to the memory cell row designated by the main X decoder 3a is selected and activated.

Similarly, sub X decoder 3b-3 responds to the address signals from main X decoder 3a and address buffer 5 in response to memory cell array block DB4.
From the word line WL in the memory cell array block DB5 to the main X decoder 3
One of the memory cell rows designated by a is selected and activated.

Similarly, the sub X decoder 3b-4 outputs the output signal of the main X decoder 3a and the address buffer 5.
In response to the address signal from the memory cell array block DB6, one word line WL in the memory cell array block DB6 and one word line WL in the memory cell array block DB7 are selected corresponding to the memory cell rows designated by the main X decoder 3a. And activate. Similarly, the sub X decoder 3
b-5 is responsive to the output signal of the main X decoder 3a and the address signal from the address buffer 5 to select from the word line WL in the parity memory cell array block DP0 and the word line WL in the parity memory cell array block DP1, respectively. One of the memory cell rows designated by the main X decoder 3a is selected and activated.

Similarly, the sub X decoder 3b-6 outputs the output signal of the main X decoder 3a and the address buffer 5.
In response to the address signal from the word line WL in the parity memory cell array block DP2 and the word line WL in the parity memory cell array block DP3, one corresponding to the memory cell row designated by the main X decoder 3a. Select to activate.

Therefore, the sub X decoders 3b-1 to 3b-1 to 3b-3
Each of b-6 simultaneously activates two word lines WL arranged in the same row of the corresponding two memory cell array blocks. As a result, the main X decoder 3a
All the word lines connected to one memory cell row indicated by, that is, 12 word lines WL in the same row included in each of the 12 memory cell array blocks DB0 to DB7 and DP0 to DP3 are activated at the same time. Be converted.

Therefore, as in the conventional case, the data stored in the memory cells MC arranged in the same row are simultaneously transmitted to the Y gate 7 through the corresponding bit line BL. Therefore, from the sense amplifier group 8 to the ECC 9, the 8-bit data D0 to D7 to be simultaneously read to the outside and the 4-bit data for detecting and correcting the error of the 8-bit data are provided.
Bit parity data P0 to P3 are supplied.

As described above, in this embodiment, each of a plurality of data to be output to the outside simultaneously and each of a plurality of parity data necessary to detect and correct an error in the plurality of data. One memory cell array block is provided in each memory cell array block, and each memory cell array block includes a word line independent of the other memory cell array blocks. Therefore, an error in the read data caused by the disconnection of the word line WL or a short-circuit with an adjacent word line has a high probability like the error in the read data due to a bit defect or a bit line defect. To be corrected.

That is, the memory cell array blocks DB0 to DB7 and DP0 to D having 12 defective word lines WL are provided.
If it exists only in any one of P3, even if the memory cell row connected to this defective word line WL is instructed by the main X decoder 3a, 12 cells connected to this memory cell row are connected. The stored data of all the memory cells connected to the 11 word lines except the defective word line WL among the word lines WL of 6 appear correctly on the corresponding bit line BL. Therefore, since only the 1-bit data read from the memory cell array block including the defective word line can be incorrect data among the data D0 to D7 and P0 to P3 supplied to the ECC 9, the ECC 9 is If there is an error in the data read from this memory cell array block, it can be corrected and correct 8-bit data D0'-D7 'can be output.

For example, of these memory cell array blocks DB0 to DB7 and DP0 to DP3, a part of the word line WL in the memory cell array block DB3 is disconnected, and the other memory cell array blocks DB0 to DB3.
2, DB4 to DB7, word lines WL in DP0 to DP3
Assumes that there is no defect.

In such a case, the broken word line W
When the memory cell row connected to L is designated by the main X decoder 3a, 1 connected to this memory cell row.
Of the two word lines WL, one (or all) of the one included in the memory cell array block DB3 is not activated, but the other memory cell array blocks DB0 to DB
All of 11 parts included in 2, DB4 to DB7 and DP0 to DP3 are all activated. Therefore, one of these 12 memory cell array blocks
Only in one memory block DB3, there is a possibility that the stored data of the memory cells in the designated memory cell row may not appear correctly in the corresponding bit line BL, and in the remaining 11 memory cell array blocks, the designated memory cell It is considered that the data stored in the memory cells in the row appear correctly on the corresponding bit line BL. Therefore EC
12-bit data D0 to D7, P0 given to C9
Out of P3, at least 11 bits of data D3 are all correct.

Further, for example, in one memory cell array block DB4, the word lines WL adjacent to each other are short-circuited, and the other memory cell array block DB0.
It is assumed that there is no defect in the word line WL in any of DB3 to DB3, DB5 to DB7, and DP0 to DP3.

In such a case, the memory cell row connected to the shorted word line WL is the main X decoder 3
When instructed by a, the storage data of the memory cell of the instructed memory cell row does not appear correctly on the bit line BL of the memory cell array block DB4, but the other memory cell array blocks DB0 to DB3, DB5 to DB5.
7 and DP0 to DP3, bit line BL
Then, the stored data of the memory cell of the designated memory cell row appears correctly. Therefore, even in this case,
12-bit data D0 to D7 input to the ECC 9,
Of P0 to P3, the only incorrect data is the data D4 read from the memory cell array block DB4.

As described above, according to the present embodiment, the defective word line does not affect the word lines in the memory cell array blocks other than the memory cell array block including this word line. The short circuit is these 12 memory cell array blocks DB0 to DB
7 and DP0 to DP3, if the occurrence location is only in one memory cell array block, 12 pieces of data D provided to the ECC 9
At least 11 data of 0 to D7 and P0 to P3 are correct. Therefore, an error that occurs in read data due to a word line defect can be corrected by the ECC 9 with high probability.

It should be noted that if the bit defect or the bit line defect is EC
Since the influence on the input data D0 to D7 and P0 to P3 to C9 is the same as that in the conventional case, an error occurring in the read data due to a bit defect or a bit line defect is corrected by the ECC 9 with a high probability.

Since each memory cell array block is configured to have an individual word line, the length of each word line is shortened. On the other hand, these word lines are not driven by the common X decoder. That is, the word lines WL in the memory cell array blocks DB0 and DB1 and the memory cell array blocks DB2 and DB
The word line WL in 3 and the memory cell array block DB
4 and DB5, the word lines WL in the memory cell array blocks DB6 and DB7, the word lines WL in the memory cell array blocks DP0 and DP1, and the memory cell array blocks DP2 and DP3.
Sub-decoders 3b-1, 3b-2, 3b-3, 3b-4, 3b whose word lines WL are different from each other.
It is driven by -5 and 3b-6. Therefore, the total load capacitance that each sub-X decoder must drive is smaller than the total load capacitance that the X decoder 3 in FIG. 5 must drive.

Therefore, according to this embodiment, the time required for changing the potential of the word line in response to the decoder output, that is, the time required for charging / discharging the word line in response to the decoder output is shortened as compared with the conventional case. As a result, the time from when the address signal is externally applied to the address input terminals A0 to An until the stored data of the memory cell corresponding to the address signal appears on the bit line BL is shortened,
As a result, there is an effect that the access time is improved.

Next, the main X decoder 3a and the sub X
Specific configurations of the decoders 3b-1 to 3b-6 will be described with reference to FIGS. 2 to 4. FIG. 2 shows a main X decoder 3a and sub X decoders 3b-1 to 3b-.
6 is a block diagram showing a schematic configuration example of No. 6; FIG. FIG. 3 is a circuit diagram showing in detail a configuration example of the main X decoder 3a.
FIG. 4 is a circuit diagram showing in detail a configuration example of the sub X decoders 3b-1 to 3b-6.

2 to 4 show the case where the internal structure of each of the memory cell array blocks DB0 to DB7 and DP0 to DP3 is that shown in FIG.

Referring to FIG. 2, main X decoder 3a
Includes a predecoder 30a and a plurality of main decoder blocks 31a.

The main decoder block 31a is provided commonly to all the memory cell array blocks DB0 to DB7 and DP0 to DP3 for every 16 memory cell rows.

Each sub X decoder block 3b-1 to 3b
-6 includes a predecoder 30b and a plurality of subdecoder block pairs 31b and 32b. Each of the plurality of sub-decoder block pairs is provided corresponding to 16 memory cell rows in the corresponding two memory cell array blocks.

The predecoder 30a decodes the address signal from the address buffer 5 in FIG. 1 so as to match the decoding operation of the main decoder block 31a. Similarly, the predecoder 30b decodes the address signal from the address buffer 5 so as to match the decoding operation of the sub decoder block pair 31b, 32b.

Each main decoder block 31a further decodes the decoded output of the predecoder 30a,
It is commonly applied to all sub-decoder block pairs 31b and 32b provided corresponding to the corresponding 16 memory cell rows.

Each sub-decoder block pair has a corresponding 2
Subdecoder block 3 provided corresponding to one 16 memory cell row of one memory cell array block
1b and a sub-decoder block 32b provided corresponding to the other 16 memory cell rows. Each of the sub-decoder blocks 31b and 32b is responsive to the decode output of the corresponding main decoder block 31a and the decode output of the corresponding pre-decoder 30b, and the 16 word lines included in the corresponding 16 memory cell rows (see FIG. (Not shown) and the potentials of two select gate lines (not shown) are controlled.

Referring to FIG. 3, each main decoder block 31a inverts the output of NAND gate 500, which receives, for example, some of the decode outputs of predecoder 30 of FIG. And an inverter 510 that operates. The predecoder 30 decodes the address signal from the address buffer 5 so that only one signal input from the predecoder 30 to any one of the NAND gates 500 becomes high level. As a result, the plurality of main decoder blocks 3
Only one of the outputs 1a goes high.

On the other hand, referring to FIG. 4, each of the sub-decoder blocks 31b and 32b includes 16 word lines WL1 to WL32 connected to the corresponding 16 memory cell rows and the output signals of the corresponding pre-decoder 31b. 16 out of
16 N-channel MOS transistors 520 respectively coupled to the respective signals, 2-input NAND gates 530 and 550 which respectively receive two of the outputs of the corresponding predecoder 31b, and these two N
Includes two inverters 540 and 560 that invert the outputs of AND gates 530 and 550, respectively. The outputs of inverters 540 and 560 are applied to two select gate lines SG1 to SG4 provided corresponding to the corresponding 16 memory cell rows, respectively.

Each main decoder block 3 in FIG.
The output of 1a corresponds to the corresponding sub-decoder block 31b,
32b transistor 520 and NAND gate 530
And 550.

As described above, among the outputs of the plurality of main decoder blocks 31a, the high level is 1
Only the output of one main decoder block. Therefore, all the transistors 520 in the 12 sub-decoder blocks 31b, 32b (corresponding to 6 sub-decoder block pairs) provided corresponding to this one main decoder block are turned on. On the other hand, in each of the other sub-decoder blocks 31b and 32b,
All the transistors 520 are turned off, and the outputs of the inverters 540 and 560 both become low level.

Each predecoder 31b has a corresponding predecoder 31b in each corresponding subdecoder block 31b.
From the 16 signals supplied to the 16 transistors 520 to 16 520, only one of the 16 signals becomes low level, and among the two signals supplied from the predecoder 31b to the two NAND gates 530 and 550, respectively. The address signal from the address buffer 5 is decoded so that only one of them becomes high level. In each sub-decoder block 31b, a transistor 520 supplied with a low-level signal from the corresponding pre-decoder 31b and a sub-decoder block 32b paired with this sub-decoder block 31b have a corresponding low-level signal from the corresponding pre-decoder 31b. And the transistor 520 to which is supplied, are connected to two word lines provided corresponding to the same row, respectively.

Therefore, only in each of the sub-decoder blocks 31b, 32b provided corresponding to one main decoder block 31a outputting a high level signal, one of the 16 transistors 520 is output. Goes low and the inverter 54
The output of either one of 0 and 560 goes high. As a result, of the word lines and select gate lines included in all the memory cell array blocks DB0 to DB7 and DP0 to DP3, twelve word lines (see FIG. 1) and one word line provided corresponding to the same row are provided. Either the select gate line is activated and each bit line is connected to the activated word line.
The storage data of one memory cell can appear (see FIG. 6).

Each of the word lines WL1 to WL32 in FIG. 4 corresponds to each word line WL in FIG. The select gate line is not shown in FIG. 1 for simplicity.

In the above embodiment, the case where the data to be simultaneously read out to the outside is 8 bits has been described, but the data to be simultaneously read out to the outside may have an arbitrary bit length.

If the data to be read out at the same time is, for example, 16-bit data and 32-bit data, 5-bit parity data and 6-bit data are required to detect and correct a 1-bit error, respectively. Data is used.

Further, in the above embodiment, the memory cell array has the bit length of the data to be simultaneously read to the outside,
Although it is divided into the same number of blocks (12) as the total of the bit length of the parity data, the memory cell array may be divided into a larger number of blocks such as twice the number. By dividing the memory cell array into more blocks, the access time can be further shortened.

Although the present invention is applied to the mask ROM in the above embodiments, the present invention can also be applied to a semiconductor memory device such as EPROM or EEPROM in which data can be written and rewritten after manufacturing.

[0125]

As described above, according to the present invention, it is possible to use not only a semiconductor memory device having a bit defect and a bit line defect but also a semiconductor memory device having a word line defect as a normally functioning semiconductor memory device. Is greatly improved.
As a result, a semiconductor memory device with high yield can be obtained. Further, according to the present invention, the word line can be activated and deactivated at a high speed, so that the access time can be improved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a mask ROM according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a main X decoder and a sub X decoder of FIG.

FIG. 3 is a circuit diagram showing a specific example of a main decoder block shown in FIG.

FIG. 4 is a circuit diagram showing a specific example of a sub-decoder block shown in FIG.

FIG. 5 is a schematic block diagram showing an example of the overall configuration of a conventional mask ROM with an error correction function.

FIG. 6 is a circuit diagram showing an example of an internal configuration of a memory cell array of a mask ROM.

FIG. 7 is a schematic block diagram showing another example of the overall configuration of a conventional mask ROM with an error correction function.

FIG. 8: X in a conventional mask ROM with an error correction function
It is a block diagram which shows schematic structure of a decoder.

9 is a circuit diagram showing a configuration example of a decoder block in FIG.

[Explanation of symbols]

1 Normal Memory Cell Array 2 Parity Memory Cell Array DB0 to DB7, DP0 to DP3 Memory Cell Array Block 3a Main X Decoder 3b-1 to 3b-6 Sub X Decoder 4 Y Decoder 5 Address Buffer 6 Control Circuit 7 Y Gate 8 Sense Amplifier Group 9 ECC 10 output buffer MC, MT memory cell BL, BL1 to BL2 bit line WL, WL1 to WL32 word line In the drawings, the same reference numerals indicate the same or corresponding portions.

Claims (1)

1. A first plurality of blocks for respectively storing a first plurality of data to be simultaneously read out to the outside, and a predetermined number according to the first plurality of data. A second plurality of parity data, each storing a second plurality of parity data;
A memory cell array divided into a plurality of blocks, each block being provided corresponding to the plurality of memory cells and a plurality of memory cells arranged in a plurality of rows; A plurality of word lines commonly connected to the memory cells arranged in a plurality of blocks, and means for selecting any one of the plurality of word lines in each block; and each of the first plurality of blocks. To read the data stored in the memory cell connected to the selected one word line, and to connect to the selected one word line from each of the second plurality of blocks. Means for reading the data stored in the stored memory cell, based on the data read by the reading means from each of the first plurality of blocks and the second plurality of blocks, A semiconductor memory device further comprising: means for detecting an error in data read by the reading means from the first plurality of blocks.