JPH05207440A - Code quantity controller - Google Patents

Abstract

PURPOSE:To reduce the deterioration in picture quality due to a quantization error by sampling picture information of a macro block to be coded next when a quantization width reaches a large width so as to reduce the produced code quantity thereby keeping the quantization width to be small. CONSTITUTION:A DCT(discrete cosine transformation) circuit 12 transforms an output of a sub sample circuit 11 into a DCT coefficient and outputs the coefficient. A quantization circuit 13 applies weighting and quantization of an output of the DCT circuit 12 and outputs the result. The quantization is implemented by using a quantization width obtained by a quantization width control circuit 16. An output of the quantization circuit 13 is coded by a variable length coding circuit 14 and stored in a buffer 15. The buffer 15 outputs the stored code sequentially from a terminal 112. The quantization width control circuit 16 changes a quantization width used by the quantization circuit 13 based on a residual quantity of the buffer 15 to control the produced code quantity. A judging circuit 17 judges the method for sub sample control implemented by the sub sample circuit 11 depending on the quantization width obtained by the quantization width control circuit 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code amount control device used for image coding.

[0002]

2. Description of the Related Art As an image encoding method, for example, MPE which promotes international standardization of moving image encoding
G3 (MPEG) coding reference model SM3 (I
SO-IEC / JTC1 / SC2 / WG11 N001
0 MPEG 90/041), in which a code amount control device is used.

A conventional code amount control device will be described below. FIG. 10 shows the configuration of a conventional code amount control device.

In FIG. 10, reference numeral 101 denotes a DCT circuit for performing DCT (discrete cosine transform), which converts image information input from a terminal 1101 into DCT coefficients. A quantization circuit 102 weights and quantizes the DCT coefficients output from the DCT circuit. Reference numeral 103 denotes a variable length coding circuit, which codes the output of the quantization circuit 102. 104
Is a buffer, which stores the code output from the variable length coding circuit 103 and outputs the code from the terminal 1102. 105
Is a quantization width control circuit, which obtains the quantization width based on the residual amount in the buffer 104.

The operation of the code amount control device will be described below. First, the image information input from the terminal 1101 is processed by the DCT circuit 101 for each block (8 × 8 small area).
It is converted into a T coefficient, and the quantization circuit 102 performs weighting and quantization. The quantization is performed for each macroblock composed of 6 blocks as shown in FIG. 3A, using the quantization width obtained by the quantization width control circuit 105. The DCT coefficient quantized by the quantization circuit 102 is coded by the variable length coding circuit 103 and stored in the buffer 104.
The buffer 104 sequentially outputs the stored codes from the terminal 1102. The quantization width control circuit 105 includes the buffer 10
The amount of generated code is controlled by changing the quantization width used in the quantization circuit 102 according to the residual amount of 4. That is, the larger the buffer residual amount is, the larger the quantization width is to decrease the generated code amount, and the smaller the buffer residual amount is, the smaller the quantization width is to increase the generated code amount. Control to approach the quantity.

[0006]

In the above configuration, since the generated code amount is controlled by adjusting only the quantization width, the larger the generated code amount, the larger the quantization width. Therefore, if the quantization width becomes too large, a very large quantization error occurs and the image quality deteriorates.

In order to solve the above problem, the present invention controls the sub-sampling of the image information of the macroblock to be coded next when the quantization width has a large value. As described above, by performing not only the adjustment of the quantization width but also the sub-sampling to reduce the generated code amount and keep the quantization width at a small value, a code amount control device with less image quality deterioration due to quantization error is provided. The purpose is to

[0008]

In order to achieve the above object, a code amount control apparatus of the present invention comprises a sub-sampling circuit for sub-sampling image information for each macroblock, and a sub-sampling control by the sub-sampling circuit. A DCT circuit for converting the output of the sub-sampling circuit into a DCT coefficient according to the block size of the image information, a quantizing circuit for weighting and quantizing the output of the DCT circuit, and an output of the quantizing circuit A variable length coding circuit for encoding, a quantization width control circuit for obtaining a quantization width of a macroblock to be coded next based on the residual amount of a buffer storing the output of the variable length coding circuit, and the quantization width control A determination circuit for determining the method of sub-sampling control performed by the sub-sampling circuit is provided based on the quantization width obtained by the circuit.

[0009]

According to the present invention, when the quantization width has a large value, the present invention reduces the generated code amount by sub-sampling the image information of the macroblock to be coded next. Therefore, the quantization width can be kept at a small value, and the deterioration in image quality due to the quantization error can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a code amount control device in an embodiment of the present invention. In FIG. 1, reference numeral 11 is a sub-sampling circuit, which inputs image information from a terminal 111 and performs sub-sampling control. Reference numeral 12 is a DCT circuit, which converts the output of the sub-sampling circuit 11 into DCT coefficients. Reference numeral 13 is a quantization circuit, which is the DCT output from the DCT circuit 12.
Coefficient weighting and quantization. Reference numeral 14 is a variable length coding circuit, which codes the output of the quantization circuit 13. A buffer 15 stores the code output from the variable-length coding circuit 14 and outputs the code from the terminal 112. Reference numeral 16 is a quantization width control circuit, which determines the quantization width of the macroblock to be coded next based on the remaining amount in the buffer 15. A determination circuit 17 determines the sub-sampling control method performed by the sub-sampling circuit 11 based on the quantization width obtained by the quantization width control circuit 16.

The operation of the code amount control device of FIG. 1 will be described below. First, the sub-sampling circuit 11 performs sub-sampling control of the image information input from the terminal 111 for each macroblock shown in FIG. 3A according to the determination result of the determination circuit 17, and outputs it. The DCT circuit 12 converts the output of the sub-sampling circuit 11 into a DCT coefficient according to the block size of the image information subjected to the sub-sampling control by the sub-sampling circuit 11 according to the determination result of the determination circuit 17, and outputs the DCT coefficient. The quantization circuit 13 weights and quantizes the output of the DCT circuit 12, and outputs the weighted and quantized signal. The quantization is performed using the quantization width obtained by the quantization width control circuit 16. The output of the quantization circuit 13 is coded by the variable length coding circuit 14 and is output to the buffer 15
Stored in. The buffer 15 stores the stored code in the terminal 1
It outputs sequentially from 12. The quantization width control circuit 16 changes the quantization width used in the quantization circuit 13 according to the remaining amount of the buffer 15, and controls the generated code amount. Judgment circuit 1
Reference numeral 7 determines the sub-sampling control method performed by the sub-sampling circuit 11 based on the quantization width obtained by the quantization width control circuit 16.

The above is the flow of the operation in this embodiment. Next, the operation of the judgment circuit 17 will be described. If the quantization is performed with a large quantization width, the image quality is deteriorated due to the quantization error. Therefore, it is necessary to reduce the generated code amount by sub-sampling and reduce the quantization width. However, when the sub-sampling rate is small, the generated code amount does not decrease and the image quality deteriorates due to the quantization error. When the sub-sampling rate is large, the sampling points decrease and the image quality deteriorates due to the lower resolution. .. Therefore, since it is necessary to change the sub-sampling rate according to the quantization width, the determination circuit 17 determines the sub-sampling control method performed by the sub-sampling circuit according to the quantization width.

That is, the quantization width obtained by the quantization width control circuit is Qs, and the preset thresholds are T1 and T2.
If (T1 <T2), the above determination circuit determines that “no subsample” when Qs ≦ T1, “horizontal subsample” when T1 <Qs ≦ T2, and “horizontal / vertical subsample” when T2 <Qs. "Sample". When the value of the image information input by the sub-sampling circuit is 0 to 255, the threshold values are, for example, T1 = 30 and T2 = 50.

The sub-sampling circuit 11 will be described below. FIG. 2 shows the configuration of the sub-sampling circuit 11 of this embodiment.

In FIG. 2, reference numeral 21 is a horizontal sub-sampling circuit, which sub-samples the image information input from the terminal 121 in the horizontal direction. A vertical sub-sampling circuit 22 sub-samples the output of the horizontal sub-sampling circuit 21 in the vertical direction. Reference numeral 23 denotes a selection circuit, which selects and outputs one image information from the three image information of the input of the horizontal sub-sampling circuit, the output of the horizontal sub-sampling circuit, and the output of the vertical sub-sampling circuit.

The operation of the sub-sampling circuit 11 shown in FIG. 2 will be described below. The horizontal sub-sampling circuit 21 is shown in FIG.
The image information of one macro block configured as shown in FIG.
The image information as shown in (b) is output. The output of the horizontal sub-sampling circuit 21 is further sub-sampled in the vertical direction by the vertical sub-sampling circuit 22 and becomes as shown in FIG. The selection circuit 23 includes image information that is not subsampled, image information that is horizontally subsampled by the horizontal subsample circuit 21, and image information that is horizontally and vertically subsampled by the horizontal subsample circuit 21 and the vertical subsample circuit 22. One of the three image information is selected according to the determination result of the determination circuit input from the terminal 122, and is output from the terminal 123. The image information output by the selection circuit 23 is the input of the horizontal sub-sampling circuit 21 when the determination result of the determination circuit input from the terminal 122 is “no sub-sampling”, and “horizontal sub-sampling”.
In the case of, the output is from the horizontal sub-sampling circuit 21, and in the case of "horizontal / vertical sub-sampling," it is the output from the vertical sub-sampling circuit 22.

FIG. 4 shows the configuration of the horizontal sub-sampling circuit 21. In FIG. 4, reference numeral 41 denotes a delay element, which delays the image information input from the terminal 141 by one pixel. An adder 42 adds the image information input from the terminal 141 and the image information output from the delay element 41. 43 is a coefficient multiplier, and the output of the adder 42 is 0.
Multiply by 5. 44 is a thinning circuit, which is a coefficient multiplier 43.
Output is thinned out every other pixel and output from the terminal 142.

Therefore, the horizontal sub-sampling circuit 2
1 receives the image information of the macroblock structure shown in FIG. 3A from the terminal 141, and the adder 42 and the coefficient multiplier 4
At 3, the average is output for every two pixels. The output of the coefficient multiplier 43 is decimated by the decimating circuit 44 every other pixel.
The image information of the macroblock structure shown in FIG.
It is output from 2.

FIG. 5 shows the configuration of the vertical sub-sampling circuit 22. In FIG. 5, reference numeral 51 is a memory, which inputs the output of the horizontal sub-sampling circuit from the terminal 151, stores it in each block, and outputs it in the numerical order as shown in FIG. A delay element 52 delays the image information output from the memory 51 by one pixel. An adder 53 adds the image information output from the memory 51 and the image information output from the delay element 52. A coefficient multiplier 54 multiplies the output of the adder 53 by 0.5. 5
A thinning circuit 5 thins out the output of the coefficient multiplier 54 every other pixel and outputs the thinned output. Reference numeral 56 denotes a memory, which stores the image information output from the thinning circuit 55, and is shown in FIG.
The numbers are output from the terminal 152 in the order of numbers.

Therefore, the vertical sub-sampling circuit 2 described above is used.
2, the output of the horizontal sub-sampling circuit is input from the terminal 151, and the adder 53 and the coefficient multiplier 54 average and output every two pixels in the vertical direction. The output of the coefficient multiplier 54 is thinned out every other pixel by the thinning circuit 55, and the image information of the macroblock structure shown in FIG.

Next, the operation of the DCT circuit 12 of this embodiment will be described. FIG. 7 shows the configuration of the DCT circuit 12. A switching circuit 71 switches the output destination of the image information input from the terminal 171 depending on the block size. 72 is an 8x8 DCT circuit, which is an 8x8 DC
Do T. 73 is a 4 × 8 DCT circuit, which is a 4 × 8 D
Perform CT. A 4 × 4 DCT circuit 74 performs 4 × 4 DCT.

As shown in FIG. 3, the block size of luminance (Y) is 8 × 8 regardless of whether sub-sampling is performed or not.
Is. However, the block size of the color difference (Pb, Pr) is 8 × 8 when the determination circuit determines “no sub-sample” and 4 × 8 when the “horizontal sub-sample” is determined. , 4 × 4 when it is determined to be “horizontal / vertical subsample”. Therefore, the switching circuit 71 uses the determination circuit 17 input from the terminal 172.
According to the determination result of (1), the circuit that performs DCT of the image information input from the terminal 171 is switched to perform DCT according to the block size. That is, 8 × 8 DCT is performed on the luminance image information or the color difference image information determined as “no sub-sample” by the determination circuit 17, and the color difference image information determined as “horizontal sub-sample” is 4 × 8. The DCT of × 8 is performed, and the image information of the color difference determined as the “horizontal / vertical subsample” is subjected to 4 × 4 DCT. In this way, the image information output from the sub-sampling circuit 11 is DCT according to the block size and output from the terminal 173.

Next, the operation of the variable length coding circuit 14 of this embodiment will be described. FIG. 8 shows the configuration of the variable length coding circuit 14. Reference numerals 81 to 83 denote tables, which respectively store information indicating the order of zigzag scanning as shown in FIGS. A switching circuit 84 selects one of the tables 81 to 83 according to the block size according to the determination result of the determination circuit input from the terminal 182 and the output of the quantization circuit input from the terminal 181. ,Output. Reference numeral 85 denotes an encoder, which inputs the output of the quantizing circuit from a terminal 181, encodes it, and outputs it from a terminal 183.

Since the block size of the color difference (Pb, Pr) differs depending on the determination result of the determination circuit 17, the switching circuit 84 selects a table indicating the order of zigzag scanning according to the block size and outputs it to the encoder 85. ..
That is, the encoder 85 selects the table 81 when the chrominance determined as "no subsample" by the luminance or the above determination circuit is input, and when the chrominance determined as "horizontal subsample" is input. Select table 82,
When the color difference determined as “horizontal / vertical subsample” is input, the table 83 is selected.

With the above configuration, when the quantization width becomes large, sub-sampling is performed to reduce the generated code amount. In this way, the quantization width is kept at a small value and image quality deterioration due to quantization error is reduced.

In the case of decoding, a determination circuit 17 for determining the method of sub-sampling control performed by the sub-sampling circuit 11 for each macroblock based on the quantization width is provided, and the determination result is similar to that of the DCT circuit 12. Inverse DCT is performed according to the block size. Further, the sub-sampled macroblock is interpolated according to the determination result of the determination circuit 17. That is, when horizontal sub-sampling is performed, pixels between pixels in the horizontal direction are interpolated, and when horizontal / vertical sub-sampling is performed, pixels between lines are further interpolated. The interpolation uses a linear interpolation method or the like. An image can be reproduced by interpolating the sub-sampled macroblocks.

[0027]

As described above, according to the present invention, when the quantization width becomes large, sub-sampling is performed to reduce the generated code amount, and the quantization width is maintained at a small value to control the code amount with less image quality deterioration. It realizes the device.

[Brief description of drawings]

FIG. 1 is a block connection diagram of a code amount control device according to an embodiment of the present invention.

FIG. 2 is a block connection diagram of a sub-sampling circuit which is a main part of the same code amount control device.

FIG. 3 is a conceptual diagram of a macroblock structure of the same code amount control device.

FIG. 4 is a block connection diagram of a horizontal sub-sampling circuit, which is a main part of the same code amount control device.

FIG. 5 is a block connection diagram of a vertical sub-sampling circuit which is a main part of the same code amount control device.

FIG. 6 is a conceptual diagram showing the order of outputting image information of a vertical sub-sampling circuit which is a main part of the same code amount control device.

FIG. 7 is a block connection diagram of a DCT circuit which is a main part of the same code amount control device.

FIG. 8 is a block connection diagram of a variable length coding circuit which is a main part of the same code amount control device.

FIG. 9 is a conceptual diagram of a zigzag scan order of a variable length coding circuit which is a main part of the same code amount control device.

FIG. 10 is a block connection diagram of a conventional code amount control device.

[Explanation of symbols]

 11 sub-sampling circuit 12 DCT circuit 13 quantizing circuit 14 variable-length coding circuit 15 buffer 16 quantizing width control circuit 17 determination circuit 111, 112 terminal 21 horizontal sub-sampling circuit 22 vertical sub-sampling circuit 23 selection circuits 121, 122, 123 Terminal 41 Delay circuit 42 Adder 43 Coefficient multiplier 44 Decimation circuit 141, 142 Terminal 51 Memory 52 Delay circuit 53 Adder 54 Coefficient multiplier 55 Decimation circuit 56 Memory 151, 152 Terminal 71 Switching circuit 722 8 × 8 DCT circuit 734 × 8 DCT circuit 74 4 × 4 DCT circuit 171, 172, 173 terminals 81-83 table 84 switching circuit 85 encoder 181, 182, 183 terminal 101 DCT circuit 102 quantization circuit 103 variable length encoding circuit 104 buffer 10 Quantization width control circuit 1101 and 1102 terminals

Claims (1)

[Claims] 1. A sub-sampling circuit for sub-sampling control of image information for each macro block, and an output of the sub-sampling circuit into a discrete cosine transform coefficient according to a block size of image information sub-sampled by the sub-sampling circuit. A discrete cosine transform circuit for converting, a quantizing circuit for weighting and quantizing the output of the discrete cosine transform circuit, a variable length coding circuit for coding the output of the quantizing circuit, and the variable length coding circuit. Is performed by the sub-sampling circuit according to the quantization width control circuit that obtains the quantization width of the macroblock to be encoded next based on the residual amount of the buffer that stores the output of the output and the quantization width that is obtained by the quantization width control circuit. A code amount control device comprising a determination circuit for determining a sub-sampling control method.