JPH05207329A - Signal processing circuit for digital video camera - Google Patents

Abstract

PURPOSE:To decrease the capacity of a memory to be used for a digital signal processing, and to simplify a digital processing circuit, in a digital video camera. CONSTITUTION:The number of bits of a digital signal are compressed by a non-linear data compressing circuit 5, the digital signal processing or a writing in a memory 7 is operated, a signal obtained after the signal processing or read from the memory 7 is extended by a non-linear data extending circuit 8, and the original digital signal is restored. And also, the data compression circuit 5 and the data extending circuit 8 are operated in combination with a comparator circuit, bit shift circuit, and selecting circuit or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video in which an analog video signal obtained from an image pickup device is once converted into a digital signal, and signal processing for electronic zoom, camera shake correction and the like is digitally performed. Regarding the camera.

[0002]

2. Description of the Related Art One of the advantages of digitizing the signal processing of a video camera is that electronic zoom and camera shake correction can be realized relatively easily using a digital memory.

In such a case, conventionally, an analog video signal obtained from a CCD image pickup device is converted into an 8-bit digital signal by an A / D converter, the 8-bit digital signal is stored in various memories, and then, Digital signal processing is performed to realize each function.

However, in such a video camera, when so-called non-linear processing such as gamma correction is performed on an 8-bit digital signal, noise becomes noticeable in the processed signal. This is because the quantization error in the low level part of the video signal, which is caused by the lack of the quantization accuracy of the A / D converter, is enlarged by the non-linear processing.

In order to eliminate such a drawback, it is sufficient to use an A / D converter having a large number of bits to improve the quantization accuracy, but at present, the number of bits is less than 8 bits. A large A / D converter is expensive, and accordingly, a large capacity memory is required for the signal processing circuit as described above. Therefore, the following method has been proposed instead. It is disclosed in JP-A-2-23778 (H
04N5 / 14), the analog video signal is non-linearized by line approximation before A / D conversion in order to secure the quantization accuracy required for the low level part of the video signal, and the analog signal after this non-linearization is Is subjected to A / D conversion for various digital signal processing.

[0006]

However, according to the above method, the boundary of each broken line characteristic varies due to the instability due to the temperature and variations of the elements constituting the analog circuit. It is difficult to surely restore linearly by the digital processing of 1., which causes deterioration of image quality at the boundary portion. Therefore, it is difficult to reduce the number of bits of the digital signal and to significantly reduce the memory capacity required for digital processing such as electronic zoom and camera shake correction without causing significant image quality deterioration. It was

Therefore, an object of the present invention is to realize a digital video camera which eliminates such drawbacks.

[0008]

According to the present invention, a digital signal obtained by A / D converting an analog video signal is once nonlinearly compressed by a data compression circuit to reduce the number of bits.
Various linear digital signal processing is performed on the compressed signal by the digital processing circuit, and the signal after the digital processing is nonlinearly expanded by the data expansion circuit to restore the original digital signal of the number of bits, and then D A / A conversion is performed to restore the analog video signal.

Further, the data compression circuit includes a plurality of bit shift circuits each of which provides a digital signal after A / D conversion with a gain corresponding to the slope of each polygonal line when the nonlinear compression characteristic is approximated by a polygonal line, and the digital signal. With a plurality of thresholds corresponding to the input level at the start point or the end point of each polygonal line, and one of the output signals of the plurality of bit shift circuits is selected and derived in accordance with the output of the comparison circuit. A first selection circuit and a second selection circuit that selects and derives one of the offset values corresponding to the intersection of the output line of each broken line according to the output of the comparison circuit; and the first and second selection circuits. And an adder circuit that obtains a compressed digital output signal by adding the respective output signals.

Further, the data decompression circuit outputs a digital signal output from the digital processing circuit and a plurality of bit shift circuits each of which gives a gain corresponding to the slope of each polygonal line when the nonlinear expansion characteristic is approximated by a polygonal line. A comparison circuit that compares a plurality of threshold values corresponding to the input level at the start point or the end point of each broken line and one of the offset values corresponding to the intersection of the input axis of each broken line is selected according to the output of this comparison circuit. A third selection circuit derived from the digital signal, a subtraction circuit for subtracting the output signal of the third selection circuit from the digital signal and inputting the signal to each of the bit shift circuits, and the plurality of bit shifts according to the outputs of the comparison circuit. A fourth selection circuit for selecting one of the output signals of the circuit and deriving it as a decompressed digital output signal.

[0011]

[Operation] According to the present invention, an analog video signal is converted into an A / D signal.
When performing conversion and digital signal processing, non-linear compression / expansion is performed before and after the digital signal processing, so that digital signal processing and writing / reading to / from the memory used for the digital signal processing have a small number of bits. It is performed on the signal without significant image quality deterioration.

The above compression / expansion can be realized very easily by using a combination of inexpensive digital element circuits such as a bit shift circuit, a comparison circuit and a selection circuit without using a multiplier.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of the essential parts of a digital video camera relating to the present invention. In the figure, 1 is a CCD image pickup device, 2 is a sample and hold circuit for sequentially sampling and holding an analog image signal from the image pickup device 1 at appropriate timing, and the image signal after the sample and hold is A / D converted. The circuit 3 converts it into a 10-bit digital signal. On the one hand, this digital signal is directly input to the signal selection circuit 4,
On the other hand, it is input to the data compression circuit 5.

The data compression circuit 5 is approximated by five broken lines shown in FIG. 2A in order to compress the 10-bit digital signal representing levels 0 to 1023 into an 8-bit signal (0 to 255 levels). Level compression is performed according to the nonlinear characteristic described above, and the 8-bit digital signal after the compression is input to the next digital processing circuit 6. The digital processing circuit 6 uses the memory 7 as necessary for the input 8-bit digital video signal while performing horizontal and vertical interpolation and Y / C (luminance / color) separation or electronic zoom. Performs various linear digital signal processing for image stabilization and image stabilization. Therefore, both writing and reading to the memory 7 are carried out up to 8 bits. Then, the digitally processed signal is input to the data expansion circuit 8.

The data decompression circuit 8 restores the inputted 8-bit digital signal to the original 10-bit digital signal, so that the data decompression circuit 8 exhibits exactly the opposite characteristic to that of FIG. Level expansion is performed by the non-linear characteristic approximated by. Then, the expanded 10-bit digital signal is input to the signal selection circuit 4.

The signal selection circuit 4 is provided with the data compression / expansion circuit 4 when the digital video signal is processed, if it is better to perform 10 bits without level compression depending on the content of the signal processing. It is provided for bypassing, and the signal from the A / D conversion circuit 3 and the signal from the data expansion circuit 8 are selected and derived as needed.

FIG. 3 shows a concrete configuration of the data compression circuit 5, in which 10 is an input of a 10-bit input digital signal to each start point or end point of the five broken lines C1 to C5 representing the compression characteristic of FIG. 2A. Threshold corresponding to level (96, 192, 384, 768)
Comparing circuits for comparing with the above, 12 to 15 are bit shift circuits for giving gains (1/2, 1/4, 1/8, 1/16) corresponding to the inclinations of the respective polygonal lines, and 16 is a circuit for input digital signals. A first selection circuit for selecting and deriving an output signal of one of the direct path 11 (a bit shift circuit having a gain of 1) or the bit shift circuits 12 to 15 in accordance with the output of the comparison circuit 10; A second selection circuit for selecting and deriving an offset value (0, 48, 96, 144, 192) corresponding to the intersection of the polygonal line with the output axis (Y axis) according to the output of the first selection circuit 15;
Reference numeral 18 denotes an adder circuit that digitally adds the output signals of the first and second selection circuits 15 and 16 and outputs the result.

Therefore, in FIG. 3, when a 10-bit input signal indicating, for example, the level 120 is input, 96 <120 <192, so that the comparison circuit 10 presents the second output. The first selection circuit 15 outputs the output value 60 of the bit shift circuit 12, and the second selection circuit 16 derives the offset value 48. Then, the 8-bit signal of level 108 (01101100), which is the addition result of the respective output values, is output from the addition circuit 18.
This means that the level compression is performed using the broken line C2 of the compression characteristic of FIG. 2A.

Even when digital signals of other levels are input, the polygonal line C1 of the compression characteristic corresponding to the signal level is input.
.About.C5, that is, the direct path 11 or the bit shift circuits 12 to 15
By selecting the output value and offset value of
10-bit digital signal ranging from -1023 levels to 0
That is, it is converted into an 8-bit digital signal with up to 255 levels and then output.

Next, FIG. 4 shows a concrete structure of the data expansion circuit 8 in FIG. 1, and 20 is each of the five broken lines E1 to E5 showing the expansion characteristics of the 8-bit input signal in FIG. 2B. A comparison circuit for comparing with a threshold value (96, 144, 192, 240) corresponding to the input level of the start point or the end point, and 21 indicates the intersection of the polygonal line and the input axis (X axis) according to the output of the comparison circuit 20. A third selection circuit that selects and derives one of the corresponding offset values (0, 48, 96, 144, 192), 22 is a subtraction circuit that subtracts the output signal of this selection circuit from the input signal, 24-27 Is a bit shift circuit for giving a gain (2, 4, 8, 16) corresponding to the slope of each polygonal line to the output signal of the subtraction circuit.
8 is the subtraction circuit 22 according to the output of the comparison circuit 20.
Is a fourth selection circuit for selecting and deriving one of the output signals of the direct path 23 (bit shift circuit of gain = 1) and each of the bit shift circuits 24 to 27.

Therefore, in FIG. 4, when an 8-bit input signal indicating the level 108 is input,
Since 96 <108 <144, the comparison circuit 20 presents the second output, which causes the third selection circuit 21 to derive the offset value 48, so that the output signal of the subtraction circuit 22 is 60. Then, by the second output of the comparison circuit 20, the fourth selection circuit 27 outputs the 10-bit output signal 60 × 2 of the bit shift circuit 24 when this signal is input.
= 120, that is, (0001111000) is derived. Therefore, the level extension is performed using the broken line E2 of the extension characteristic of FIG. 2B.

Even when a digital signal of another level is input, a polygonal line E1 having an extension characteristic corresponding to the signal level is input.
~ E5, that is, the direct path 23 or the bit shift circuits 24 to 27
By selecting the output value and offset value of
8 bit digital signal over 253 levels is 0
It is converted into a 10-bit digital signal ranging from -1023 levels and output.

FIG. 5A shows that when the output signal of the A / D conversion circuit 3 of FIG. 1 is 9 bits, it is converted into a 10 bit signal by adding 1 bit of 0 to the least significant digit of the 9 bit signal. However, the compression characteristics when the 10-bit signal is non-linearly compressed to 8 bits are shown. Further, FIG. 5B shows a decompression characteristic when the 8-bit signal is non-linearly decompressed to 10 bits, and each compression / decompression characteristic is approximated by three broken lines.

Although the circuit configurations of the data compression circuit and the data decompression circuit in FIG. 5 are not shown in FIG.
As can be easily understood from the comparison between B and FIG. 3 and FIG.
In this case, the number of bit shift circuits is 12, 14, 15 and the offset value is 0, 144, 192, and the threshold value of the comparison circuit 10 is 384, 768. Further, the straight passage 11 may be deleted. Similarly, in FIG. 4, the number of bit shift circuits is 24, 26 and 27, the offset values are 0, 144 and 192, and the threshold value of the comparison circuit 20 is 19.
2, 240, and the direct passage 23 may be deleted.

The above is the data compression circuit 5 as shown in FIG.
After performing the above-described various linear digital processes on the digital video signal nonlinearly compressed by the data decompression circuit 8
Although the description has been given by taking the embodiment in which the non-linear expansion is performed to restore the original signal as an example, the major purpose of performing such compression is to reduce the capacity of the memory 7 used in the digital processing. .. Therefore, when it is better to perform the digital signal processing itself on the uncompressed signal,
It is sufficient to perform the compression and decompression only before and after the writing and reading of the memory 7 with the configuration as in the embodiment of FIG. In addition, writing to memory,
Since reading is also a linear process of a digital signal in a broad sense, in the present invention, such a writing and reading operation to a memory will be referred to as a nonlinear digital signal process in a broad sense.

[0026]

According to the present invention, the number of bits of a digital signal is once compressed to perform linear digital signal processing, and the signal after the digital processing is expanded to restore the signal of the original number of bits. Therefore, it is possible to reduce the memory capacity required for signal processing of the digital video camera without significant image quality deterioration, and the compression circuit and decompression circuit can be realized with a simple circuit configuration. The cost and size of the camera can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2A is a characteristic diagram of the data compression circuit, and B is a characteristic diagram of the data decompression circuit.

FIG. 3 is a circuit block diagram showing a specific configuration of a data compression circuit of the above embodiment.

FIG. 4 is a circuit block diagram showing a specific configuration of a data expansion circuit of the above embodiment.

5A and 5B are characteristic diagrams for explaining another example of data compression / decompression.

FIG. 6 is a block diagram showing a main part of another embodiment of the present invention.

[Explanation of symbols]

 5 data compression circuit 6 digital processing circuit 7 memory 8 data decompression circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toru Asaeda 2-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Toru Yamamoto 2-18th Keihanhondori, Moriguchi-shi, Osaka Sanyo Denki Co., Ltd. (72) Inventor Seiji Kawakami 2-18, Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Masao Takuma, 2-18, Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Co., Ltd.

Claims (3)

[Claims] 1. An analog video signal obtained from an image sensor is
In a digital video camera in which D / A conversion is performed and digital processing is performed, and then D / A conversion is performed to obtain a camera image output signal, the number of bits of the A / D converted digital signal is non-linearly compressed. A data compression circuit, a digital processing circuit that performs linear digital processing on the output signal of the data compression circuit, and a data expansion circuit that non-linearly expands the number of bits of the output signal of the digital processing circuit are provided. A signal processing circuit for a digital video camera, wherein a digital output signal of the circuit is D / A converted. 2. The data compression circuit sets a gain corresponding to the slope of each polygonal line when the nonlinear compression characteristic is approximated to a polygonal line by A.
A plurality of bit shift circuits which are respectively applied to the digital signals after D / D conversion, a comparison circuit which compares the digital signals with a plurality of threshold values corresponding to the input level of the start point or the end point of each broken line, and an output of the comparison circuit. According to the output of the comparison circuit, and one of the offset values corresponding to the intersection of the output axis of each of the polygonal lines according to the output of the comparison circuit. 2. A digital video camera according to claim 1, further comprising a second selection circuit for selecting and deriving one of the output signals and an addition circuit for adding output signals of the first and second selection circuits to obtain a compressed digital output signal. Signal processing circuit. 3. The data decompression circuit outputs a digital signal output from the digital processing circuit, and a plurality of bit shift circuits each of which provides a gain corresponding to the slope of each polygonal line when the non-linear decompression characteristic is approximated by a polygonal line. A comparison circuit that compares a plurality of threshold values corresponding to the input level at the start point or the end point of each broken line and one of the offset values corresponding to the intersection of the input axis of each broken line is selected according to the output of this comparison circuit. And a subtraction circuit for subtracting the output signal of the third selection circuit from the digital signal and inputting it to each bit shift circuit, and the plurality of bit shifts according to the outputs of the comparison circuit. Fourth selecting one of the output signals of the circuit and deriving it as an expanded digital output signal
The signal processing circuit of the digital video camera according to claim 1, comprising a selection circuit.