JPH05207237A - Picture recorder - Google Patents

Abstract

PURPOSE:To attain optimum luminous quantity control by controlling an automatic power control(APC) function used to keep a luminous quantity of a laser diode light source constant by means of a CPU in terms of the software in the picture recorder so as to vary the interval of the application of the APC with respect to a change in the environment. CONSTITUTION:Plural D/A converters 601-603 are controlled by a CPU and a current IPT=IPa+IPb+IPd of an LD driver circuit 60A and an LD drive current ILD of a power application control circuit 60B have an inversely proportional relation. Thus, the LD drive current is controlled by changing an input to the D/A converters 601-603 by the CPU. Thus, the CPU is used to control the APC function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus using a laser diode (hereinafter referred to as LD) writing system such as a laser printer, a plain paper copying machine (PPC) and a facsimile.

[0002]

2. Description of the Related Art Conventionally, automatic power control (hereinafter referred to as AP
It is already known to perform the function C by hardware (for example, Japanese Patent Laid-Open Nos. 62-128273 and 62-1).
28274, automatic light output control device).

[0003]

However, in the conventional image recording apparatus, since the APC is composed of the hardware circuit, the APC interval is changed to cope with the optimum light quantity control when the environment changes suddenly. There was a problem that things could not be done easily. The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an image recording apparatus capable of coping with a sudden change in environment.

[0004]

In order to achieve the above object, the present invention provides an image recording apparatus having an APC function for maintaining a constant light quantity of a laser diode light source, in which an APC function is controlled by a central control unit (CPU). The APC interval is changed by performing the interrupt processing in (4). In addition, the operation of the APC is performed using a plurality of DA converters.

[0005]

Therefore, according to the present invention, the APC function is
It is possible to control the optimum light quantity by performing the interrupt processing of the PU and changing the APC interval, and it is possible to adapt to a sudden environment.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the outline of the structure of a mechanical portion of an embodiment of a laser printer to which the present invention is applied. Figure 1
At, the surface of the photoconductor 1 is uniformly negatively charged by the main charger 2. The laser scanning unit 3 performs exposure corresponding to an image signal on the surface of the photoconductor, whereby an electrostatic latent image is formed on the surface of the photoconductor 1. The developing device 4 applies toner to a region of the electrostatic latent image where the negatively charged electric charge disappears due to the exposure, whereby a toner image corresponding to the electrostatic latent image is formed on the surface of the photoconductor 1. This toner image is transferred to the transfer paper sent by the registration roller 6 by the transfer / charge elimination charger 5 part. The transfer paper on which the toner image has been transferred is sent to the fixing device 7, where it is heated and pressurized, sent to the paper discharge unit 8, and then discharged outside the machine by the paper discharge unit 8. The transfer paper is fed from the paper feed tray 9 or the optional large-capacity paper feed stand 10, and transferred / charged by the charger 5
Sent to the department.

FIG. 2 shows the details of the laser scanning unit 3, and FIG. 2 (a) shows an enlarged plane of FIG. 2 (b) showing the positional relationship of the mechanical elements. In this laser scanning unit 3, a light source 11 incorporating a laser diode is used.
Light emitted by the first cylindrical lens 12
Then it is reflected by the first mirror 13 and then the spherical lens.
The rotating polygon mirror 15 passing through 14 is rotated at a constant speed by a motor 16,
Reflects the illuminating light. With the rotation of the rotary polygon mirror 15, the angle of the mirror surface that reflects the irradiation light with respect to the irradiation light increases in sequence, and in the illustrated example, the mirror surface facing the irradiation light is updated every 360 ° / 6 rotation, and the rotation polygon The reflected light of the mirror 15 is repeatedly shaken (main scanning B: FIG. 2B). The light reflected by the rotary polygon mirror 15 is reflected by the second mirror 17 and applied to the photoconductor 1 through the second cylindrical lens 18, and the surface of the photoconductor 1 is line-scanned (B in FIG. 2B). During line scan
By turning the laser diode (LD: FIG. 3 (e)) of the light source 11 ON (energized) / OFF (non-energized) according to the image signal, the surface of the photoreceptor 1 uniformly charged is a minute dot. The charge is selectively removed in units to form an electrostatic latent image on the surface of the photoconductor 1. In order to obtain a beam detect signal representing a line scanning (B in FIG. 2B) division (switching of reflecting surface: switching of line), the light reflected by the mirror 19 on the outer side for exposing the photosensitive member is It is detected by the photo sensor 20. A signal obtained by detecting light with the photo sensor 20 is a beam detect signal generated in the laser scanning system.

FIG. 3 is a diagram showing the configuration of the laser printer. FIG. 3 (a) shows an outline of the electrical system, FIG. 3 (b) shows the detailed configuration of the device controller, and FIG. 3 (c) shows the device controller. FIG. 3D shows the detailed configuration of the exposure controller as the main LSI, and FIG. 3E shows the configuration of the LD driver. Incidentally, FIG. 3 (e) shows the details of the embodiment of the present invention.

In FIG. 3A, the printer controller comprises a data controller 90 and a device controller 80. An operation panel 70 is connected to the data controller 90, and receives image data from the host computer 200 and transfers it to the device controller 80. The device controller 80 is connected to various drivers for electrically energizing various devices for print processing and signal processing circuits connected to various sensors for state detection. The device controller 80 is the data controller 90
In order to execute the print cycle designated in step 1, various devices are sequence-controlled while referring to the detection signals of various sensors.

As shown in FIG. 3B, the main body of the device controller 80 is a print for recording an image of a required size and density on a transfer paper by energizing / deactivating the printing mechanism element of the laser printer at a predetermined timing. LSI21 designed to execute a cycle, and a data controller
Interface buffers 22 and 23 for connection with 90 and options, an input buffer 29, a voltage / current conversion circuit 28, etc. are connected. The LSI 21 also has a ROM 30, which stores optical scanning characteristic compensation data and other data for adapting the laser printer of this embodiment to the laser scanning unit 3 and other laser scanning units.
An EE for storing print condition data such as the number of prints instructed by the DIP switch 31 and the data controller 90 for designating the optical scanning characteristic compensation data and other data corresponding to the mounted laser scanning unit.
A PROM 32 is connected.

As shown in FIG. 3C, the LSI 21 has a CP
The U33, the exposure controller 34, the RAM 35, the A / D converter 36, the input / output port 37, the address decoder 38, the serial interface controllers 39 and 40, the timers 41 to 43, and the interrupt controller 44 are connected by the address bus 45 and the data bus 46. It is one unit of LSI. CPU
Immediately after the power is turned on, 33 reads out the data designated by the DIP switch 31 from the ROM 30 and writes it in the RAM 35. In other words, open 8 (8) DIP switches 31.
(1) / closed (0) 8-bit (SW1 to SW8) code DPSW (recording pixel density designation is 2 bits SW1, S
W2, laser scanning unit type designation is 2-bit SW
3, SW4, and the main scanning control data designated by SW1 to SW4 of the data DPSW of the dip switch 31 and the data SW3 and SW4 designated in correspondence with the print position adjustment instruction in the main scanning direction B of 4 bits SW5 to SW8). The light intensity modulation data (hereinafter referred to as light intensity modulation data) of the laser diode and the frequency modulation data are read from the ROM 30 and written in the RAM 35. The exposure controller 34 is C
The PU 33 operates according to the data read from the ROM 30 based on the data DPSW. The CPU 33 writes the data read from the ROM 30 into the register inside the exposure controller 34, which will be described later. The exposure controller 34 generates a pixel clock signal WCLK according to the data in the internal register, sets the reference light amount of the laser diode, and generates a recording start signal in the main scanning direction based on the main scanning control data read from the RAM 35. Then, the light emission timing and the light emission power of the laser diode LD in the LD driver 60 are controlled based on the light amount modulation data read from the RAM 35 and the image signal VIDEO.

As shown in FIG. 3D, the exposure controller 34 causes the main scanning controller 51 to generate recording start signals LSYNC, LGATE, etc. in the main scanning direction based on the main scanning control data read from the RAM 35. The light quantity modulator 52 changes the light quantity based on the light quantity modulation data read from the RAM 35. The frequency modulator 53 causes the CPU 33 to generate the PLL reference signal CLKA at the frequency set in the internal register 50 and modulates the PLL reference signal CLKA based on the frequency modulation data read from the RAM 35. The internal register 50 designated by the decoder 55 that decodes the address when writing data to the internal register 50,
The CPU 33 uses the LD light amount upper limit data, the LD light amount lower limit data, the reference frequency data of the PLL reference signal CLKA,
Test pattern data and the like are written. The video controller 57 modulates the test pattern generated by the test pattern generator 56 and the image data sent from the data controller 90 based on the output of the main scanning controller 51 to generate an image signal VIDEO. The test pattern generator 56 generates a test pattern based on the data in the internal register 50 written by the CPU 33. Oscillator 24
The clock OSC of FIG. 3B is given to the timing generator 54, and the timing generator 54 generates the timing signals Φ, T0, T1 and T2 based on the clock OSC. The signal Φ is a signal that determines the timing at which the exposure controller 34 accesses the RAM 35, and T0, T1,
T2 defines the timing for reading the main scanning control data, the light quantity modulation data, and the frequency modulation data from the RAM 35. The clock OSC is tap select A64.
Thus, the reference signal CLK0 synchronized with the fall of the beam detect signal DETP is selected. The relationship between the timing pulses T0, T1 and T2 and the RAM 35 is shown in FIG. It should be noted that T0, T1 and T2 are clocks obtained by dividing Φ by 3, and are out of phase with each other by one cycle of Φ. Dividers 58 and 59, phase comparator 160, voltage controlled oscillator 61
The tap selector B62 is a PLL that generates a pixel clock signal WCLK having a frequency specified by the frequency modulator 53.
(Phase-locked loop) circuit, which is reset by beam detect signal DETP
A pixel clock signal WCLK having a frequency corresponding to the frequency modulation data given by 53 is generated. The frequency divider 63 divides the pixel clock signal WCLK to generate a main scanning control clock SCLK.

Now, the data written in the ROM 30 will be described with reference to FIGS. 4 and 5 (a) to 5 (d). First, the dip switch 31 is a switch of 8 stations (8 switches), and the data DP represented by open (1) / close (0) of them.
The contents of SW (SW1 to SW8) specify the items shown in FIG. That is, SW1 and SW2 of the data DPSW are
The recording pixel (dot) density is designated, SW3 and SW4 designate the format or identification code of the laser scanning unit (the mounted laser unit 3), and SW5 to SW8 are optional large capacity. The recording position in the main scanning direction B (FIG. 2B) for the paper feed from the paper feed tray 10 (in the case of the paper feed from the paper feed tray 9 of the main body to the paper feed from the large capacity paper feed tray 10, This is for designating a sheet feeding position deviation adjustment amount in the main scanning direction B). DIP switch 31
As for SW3 and SW4 of the data DPSW to be input at 1, that is, the type or type of the laser scanning unit, four types are assumed in this embodiment as shown in FIG. In the ROM 30 corresponding to this, main scanning control data, light intensity modulation data and frequency modulation data corresponding to each of these four types are stored in the type of laser scanning unit (SW of DPSW).
3 and SW4) correspondingly, four groups are stored. 4 kinds of recording pixel densities (240 DPI, 300D) for 1 group of 1 kind of laser scanning unit of these data
PI, 400DPI and 480DPI) are assumed,
There are four groups of data, one group for one type of laser scanning unit. 5 (a) to 5 (d) show the area division on the ROM 30 of each group of the main scanning control data, the light quantity modulation data, and the frequency modulation data assigned to each of the four types of laser scanning units. .. ROM
On the 30, the laser scanning unit compatible group is
SW3 and SW of data DPSW of DIP switch 31
4, each set in the group is designated by SW1 and SW2 of the data DPSW.

FIG. 6 shows the timing of each part of the exposure controller. The main scanning control data and the main scanning controller 51 will be described with reference to FIG. The main scanning control data is basic magnetic data for generating a main scanning synchronization signal LSYNC in the main scanning direction B starting from the beam detect signal DETP, a main scanning image area designating signal LGATE and other timing signals for recording processing. Yes, the switching interval of adjacent timing signals in time series is defined by the count value (DS) of the main scanning control clock SCLK.
1, DS2, DS3, ...). The main scanning controller 51 includes an address counter 102, a down counter 101, a data register 103, and a sequencer 104, and DS1 (main scanning control data) which is the content of the main scanning control data read from the RAM 35 at T0 immediately after the fall of the beam detect signal DETP. The first DS1 of scan control data)
Are loaded into the data register 103, loaded into the down counter 101, and down counted with the main scanning control clock SCLK. When the down counter 101 counts over, the down counter 101 generates the clock CLK1, increments the address value of the address counter 102, and updates the address value to the RAM 35. That is, the DS1 data access address of the RAM 35 is incremented by 1. Then, DS2, which is the content of the next address read from the RAM 35 in synchronism with T0, is fetched into the data register 103, loaded into the down counter 101, and down counted with the main scanning control clock SCLK. When the down counter 101 counts over, the down counter 101 generates the clock CLK1 to increment the address value of the address counter, and the RAM 35
Update the address value to. That is, DS of RAM35
2 Increment the data access address by 1. Then, DS3, which is the content of the address read out from the RAM 35 in synchronization with T0, is fetched into the data register 103, loaded into the down counter 101, and down counted with the main scanning control clock SCLK. The same operation is performed thereafter to generate the clock CLK1 and the sequencer.
104 counts the clock CLK1 to generate PCDA and below, which indicates the width of the photoconductor 1 in the main scanning direction B shown in FIG. 6B. Some of these timing signals are given to the light quantity modulator 52 and the frequency modulator 53.

FIG. 7 is a detailed block diagram of the photoelectric modulator 52. The relationship between the light quantity modulation data and the light quantity modulator 52 will be described with reference to the time chart of FIG. 6C and FIG.
The light amount modulation data is data including a change amount for changing the light amount, a changing direction, and a changing interval based on the light amount upper limit data of the LD written by the CPU 33 in the internal register 50 of the exposure controller 34. The light quantity modulator 52 is
An address counter 111, a down counter 112 and a data register 113, an up / down counter 114 and a multiplexer 115 are built in, and DP1 (light intensity modulation data) which is the content of the light intensity modulation data read from the RAM 35 at T1 immediately after the fall of the beam detect signal DETP. The first DP 1) in the data register 113 is loaded into the data register 113 and then the down counter 112 is loaded. While the CURV signal generated by the main scanning controller 51 is high (H), the CPU 33 causes the internal register 50 of the exposure controller 34 to read. The light amount upper limit data PMAX of the LD written in the above is output from the up / down counter 114 through the multiplexer 115 to the DA converter described later, but when the CURV signal becomes low (L), the clock CLK2 is generated and the light amount modulation data of Change the amount of light included in the content DP1 The output from the up / down counter 114 to the DA converter D is changed by the data DP1V to be converted, and PMAX-DP1V is output to the DA converter D. Also, clock C
The address value of the address counter 111 is incremented by LK2, and the address value to the RAM 35 is updated. That is, the DP1 data access address of the RAM 35 is set to 1
Increment. Then, after DP2, which is the content of the next address read from the RAM 35 in synchronization with T1, is loaded into the data register 113, the interval component DP
2I is loaded into the down counter 112 and down counted with the main scanning control clock SCLK. Down counter
When the counter 112 counts over, the down counter 112 generates the clock CLK2, and the output from the up / down counter 114 to the DA converter D is changed by the data DP2V that changes the amount of light included in DP2.
The PMAX-DP1V-DP2V is output to the converter D, the address value of the address counter is incremented, and the address value to the RAM 35 is updated. That is, the data access address of DP2 of the RAM 35 is incremented by 1. And RAM35 in synchronization with T1
After the DP3, which is the content of the next address read from, is fetched into the data register 113, it is loaded into the down counter 112 and down counted by the main scanning control clock SCLK. The same operation is performed thereafter to generate the clock CLK2, change the output from the up / down counter 114 to the DA converter D134, and modulate the light amount of the LD driver. Up / down counter in light intensity modulator 52
The output of 114 and the light amount designation data designated by the CPU 33 are given to the LD driver 60A shown in FIG.
The amount of current flowing through the laser diode LD of the light source 11 (FIGS. 2 (a) and 2 (b)) is determined. An energization (ON / OFF) control circuit 60B is connected to the laser diode LD, and when the image signal VIDEO supplied from the exposure controller 34 to the circuit 60B is low (0) indicating recording, the energization control circuit.
The output of 60B to the laser diode LD becomes high, and a current having a level according to the light quantity designation data flows through the laser diode LD, and the laser diode LD emits light (laser light) having a level corresponding to the light quantity designation data. When the image signal VIDEO is high (1) indicating non-conduction, virtually no current flows in the laser diode LD of the conduction control circuit 60B, and the laser diode LD does not emit light. Due to the output of the up / down counter 114 in the light quantity modulator 52 described above, if the image signal VIDEO is one-line all-dot recording, the energizing current of the laser diode LD is roughly as shown in FIG. In advance R
Light quantity modulation data stored in OM30 and written in ROM30 by CPU33, light quantity upper limit data PMAX, L of LD
Current level distribution defined by DPC light amount lower limit data PMIN and APC of LD light amount performed by CPU 33
(Main scanning direction B). Light intensity reference data PR
EF is an energization level controlled by the light amount upper limit data PMAX of the LD and the APC performed by the CPU 33.
In FIG. 9, ± DPnV (n = 1, 2, 3, ...) is
This is data for changing the amount of light contained in DP1 which is the content of the light amount modulation data, and + is DP of the energization level.
nV step up indicates-DP of energization level nV step down specifies the interval component DP of DP2
nI (n = 1, 2, 3, ...) Designates the amount of progress of main scanning. For example, DPnI sets the current level to DPnI when main scanning advances by the main scanning control clock SCLK pulse.
It means V step down.

FIG. 8 shows a detailed block diagram of the frequency modulator 53. Referring to the time chart of FIG. 6 (d) and FIG. 8, the frequency modulation data, the frequency modulator 53 and the frequency divider 58 are shown. explain. The frequency modulation data is PL based on the reference frequency data FINT of the PLL reference signal CLKA written in the internal register 50 of the exposure controller 34 by the CPU 33.
The amount of change and the direction in which the L reference signal CLKA is adjusted
It is data including a changing interval. The frequency modulator 53 gives data designating the frequency of the PLL reference signal CLKA to the frequency divider 58, and the frequency divider 53 generates the PLL reference signal CLKA having the frequency designated by the frequency modulator 53. First, the frequency divider 58 will be described. The frequency divider 58 is a down counter, and when the reference signal CLK0 is counted by the number of frequency data given by the frequency modulator 53, the reference signal CLK0 has a length of 10 clocks. Output pulse,
This is repeated to output as the PLL reference signal CLKA. When the frequency data given by the frequency modulator 53 does not change, the PLL reference signal CLKA having a constant pulse length and a constant cycle is output.
Changes the frequency data, it outputs the PLL reference signal CLKA whose pulse width does not change but its cycle changes. The frequency modulator 53 includes an address counter 121, a down counter 122, a data register 123 and an up / down counter.
The built-in 124, after loading the DF1 (the top DF1 of the frequency modulation data), which is the content of the frequency modulation data read from the RAM 35 at T2 immediately after the fall of the beam detect signal DETP, into the data register 123, the down counter Load to 121. While the CURV signal generated by the main scanning controller 51 is high, the reference frequency data FINT of the PLL reference signal CLKA written in the internal register 50 of the exposure controller 34 by the CPU 33 is later divided by the frequency divider 58.
Output from the up / down counter 124,
When the RV signal becomes low, the clock CLK3 is generated, and the output from the up / down counter 124 to the frequency divider 58 is changed by the amount of data DF1V that changes the frequency contained in DF1 which is the content of the frequency modulation data. Divider 58
To FINT-DF1V. Further, the address value of the address counter 121 is incremented by the clock CLK3, and the address value to the RAM 35 is updated.
That is, the DF1 data access address of the RAM 35 is incremented by 1. And RAM35 in synchronization with T2
The interval component DF2I of DF2, which is the content of the next address read from, is fetched in the data register 123, loaded into the down counter 122, and down counted by the PLL reference signal CLKA. Down counter 12
When 2 counts over, the down counter 122 generates the clock CLK3, and the output from the up / down counter 124 to the frequency divider 58 is changed by the amount of data DF2V that changes the light amount included in DF2. FINT-DF1V-DF2V is output to the device 58, the address value of the address counter is incremented, and the address value to the RAM 35 is updated. That is, R
The DF2 data access address of AM35 is incremented by 1. Then, DF3, which is the content of the next address read from the RAM 35 in synchronization with T2, is stored in the data register.
After loading it to 123, load it to the down counter 112,
Down count with the PLL reference signal CLKA. In the same manner as above, the clock CLK3 is generated, the output from the up / down counter 124 to the frequency divider 58 is changed, and the PLL reference signal CLKA is modulated. Since the frequency modulator 53 thus changes the count value given to the frequency divider 58, the frequency of the PLL reference signal CLKA generated by the frequency divider 58 corresponding thereto changes.

The frequency modulator 53 and the frequency divider 58 described above
The PLL reference signal CLKA is stored in the ROM 30 in advance as shown in FIG.
The frequency modulation data (main scanning direction B) defined by the frequency modulation data written in the AM35 and the reference frequency data FINT of the PLL reference signal CLKA is shown. In Fig. 10, ± DFmV (m = 1, 2, 3, ...)
Is data for changing the frequency included in DF1 which is the content of the frequency modulation data, and + indicates the up of the DFmV step of the frequency, − indicates the down of the DFmV step of the frequency, and the interval component of DF2. D
FmI (m = 1, 2, 3, ...) Designates the amount of progress of main scanning. For example, DFmI changes the frequency to D when the main scan advances by the DFmI pulse of the PLL reference signal CLKA.
It means to step down by FmV. The PLL reference signal CLKA generated by the frequency divider 58 is a low-pass filter external to the frequency divider 59 for the pixel clock signal WCLK, a phase comparator 160, a voltage controlled oscillator 61, and a tap selector B62.
Is a PLL circuit that generates a pixel clock signal WCLK having a frequency specified by the frequency modulator 53.
Pixel clock signal WCL synchronized with L reference signal CLKA
K is supplied to the video controller 57 and the frequency divider 63, the video controller 57 serially reads the image data from the data controller 90 in synchronization with this WCLK, and after processing the signal, outputs the image signal VIDEO. To the energization control circuit 60B (FIG. 3 (e)) of the LD driver 60.

The operation of the light quantity modulator 52 and the frequency modulator 53 described above and the light quantity modulation data and the frequency modulation data which are stored in the ROM 30 in advance and written in the RAM 35 by the CPU 33 are used as the light source 11 (see FIG. 2 (a), FIG. The laser diode LD of 2 (b) is energized with the current level distribution shown in FIG. 9, and the frequency of the pixel clock signal WCLK is a frequency distribution obtained by multiplying CLKA showing the frequency modulation distribution as shown in FIG. The dot recording of one main scanning line is performed in synchronization with this WCLK. The current level distribution as shown in FIG. 9 and the frequency modulation distribution as shown in FIG. 10 can obtain arbitrary distribution characteristics by setting (changing) the light intensity modulation data and the frequency modulation data. Therefore, in this embodiment, the ROM 30 stores four groups of data (FIGS. 5A to 5D) suitable for each of the four types of laser scanning units. Since different types of laser scanning units may have scanning region shifts, the timing signal for defining the main scanning image region and the main scanning control data for each of the four types of laser scanning units are determined for each type of laser scanning unit. Data of four groups (FIGS. 5 (a) to 5 (d)) conforming to the above are stored in the ROM 30.
Each group has four sets of data corresponding to four sets of recording pixel densities.

FIG. 11 is a diagram showing the relationship between the optical output of the LD and the drive current characteristics. In FIG. 11, indicates the light output characteristic curve when the LD ambient temperature T = T ₁ , and T = T ₂
The optical output characteristic curve at the time of is shown. The characteristic card having the relationship of T ₁ <T ₂ is obtained by translating the characteristic curve of. I _th1 and I _th2 represent LD oscillation threshold currents at T = T ₁ and T = T ₂ , respectively. LD drive current I _LD is LD
Is the forward current. In addition, since the optical output and the slope of the LD drive current (P-I _LD ) characteristic also change due to variations in the LD and changes over time, when the LD is driven with a constant current, the optical output fluctuates due to changes such as temperature and changes over time. Will end up. Therefore, in order to obtain a constant light output, the LD light output is monitored by the photo diode (PD) built in the LD, and the drive current is automatically controlled so that the monitor output becomes constant.
(APC) is required. In the embodiment of the present invention,
The APC function is performed by the control device.

3 (e) showing the details of the LD driver in one embodiment of the present invention will be described. Figure 3
In (e), 601 to 604 are DA converters A, B,
C, D, 605 to 610 are resistors, 611 to 613 are operational amplifiers, 614 to 616 are transistors, 617 is an operational amplifier, 6
Reference numerals 18 and 619 are comparators, and 620 is a photodiode (PD). The DA converters A, B, and C601 to 603 are 8-bit ones and are connected to the data bus of the CPU 33 (FIG. 3 (c)), and the CPU 33 directly controls these DA converters. The DA converter 604 is connected to the light quantity modulator 55 (FIG. 3D) of the exposure controller 34. DA converter 601
And the output of the DA converter 602 is the operational amplifier 6 respectively.
11 and 612, the operational amplifiers 611 and 612 are connected to the transistors 614 and 615, and convert the analog output voltage corresponding to the digital value input to the DA converters 601 and 602 into currents I _Pa and I _Pb. There is. Similarly D
The A converter 604 is a transistor via the operational amplifier 613.
It is connected to 616 and converts the analog output voltage corresponding to the digital value input from the light quantity modulator 52 to the DA converter D604 into the current value I _Pd . DA converter C
603 performs impedance conversion of an analog output voltage corresponding to the digital value set by the CPU 33 by an operational amplifier 617 and supplies it as a reference input voltage of the DA converter D604. _{Assuming that} the added value of I _Pa , I _Pb and I _Pd is I _PT , I _PT and LD drive current I _LD have an inversely proportional relationship as shown in FIG. Therefore, DA converter A ~
By changing the digital input value of D601 to 604, L
It becomes possible to control the D drive current. The DA converter A601 performs rough control of the light amount, and the DA converter B602
In order to perform fine control, the values of R _a 605 and R _b 606 are selected to change the change amount of I _PT per one least significant bit (LSB). For example, 1LSB of DA converter A601 is DA
Equal R _a to 256LSB converter B 602, by setting the R _b, allowing the DA converter equal control of up to 16-bit equivalent. LDCT ₁ and LDCT ₂ are output signals of the comparators 619 and 618, respectively,
(H) or low (L) takes two values and photodiode (P
D) It changes depending on the monitor output voltage of 620. The threshold level is determined by the resistance value of R ₁ 608, R ₂ 609, R ₃ 610,
LDCT ₁ signal reaches maximum light intensity (PMAX) and LDC
The T ₂ signal has a set value corresponding to the minimum light amount (PMIN) (see FIG. 13).

The exposure controller 34 (FIG. 3 (c)) has an APC
There is an interrupt function, and the CPU 33 controls the exposure controller 34
An APC interrupt is generated by setting the internal register. Exposure controller 34 video controller 57
The LD drive command signal (VIDEODB becomes active and the LD starts lighting. From FIG. 3 (d). After that, the exposure controller 34 generates an interrupt signal to the CPU 33, and at the same time sets the values of the LDCT ₁ and LDCT ₂ signals. The CPU 33 reads the values of LDCT ₁ and LDCT ₂ latched in the interrupt processing routine, and the DA converter A601, DA converter B602,
The LD light amount is controlled by changing the digital input value of the DA converter C603. Further, by setting the internal register, an area where an interrupt occurs within one main scan can be selected, and can be selected from the following four areas. Within the PCDA range indicating the photoconductor area, outside the PCDA range, PCD
All areas outside the A range and after the SYNC1 signal.

Next, the operation of the APC of this embodiment will be described. In the initialization routine after power-on of the image recording apparatus, "FF" is set in the DA converter A601 and the DA converter B602 as initial data, and the DA converter C603 is set.
And "0" is set to the DA converter D604. In this state, I _PT is maximum and I _LD is minimum (FIGS. 12 and 1).
3). Next, the APC interrupt is generated, and the maximum light amount
(PMAX) and minimum light amount (PMIN) settings are started. C
PU33 sets the digital input value of DA converter B602 to "F
The input of the DA converter A601 is decremented in the state of being fixed to F ″, and fixed when the LDCT ₁ signal is detected. After that, the input value of the DA converter B602 is increased / decreased and fixed when the LDCT ₁ signal changes. This completes the setting of the maximum light amount (PMAX).
For the setting of (IN), first, the DA converter D604 is set to a maximum variable range value which is a value peculiar to the image recording apparatus which is preset in the register in the exposure controller 34, and DA
The value of the converter 603 is incremented from "0" and fixed when the LDCT ₂ signal is detected. As a result, the setting of the minimum light amount (PMIN) is completed, and the APC operation in the initial routine is completed. After that, the light quantity modulator 52 modulates the light quantity by changing the input value of the DA converter D604 based on the light quantity modulation data preset in the RAM 35. Further, after the completion of the initial APC, it is possible to keep the LD light amount constant by executing the APC operation at an appropriate interval described later.

FIG. 14 is a flow chart for explaining the APC operation of the LD of the present invention. FIG. 14 (a) is a diagram showing initial settings after power-on, and DA converters A601 to DA
The initial input data of the converter D604 is set (S ₁ ), then the internal register of the exposure controller 34 is set to the APC full area mode (S ₂ ), and at the same time, the APC in the above register is set.
Interrupt and sets the APCRUN flag to start (S _3). After that, the LD drive command signal (VIDEOB) becomes active and the LD is activated, and the exposure controller 34 generates an interrupt signal to the CPU 33, and at the same time, latches the values of the LDCT ₁ and LDCT ₂ signals in the internal register. ..

FIG. 14B is a diagram showing an APC interrupt in the initial routine after power-on. The following processing is executed by the interrupt generated by the APCRUN flag set. First, because the maximum amount of light (PMAX) setting mode (S ₄ -N), to determine the LDCT ₁ signal (S _6), the input value of DA converter A601 is decremented by 1 from "FF", LDCT ₁ signal input value of DA converter A601 are fixed as they become _{L (S 7, S 8)} . Then, the input value of the DA converter B602 changes from "FF" to "7".
F (128) "is changed (S ₉ ), the LDCT ₁ signal is judged again (S ₁₀ ), and in the case of L, the input value of the DA converter B602 is incremented (S ₁₁ ), and the LDCT ₁ signal is changed. they become H, is set to be decremented by one input value of DA converter B602 (S _12, S ₁₃₎ the minimum amount by fixing the input value of DA converter B 602 (PMIN) mode
(S _14). When the LDCT ₁ signal is H in S ₁₀ , the input value of the DA converter B602 is decremented.
(S _15), LDCT ₁ signal is set by fixing the input value of DA converter B602 in minimum light (PMIN) mode they become _{L (S 16, S 17)} .

FIG. 14C is a diagram showing the APC operation in the normal mode. After the interrupt is generated, PMAX is set first. Check the value of the LDCT ₁ signal, and in the case of L, S ₂₀ ~
The processing of S _{24 is performed} , and in the case of H, the processing of S _{26 to} S ₂₉ is performed.
Processing S ₂₀ to S ₂₄ increments the DA converter B 602, when the LDCT ₁ is changed to the L → H, D
Decrement the A converter B602 by 1 and fix it, and set the minimum light amount (PMIN) mode. DA converter B60
If a carry occurs (FF → 0) is in the middle of increments second input value, increments the input value of DA converter A 601 (S _30), the DA converter B
Set the "7F" in 602 (S ₃₁₎ and then, to set the DA converter B602 again. Processing S ₂₆ to S _29, the value of LDCT ₁ is decremented input value of DA converter B602 is fixed at the time of the change to the H → L. DA converter B
If the input value of 602 is borrow while you are decremented occurs, it decrements the input value of DA converter A 601 (S _32), after setting the "7F" to the DA converter B602, the DA converter B602 again Make settings.
After PMAX setting is completed, set PMIN shown in FIG. 14 (d), reset the APCRUN flag and set normal APC.
Complete the operation. After executing APC in normal APC mode,
The set values of the DA converter A and the DA converter B are compared with the set values after the previous APC execution.
By increasing the execution interval and shortening the APC execution interval when different, it is possible to execute the APC at the optimum interval.

FIG. 14 (d) is a diagram showing details of the minimum light amount setting process shown in S ₅ . The maximum variable range value, which is a value unique to the image recording apparatus, is set in the DA converter D604.
( _S34 ). The DA converter D604 is a 6-bit DA converter that can take input values in 64 steps from 0 to 64, but it is unique to each model. The maximum variable range value is the maximum light amount.
DA converter D between (PMAX) and minimum light amount (PMIN)
The number of steps of 604 is shown. After that, the value of the signal LDCT ₂ for setting the minimum light amount is checked (S ₃₅ ), and in the case of L, the input value of the DA converter C603 is incremented by 1 and LD
When CT ₂ changes to H, set DA converter C603 to 1
Decrement to be fixed (S ₃₆ ~S _38). When LDCT ₂ is H, the input value of the DA converter C603 is decremented and fixed when LDCT ₂ changes to L (S
₄₀ , S ₄₁ ). Maximum light intensity (PMAX) setting, minimum light intensity (PM
When the setting of (IN) is completed, the APCRUN flag is reset (S ₃₉ ), and one APC operation is completed. After the APC operation of the initial routine is completed, the APC area mode is changed from the whole area mode to another mode and the normal APC operation is performed.
Take action.

FIG. 15 is an operation flowchart for setting the APC operation interval. First, when the interval setting mode is set, the set values of the DA converter A601 after the past two APC executions are compared (S ₅₁ , S ₅₂ ), and when the values are different, the APC execution interval T _INT Is set to T ₁ (S
₅₅ ). If they are equal, it is determined whether or not the current setting value of T _INT is T ₁ (S ₅₄ ), and if it is equal to T ₁ , T _INT is set to T ₂ (S ₅₆ ). If it is different from T ₁ , then it is determined whether the set value of T _INT is equal to T ₂ (S ₅₇ ), and if it is equal to T ₂ , T _INT is set to T ₃ (S ₅₈ ). If it is different from T ₂ , then it is judged whether the set value of T _INT is equal to T _3.
(S ₅₉ ), if they are equal, the set value is set to T ₃ as it is, and if they are different, T _INT is set to T ₁ (S ₆₀ ).

[0028]

As is apparent from the above embodiment, the present invention makes it possible to change the interval of the automatic power control by performing the automatic power control function in the image recording apparatus by the interrupt processing from the controller. Therefore, it is possible to control the optimum amount of light, and it is possible to adapt to sudden changes in environmental conditions.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a laser printer to which the present invention is applied.

FIG. 2 is a diagram showing details of a laser scanning unit in FIG.

3A and 3B are diagrams showing a detailed configuration of a laser printer to which an embodiment of the present invention is applied. FIG. 3A is a schematic diagram of an electric system, FIG. 3B is a configuration diagram of a device controller, FIG. 3C is an LSI mainly serving as an equipment controller, FIG. 3D is a configuration diagram of an exposure controller, and FIG. 3E is a configuration diagram of an LD driver.

FIG. 4 is a diagram illustrating data written in a ROM of a device controller of a laser printer to which an embodiment of the present invention is applied.

FIG. 5 is a diagram illustrating data written in a ROM of a device controller of a laser printer to which an embodiment of the present invention is applied.

FIG. 6 is a timing chart of each part of the exposure controller of the laser printer to which the embodiment of the present invention is applied.

FIG. 7 is a detailed block diagram of an exposure controller light amount modulator of a laser printer to which an embodiment of the present invention is applied.

FIG. 8 is a detailed block diagram of an exposure controller frequency modulator of a laser printer to which an embodiment of the present invention is applied.

FIG. 9 is a diagram showing the relationship between the current level of the energizing current of the laser diode and the main scanning direction B by the exposure controller light amount modulation output of the laser printer to which the embodiment of the present invention is applied.

FIG. 10 is a diagram showing the relationship between the frequency of the PLL reference signal clock and the main scanning direction B by the exposure controller frequency modulator and the frequency divider of the laser printer to which the embodiment of the present invention is applied.

FIG. 11 is a characteristic diagram of optical output and drive current of a laser diode (LD) according to an embodiment of the present invention.

FIG. 12 is a diagram showing a relationship between a laser diode drive current and an added value of current values corresponding to digital values input to a DA converter in one embodiment of the present invention.

FIG. 13 is a diagram illustrating the operation of APC in one embodiment of the present invention.

FIG. 14 is a flowchart illustrating the APC operation of the laser diode according to the embodiment of the present invention.

FIG. 15 is an operation flowchart for setting an APC operation interval according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Photosensitive member, 2 ... Main charger, 3 ... Laser scanning unit, 4 ... Developing device, 5 ... Transfer / static elimination charger, 6 ... Registration roller, 7 ... Fixing device,
8 ... Paper discharge unit, 9 ... Paper feed tray, 10 ... Large capacity paper feed stand, 11 ... Light source, 12 ... First cylindrical lens,
13 ... 1st mirror, 14 ... Spherical lens, 15 ...
Rotating multi-sided boundary, 16 ... motor, 17 ... second mirror, 18 ...
Second cylindrical lens, 19 ... Mirror, 20 ... Photo sensor, 21 ... LSI, 22, 23 ... Interface buffer, 24 ... Transducer, 25 ... Motor driver, 26
... Clutch driver, 27 ... Output buffer, 28 ... Voltage / current conversion circuit, 29 ... Input buffer, 30 ... ROM,
31 ... DIP switch, 32 ... EEPROM, 33 ...
CPU, 34 ... Exposure controller, 35 ... RAM, 36
... A / D converter, 37 ... I / O port, 38 ... Address decoder, 39 ... Serial interface controller 1, 40 ... Serial interface controller 2, 41, 42, 43 ... Timer, 44 ... Interrupt controller,
50 ... Internal register, 51 ... Scan controller, 52 ...
Light intensity modulator, 53 ... Frequency modulator, 54 ... Timing generator, 55 ... Decoder, 56 ... Test pattern generator,
57… Video controller, 58, 59, 63… Divider, 60…
LD driver, 61 ... Voltage controlled oscillator, 62 ... Tap selector B, 64 ... Tap selector A, 70 ... Operation panel, 80 ... Equipment controller, 90 ... Data controller, 100 ... Laser printer, 111, 121 ... Address counter, 112, 122 ... Down counter, 113, 123 ... Data register, 114, 124 ... Up-down counter, 11
5 ... Multiplexer, 160 ... Phase comparator, 200 ... Host computer, 601, 602, 603, 604 ... DA converter, 605, 606, 607, 608, 609, 610 ... Resistor, 611, 6
12, 613, 617 ... Operational amplifier, 614, 615, 616 ... Transistor, 618, 619 ... Comparator, 620 ... Photodiode (PD).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01S 3/133 7131-4M

Claims (2)

[Claims] 1. A laser diode light source, an optical scanning unit located between the light source and the image forming medium for scanning light emitted from the light source in the main scanning direction of the image forming medium, and a dot unit in synchronization with a main scanning synchronizing signal. An image signal output means for updating an image signal for image formation and a light irradiation control means for turning on / off the light source in response to the image signal are provided, and for keeping the light quantity of the laser diode light source constant. It has an auto power control function.
An image recording apparatus for performing APC by interrupt processing of a central control unit (CPU), wherein an interval for executing the APC function is variable. 2. The image recording apparatus according to claim 1, wherein the APC operation is performed using a plurality of DA converters.