JPH05207086A - System and equipment for duplex differential coding communication - Google Patents

Abstract

PURPOSE:To provide communication equipment by a duplex differential coding system capable of easily compensating a phase error due to the fluctuation of a carrier frequency in digital data communication by a phase modulation system. CONSTITUTION:This system and equipment is comprised of a duplex differential modulation system in which the phase of the carrier of a first modulation signal on which a digital signal to be transmitted is added by delaying by one time slot is modulated and transmitted by a second modulation signal generated by adding the first modulation signal by delaying by one time slot again, and a duplex detection system which demodulates the first modulation signal obtained by phase-detecting a baseband signal orthogonally intersecting from a reception frequency signal, and delaying and detecting from the baseband signal and the one before one time slot to the digital signal to be transmitted by delaying and detecting by one time slot again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual differential encoding communication system and its apparatus used in a wireless network for high speed digital signal transmission such as a mobile phone and a LAN.

[0002]

2. Description of the Related Art A communication device, particularly a receiving device, used in the above-mentioned wireless network includes a phase detecting means for detecting a baseband signal orthogonal to a phase-modulated received high frequency signal, and a phase detecting means for detecting the phase detecting means. There is a delay detection means for calculating and deriving a modulated digital signal from the baseband signal and the baseband signal one time slot before, and the delay detection means is used for this baseband signal and one time slot before. A delay circuit for delaying the quadrature component data by one time slot in order to calculate and derive a modulated digital signal from the baseband signal of
There is a configuration in which an arithmetic circuit including four to four multipliers and adders / subtractors is provided (Japanese Patent Application No. 2-252338).
issue). When the baseband signal is detected by the phase detection means, a phase difference occurs in one time slot due to a frequency change occurring in a carrier wave or the like, and as a result, the error characteristic is deteriorated. A phase compensating circuit that compensates for frequency fluctuations using a moving average of the phase difference is provided.

[0003]

However, according to the above-mentioned conventional receiver using the baseband differential detection method, not only is the structure of the phase compensation circuit for calculating the phase shift complicated, but one time slot is used. However, if the phase error per unit becomes 1/2 or more of the modulation phase unit (π for BPSK, π / 2 for QPSK), there is a drawback that accurate compensation cannot be performed. An object of the present invention is to eliminate the above drawbacks.

[0004]

In order to achieve this object, a characteristic configuration of a dual differential encoding communication system according to the present invention is that a first modulated signal obtained by delaying and adding a digital signal to be transmitted by one time slot is added. , A double differential modulation method in which the carrier wave phase is modulated by the second modulation signal generated by delaying by one time slot and then added, and a baseband signal having a different π / 2 phase from the received high frequency signal is phased. The first modulated signal obtained by detecting and delay-detecting the baseband signal and the baseband signal one time slot before is again detected by one time slot delay and demodulated to the digital signal to be transmitted. It consists of a double delay detection method.

In realizing the above-mentioned dual differential encoding communication system, the characteristic configuration of the dual differential encoding communication device according to the present invention is a phase detection for detecting a baseband signal from a phase-modulated received high frequency signal. Means and delay detection means for calculating and deriving a modulated digital signal from the baseband signal detected by the phase detection means and the baseband signal one time slot before, and the delay detection means detects the modulated digital signal. It is composed of a first differential detection unit to be derived and a second differential detection unit to remove a frequency error from the modulated digital signal derived by the first differential detection unit.

In the above-mentioned dual differential encoding communication device,
Said phase detection means, the frequency F _C of the carrier, the symbol rate F _B of the modulated digital signal, for positive integer N, | having ≧ (1/2) · N · F B the relationship | F _C -F _L frequency F and phase detection unit in _L of the reference signal for detecting said baseband signal, extracted by the phase detection unit frequency F _C -F _L in at the baseband signal to the [pi / 2 interval of phase rotation a / A quadrature component deriving unit that performs D conversion to derive quadrature component data, and the differential detection means converts the quadrature component data into angle component data, and the angle component data and an angle one time slot before. It is preferable that the modulated digital signal is calculated and derived from the component data.

A dual differential encoding communication device for generating a received high frequency signal is generated by first differential means for delaying and adding a digital signal to be transmitted by one time slot, and the first differential means. Second differential means for delaying and adding the first modulated signal again for one time slot, phase modulating means for modulating the phase of the carrier wave by the second modulated signal generated by the second differential means, and phase modulation thereof It suffices if it is composed of a transmitting means for transmitting the signal generated by the means.

[0008]

The quadrature detection output two time slots before detected by the phase detection means, where Δφ is an initial phase angle value, Δω is a phase error per time slot due to a frequency error, and S1 and S2 are primary differential phase differences. (Cos (Δφ), s
in (Δφ)), the quadrature detection output one time slot before is (cos (Δφ + Δω + S2), sin (Δφ + Δω +
S2)), the current quadrature detection output is (cos (Δφ + Δω
+ S1 + S2), sin (Δφ + Δω + S1 + S2))
Then, the differential detection operation two time slots before is as follows: I2 ′ = cos (Δφ) · cos (Δφ + Δω + S2) + sin (Δφ) · sin (Δφ + Δω + S2) = cos (Δω + S2) Q2 ′ = cos (Δφ) · sin (Δφ + Δω + S2) ) −sin (Δφ) · cos (Δφ + Δω + S2) = sin (Δω + S2) Similarly, in the differential detection calculation one time slot before, I1 ′ = cos (Δφ + Δω + S2) · cos (Δφ + Δω + S1 + S2) + sin (Δφ + Δω + S2) + sin (Δ2 + Sω) Sin = Cos (Δω + S1) Q1 ′ = cos (Δφ + Δω + S2) · sin (Δφ + Δω + S1 + S2) −sin (Δφ + Δω + S2) · cos (Δφ + Δω + S1 + S2) = sin (Δω + S1), and the term of Δφ is obtained by the first-order differential detection. When these are further detected by delay detection, I1 = cos (Δω + S2) · cos (Δω + S1) + sin (Δω + S2) · sin (Δω + S1) = cos (S1-S2) Q1 = cos (Δω + S2) · sin (Δω + S1) −sin (Δω + S2) Cos (Δω + S1) = sin (S1-S2), and the Δω term is eliminated in the second-order differential detection. That is, the phase error due to the frequency error can be removed.

In the above-mentioned dual differential encoding communication device,
Said phase detection means, the frequency F _C of the carrier, the symbol rate F _B of the modulated digital signal, for positive integer N, | having ≧ (1/2) · N · F B the relationship | F _C -F _L a phase detection unit for detecting the baseband signal with the reference signal of frequency F _L, the frequency F _C -F _L quadrature component data in said base band [pi / 2 intervals to the signal to a / D conversion of phase rotation in And a quadrature component deriving unit for deriving the quadrature component, it is possible to obtain quadrature component data while the phase detection unit is composed of a single mixer circuit. Further, if the differential detection means is configured to convert the quadrature component data into angle component data and arithmetically derive a modulated digital signal from the angle component data and the angle component data one time slot before, This can be easily configured by continuously connecting two delay circuits to delay the component data.

[0010]

According to the dual differential encoding communication system and the apparatus thereof according to the present invention, the phase error per one time slot is modulated even with respect to the phase change due to the disturbance with an extremely simple circuit configuration. Phase unit (π for BPSK, QPSK
Now, it has become possible to provide a communication system and a device thereof that can surely compensate for a phase error even when it becomes 1/2 or more of π / 2).

[0011]

EXAMPLES Examples will be described below. Data transmission rate (symbol rate F _B ) Frequency of 150 MHz which is two-phase phase modulated [BPSK] with a modulated digital signal of 1 Mbps
The dual differential encoding communication device for receiving the high frequency signal of is composed of a transmitting device and a receiving device.

As shown in FIG. 1, the transmitter includes a first differential means 1 for delaying and adding a digital signal to be transmitted by one time slot, and a first modulation means generated by the first differential means 1. Phase differential means 2 comprising a second differential means 2 for delaying the signals again by one time slot and adding, and a ring modulator or the like for modulating the phase of the carrier wave by the second modulated signal generated by the second differential means 2. 3 and transmitting means 4 for transmitting the signal generated by the phase modulating means 3. The first differential means 1 and the second differential means 2
Is a digital delay element such as a shift register for delaying a digital signal to be transmitted by one time slot, a current signal and a delayed signal in a mod. It is made up of an adder for adding by 2.

As shown in FIG. 2, the receiving apparatus has an amplifying means 5 for amplifying a received high frequency signal, a phase detecting means 6 for detecting an orthogonal base band signal from the amplified high frequency signal, and a phase detecting means 6 thereof. A delay detection means 7 for calculating and deriving a modulated digital signal from the baseband signal detected by the above and the baseband signal one time slot before, and the delay detection means 7 is for deriving the modulated digital signal. One delay detection unit 8 and its first delay detection unit 8
And a second differential detection section 9 for removing a frequency error from the modulated digital signal derived by.

More specifically, as shown in FIG. 3, the phase detecting means 2 calculates the carrier frequency F _C , the modulated digital signal symbol rate F _B from the output signal of the amplifying means 1.
For positive integer N, | F _C -F _L | and ≧ (1/2) · N · F oscillator 61 that generates a reference signal of frequency F _L with _B the relationship, the baseband signal at the reference signal Phase detection unit 6A including a mixer circuit 62 for detection and an amplifier 63, etc.
And an orthogonal component deriving unit 6 that derives an orthogonal component from its output.
And B, and in this embodiment, F _C = 150 MH
z, F _L = 148 MHz, F _B = 1 MHz, and N = 1. The orthogonal component deriving unit 6B has a frequency of 8 MHz.
Of the clock oscillator 64 and an A / D converter 65 that converts the baseband signal into a digital signal in synchronization with the clock signal from the clock oscillator 64, and has a frequency F _C -F _L (= 2 MHz). ), The baseband signal that beats at A) is A / D converted at intervals of π / 2.

The differential detection means 7 converts the quadrature component data converted into digital data at π / 2 intervals into angle component data 71, the angle component data obtained by the angle converter 71 and the time component one time slot before. Delay detection circuits 8 and 9 for calculating and deriving a modulated digital signal from angle component data
It consists of and. More specifically, the angle converter 71
Is 00H to 0F corresponding to the phase angle 0 ° to 360 °
ROM 73 in which the HEX data of FH is stored, shift register 72 for securing the digital signal previously converted by A / D converter 65 and having a phase difference of π / 2, and A / D
An access circuit (not shown) for reading the angle component data of the baseband signal from the ROM 73 from the digital data most recently converted by the converter 65 and the data in the shift register 72. The differential detection circuits 8 and 9 respectively include shift registers SR0 to SR7 that delay the angle component data by one time slot,
It is composed of arithmetic units 81 and 91 for subtracting the value of the shift register SR7 and the latest angle component data. That is, the arithmetic unit 81 functions as a first differential detection unit for deriving a modulated digital signal, and the arithmetic unit 91 functions as a second differential detection unit for removing a frequency error from the modulated digital signal derived by the first differential detection unit. Constitute. That is, if the outputs of the arithmetic units 81 and 91 are 00H, that is, if the time component of one time slot before and the angle component data of this time are equal, the data of the previous time and the data of this time are equal,
If the outputs of the arithmetic units 81 and 91 are 80H, that is, if the phase data of the angle component data of one time slot before and this time is inverted, it is determined that the data of the previous time and the data of this time are different. Here, the arithmetic units 81 and 91 are 8-bit subtracters that indicate 00H at 0 ° and 80H at 180 °.

Another embodiment will be described below. In the above embodiment, the data transmission rate (symbol rate F _B ) is 1 Mbps.
A high-frequency signal with a frequency of 150 MHz that has been subjected to two-phase phase modulation [BPSK] with a modulated digital signal of 148 MHz.
Has been described in the reference signal for the orthogonal detection circuit of the single mixer method of phase detection, data transmission speed, the carrier frequency is optional rather than limited to these values, the reference wave frequency, | F _C -F _L ｜ ≧ (1/2) ・ N ・
Any frequency F _L that satisfies F _B is arbitrary. In the above embodiment, the two-phase phase modulation [BPSK] has been described.
The present invention is not limited to this and can be applied to arbitrary phase modulation, and may be, for example, quadrature phase modulation [QPSK].
In this case, the output of the calculator is 0, π / 2, π, 3
Binary data of 00B, 01B, 10B, 11B corresponding to π / 2 is obtained.

In the previous embodiment, the differential detection means 7 converts the quadrature component data into angle component data, and calculates and derives the modulated digital signal from the angle component data and the angle component data one time slot before. However, as the delay detection means 7, as shown in FIG. 4, the shift register SR for delaying the quadrature component data derived by the quadrature component deriving unit 6B by one time slot is used.
0 ', ..., SR8' and an operation unit 8 for performing the following operations
1'to form a first differential detection unit 8'and a pair of orthogonal component data derived by the first differential detection unit 1
Delay circuits SR9 'and SR1 for delaying time slots
The second differential detection unit 9 ′ may be configured by 0 ′ and the calculation unit 91 ′. I (n) = _Si (n) * _Si-1 (n) + _Si (n-1) * _Si-1 (n-1) Q (n) = _-Si (n) * _{Si- 1} (n-1) + S _i (n-1) · S _i-1 (n)

In the above embodiment, the phase detection means for detecting a baseband signal orthogonal to the received high frequency signal is used as | F for the frequency F _{C of} the carrier, the symbol rate F _B of the modulated digital signal, and a positive integer N. A phase detector 6A for detecting the baseband signal with a reference signal having a frequency F _L having a relationship of _C −F _L | ≧ (1/2) · N · F _B, and a frequency F _C −F _L
The quadrature component deriving unit 6B for deriving the quadrature component data by A / D converting the baseband signal whose phase is rotated at π / 2 intervals is shown in FIG. As shown, an oscillator 61 ′ that generates a reference signal having a frequency F _L equal to the frequency F _C of the carrier wave and a phase shifter 6 that generates an orthogonal reference signal having a π / 2 phase different from that of the reference signal.
2 ', a pair of mixer circuits 63' and 64 'that generate baseband signals having different π / 2 phases, and A / D converters 65' and 66 'that convert their outputs into digital data.
You may comprise with. In this case, I (n) = S _i (n) · S _i−1 (n) + S _i (n−1) · S _i−1 (n−1) Q (n) = − S _i (n ) .S _i-1 (n-1) + S _i (n-1) .S _i-1 (n) by the delay circuits 80 'and 90' and the arithmetic units 81 'and 91'. , The first differential detection section 8'and the second differential detection section 9 '. This method is 4 / π
It can be easily applied to a narrow band type modulation system such as shift QPSK.

It should be noted that reference numerals are given in the claims for convenience of comparison with the drawings, but the present invention is not limited to the structures of the accompanying drawings by the entry.

[Brief description of drawings]

FIG. 1 is a circuit block configuration diagram of a dual differential encoding communication device on a transmission side.

FIG. 2 is a circuit block configuration diagram of a receiving side dual differential encoding communication device.

FIG. 3 is a circuit block configuration diagram of a receiving-side dual differential encoding communication device according to another embodiment.

FIG. 4 is a circuit block configuration diagram of a receiving side dual differential encoding communication device according to another embodiment.

FIG. 5 is a circuit block configuration diagram of a receiving side dual differential encoding communication device showing another embodiment.

[Explanation of symbols]

 6 Phase Detector 7 Delay Detector 6 First Delay Detector 7 Second Delay Detector

Claims (4)

[Claims] 1. A first modulated signal obtained by delaying and adding a digital signal to be transmitted by one time slot and again being delayed by one time slot and added to generate a second modulated signal, the phase of a carrier wave is modulated and transmitted. And the first modulation obtained by phase-detecting a quadrature baseband signal from the received high-frequency signal and performing delay detection from the baseband signal and the baseband signal one time slot before. A double differential encoding communication system comprising a double delay detection system in which a signal is again subjected to one time slot delay detection and demodulated into the digital signal to be transmitted. 2. A phase detection means (6) for detecting a baseband signal from a phase-modulated received high frequency signal, a baseband signal detected by the phase detection means (6) and a baseband signal one time slot before. And a delay detection means (7) for calculating and deriving a modulated digital signal from the above. The delay detection means (7) is a first delay detection section (8) for deriving a modulated digital signal, and its first delay detection. Division (8)
And a second differential detection section (9) that removes a frequency error from the modulated digital signal derived by. 3. The phase detection means (6) is adapted to: | F _C −F _L | ≧ (1/2) · for the frequency F _{C of} the carrier wave, the symbol rate F _B of the modulated digital signal, and the positive integer N. A phase detection unit (6A) for detecting the baseband signal with a reference signal of frequency F _L having a relationship of N · F _B, and the baseband extracted by the phase detection unit and rotating in phase at frequency F _C −F _L And a quadrature component derivation unit (6B) for deriving quadrature component data by A / D converting the signal at π / 2 intervals. 3. The dual differential encoding communication device according to claim 2, wherein the dual differential encoding communication device is configured so as to be converted into data, and a modulated digital signal is calculated and derived from the angle component data and the angle component data one time slot before. 4. A dual differential encoding communication device for generating a received high frequency signal according to claim 2 or 3, wherein first differential means (1) delays digital signals to be transmitted by one time slot and adds the digital signals. 1), a second differential means (2) for delaying the first modulated signal generated by the first differential means (1) again by one time slot, and adding the second differential means (2). Phase modulation means (3) for modulating the phase of the carrier wave by the second modulation signal generated by the, and transmission means (4) for transmitting the signal generated by the phase modulation means (3).
A dual differential encoding communication device comprising: