JPH05205493A - Boosted voltage controlling circuit - Google Patents

Abstract

PURPOSE:To provide a boosted voltage controlling circuit which is reduced in its circuit area while securing a desired time constant. CONSTITUTION:A level transforming circuit 1 level-transforms a clock signal CLK based on a boosted power supply voltage Vpo which is boosted by a booster circuit and outputs boosted block signal, the inverse of VCLK. A time constant circuit 2 decreases the rise of the boosted power supply voltage Vpo by the time constant which is set by a resistance and a capacitance and outputs an output voltage Vpp. The time constant operation is constructed so that it performs an intermittent operation based on a boosted clock signal, the inverse of VCLK and the boosted voltage controlling circuit is constituted of the circuit 1 and 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boosted voltage control circuit for controlling the rising speed of a boosted voltage generated by a booster circuit in order to write and erase a memory cell in a nonvolatile memory such as an EEPROM. is there.

A nonvolatile memory such as an EEPROM requires a write voltage or an erase voltage higher than a normal power supply voltage when writing cell information in a storage cell or erasing cell information stored in a storage cell. .. The steeper the rising of the write voltage and the erase voltage during the write and erase operations, the higher the write and erase efficiency. However, if the rising edges of the write voltage and the erase voltage are too steep, the memory cell may be destroyed. Therefore, the boosted output voltage of the booster circuit is output via the boosted voltage control circuit that controls the rising speed.

[0003]

2. Description of the Related Art In a conventional EEPROM, a booster circuit for generating a write voltage and an erase voltage and a booster voltage control circuit for controlling a rising speed of a boosted output voltage of the booster circuit are formed in the same chip. The boosted voltage control circuit is composed of a time constant circuit composed of a resistor and a capacitor, and operates so as to slow down the rising speed of the boosted output voltage generated by the booster circuit to a desired speed. The time constant of such a boost voltage control circuit is usually several μs.
It is set to a few msec from c.

[0004]

However, in the boosted voltage control circuit as described above, in order to secure a desired time constant, a capacitor having a large capacitance value and a resistor having a large resistance value are required. Will increase. Therefore, there is a problem that the chip area of the EEPROM having such a boosted voltage control circuit increases.

An object of the present invention is to provide a boost voltage control circuit which can reduce the circuit area while securing a desired time constant.

[0006]

FIG. 1 illustrates the principle of the present invention. That is, the level conversion circuit 1 level-converts the clock signal CLK based on the boosted power supply Vpo boosted by the booster circuit and outputs the boosted clock signal bar VCLK,
The time constant circuit 2 slows the rise of the boosting power source Vpo with a time constant set by a resistor and a capacitance to output an output voltage Vpp, and the time constant operation is intermittently based on the boosting clock signal bar VCLK. In this way, the level conversion circuit 1 and the time constant circuit 2 constitute a boost voltage control circuit.

Further, as shown in FIG. 2, the time constant circuit 2
Is an N-channel MOS transistor Tr6, which is intermittently turned on based on the boosted clock signal VCLK, supplies a charging current to a capacitor C from a boosting power source Vpo, and a charging potential of the capacitor C is input to a gate. The boosted power source Vpo is supplied to the drain of Tr7,
The output voltage Vpp is output from the source of the transistor Tr7.

[0008]

The output voltage Vpp output from the time constant circuit 3 is the resistance and capacity of the time constant circuit 3 and the boosted clock signal bar VC.
It can be set based on the duty ratio of LK.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of the boosted voltage control circuit, which is composed of a level conversion circuit 1 and a time constant circuit 2.

The level conversion circuit 1 includes an N-channel MOS transistor Tr1, a P-channel MOS transistor Tr2 and a P-channel MOS transistor Tr2.
Channel MOS transistor Tr3 and N channel MOS
It is composed of an inverter circuit 3 composed of a transistor Tr4.

The clock signal CLK is input to the drain of the transistor Tr1, and the source of the transistor Tr1 is connected to the input terminal of the inverter circuit 3 and also to the drain of the P-channel MOS transistor Tr2. The source of the transistor Tr3 of the inverter circuit 3 is supplied with a boosted output voltage Vpo of a booster circuit (not shown) as a high potential side power source, and the source of the transistor Tr4 is supplied with a power source Vss as a low potential side power source.

The boosted output voltage Vpo is supplied to the source of the transistor Tr2, and the gate is connected to the output terminal of the inverter circuit 3. The output signal VCLK of the inverter circuit 3 is output to the time constant circuit 2. In the time constant circuit 2, the boosted output voltage Vpo is supplied to the drain and gate of the N-channel MOS transistor Tr5, and the source of the transistor Tr5 is connected to the positive terminal of the capacitor C via the transistor Tr6.
The output signal bar VCLK of the inverter circuit 3 is input to the gate of the transistor Tr6, and the power source Vss is connected to the negative terminal of the capacitor C.

The positive terminal of the capacitor C is an N channel M
It is connected to the gate of the OS transistor Tr7, the boosted output voltage Vpo is supplied to the drain of the transistor Tr7, and the output voltage Vpp used as a write voltage and an erase voltage is output from the source.

The transistors Tr2, Tr3, Tr
4, Tr5, Tr6, Tr7 and the capacitor C are of high withstand voltage type corresponding to the boosted output voltage Vpo. Next, the operation of the boosted voltage control circuit configured as described above will be described with reference to FIG.

The clock signal C is applied to the transistor Tr1.
When LK is input, the clock signal CLK is input to the inverter circuit 3 via the transistor Tr1 which is always on. Then, the inverter circuit 3 inverts the clock signal CLK and changes the output signal bar VCLK between the boosted output voltage Vpo and the power supply Vss.
To the gate of the transistor Tr6 of the time constant circuit 2.

In the time constant circuit 2, the transistor Tr5 is always on, and the transistor Tr6 is turned on when the output signal VCLK becomes H level. Therefore, the capacitance C has the same capacitance C as the on resistance of the transistors Tr5 and Tr6.
Electric charges are charged every time the transistor Tr6 is turned on based on the time constant defined by the capacitance value of, and the output voltage Vp1 of the same capacitance C rises based on the time constant each time the transistor Tr6 is turned on.

Then, the transistor Tr7 is turned on based on the output voltage Vp1 of the capacitor C, but the source potential of the transistor Tr7, that is, the output voltage Vpp is equal to or higher than the gate potential of the transistor Tr7 lowered by the threshold value of the transistor Tr7. Output voltage Vpp rises following the output voltage Vp1 of the capacitor C.

As described above, in the time constant circuit 2, the time constant set by the ON resistance of the transistors Tr5 and Tr6 and the capacitance value of the capacitance C is delayed by the clock signal CLK, and based on the delayed time constant. The output voltage Vpp is output.
Therefore, for example, the time constant of the time constant circuit 2 can be changed by changing the duty ratio of the clock signal CLK. For example, the duty ratio of the clock signal CLK is set to 5
When it is set to 0%, an equivalent time constant can be obtained even when the capacitance value of the capacitance C is set to 1/2 as compared with the case where the charging current is constantly supplied to the capacitance C via the transistors Tr5 and Tr6. As a result, the circuit area of the boosted voltage control circuit can be reduced.

[0019]

As described above in detail, the present invention exerts an excellent effect of providing a boosted voltage control circuit capable of reducing a circuit area while securing a desired time constant.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation of one embodiment.

[Explanation of symbols]

 1 level conversion circuit 2 time constant circuit CLK clock signal bar VCLK boosted clock signal Vpp output voltage Vpo boosted power supply Tr6 N channel MOS transistor Tr7 N channel MOS transistor C capacity

Claims (2)

[Claims] 1. A level conversion circuit (1) for level-converting a clock signal (CLK) based on a boosting power supply (Vpo) boosted by a boosting circuit and outputting a boosting clock signal (VCLK), said boosting power supply ( A time constant circuit that outputs an output voltage (Vpp) in which the rise of (Vpo) is slowed down by a time constant set by a resistor and a capacitance, and the time constant operation is an intermittent operation based on the boosting clock signal (VCLK). A boosted voltage control circuit comprising (2) and: 2. The time constant circuit (2) is turned on intermittently based on the boosting clock signal (VCLK).
Channel MOS transistor (Tr6) for boosting power supply (Vp
N-channel MOS in which a charging current is supplied from o) to the capacitor (C) and the charging potential of the capacitor (C) is input to the gate.
The booster power source (Vp
2. The boosted voltage control circuit according to claim 1, wherein the output voltage (Vpp) is output from the source of the transistor (Tr7).