JPH05204037A - Camera - Google Patents

Abstract

PURPOSE:To set the optimum cut-off frequency of a filter without making a cost high by providing a filter circuit limiting frequency band to the frequency band previously set according to the cycle of a reproducing signal. CONSTITUTION:The output signal of a magnetic head 1 is amplified by a differential amplifier 11, filter clock is supplied to a switched capacitor filter 12 by a logic circuit 29 in accordance with the clock signal cycle of a pulse position modulating signal. The output of the switched capacitor filter 12 is inputted to a multiplying circuit 27, and another input of the multiplying circuit 27 is supplied by the output of a D/A converter 28. Consequently, the output of the D/A converter 28 is controlled by the pulse position modulating signal and the clock latch signal from the logic circuit 29, and the output amplitude of the multiplying circuit 27 is controlled in a state where the amplitude of the pulse position modulating signal is made fixed according to the clock signal cycle of the pulse position modulating signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a camera using a film with a magnetic recording portion, and more particularly to a reproducing circuit for reproducing information recorded in the magnetic recording portion. .

[0002]

2. Description of the Related Art A conventional reproducing circuit is constructed as shown in the specification and drawings of an application (Jan. 6, 1992) filed by the same applicant as the present application.

FIG. 12 is a circuit block diagram showing a schematic structure of a conventional magnetic recording data reproducing apparatus as described above.
In the figure, 1 is a magnetic head, 2 is a magnetic data reproducing circuit, 3 is a CPU (central processing unit) for controlling the whole, 4 is a switch, 5 is photometry (AE), distance measurement (AF), and shutter drive. (SH) control circuit, 6 battery, 7 film feeding motor drive circuit, 8 film feeding motor, 9
Is a photo reflector for detecting perforations on the film, and 10 is an A / D converter circuit for detecting the voltage of the battery 6.

FIG. 13 is a circuit diagram showing details of the magnetic data reproducing circuit. In the figure, 11 is a differential amplifier (for example, AD524 manufactured by Analog Devices), 12 is a switched capacitor filter (for example, LTC1064-3 manufactured by Linear Takenology), 13 and 14 are reference voltages,
15 and 16 are voltage comparison circuits (for example, LM290 manufactured by TI).
3) and 17 are RS flip-flops (for example, S manufactured by TI)
N74279), 18 is an oscillation circuit, 19 is a counter circuit (for example, SN74163 manufactured by TI), 20, 21 are knot circuits, 22 and 23 are AND circuits, 24 is an OR circuit, 2
5 is a D flip-flop.

The magnetic signal recorded on the film is converted into a voltage signal by the magnetic head 1 and amplified by the differential amplifier 11. Then, by passing through the switched capacitor filter 12, the frequency band is band-limited and the signal-to-noise ratio is improved. Next, the voltage is input to the voltage comparison circuits 15 and 16, and the voltage comparison circuit 15 outputs 1 when the signal voltage is lower than the voltage value of the reference voltage 13, and outputs 0 when it is high. Further, the voltage comparison circuit 16 outputs 1 when the signal voltage is higher than the voltage value of the reference voltage 14,
When it is low, 0 is output. Next, in the RS flip-flop circuit 17, the output Q becomes 0 when the reset signal output from the voltage comparison circuit 15 becomes 1, and the output Q becomes 1 when the set signal output from the voltage comparison circuit 16 becomes 1. .. These are output to the CPU 3.

The cutoff frequency of the switched capacitor filter 12 is controlled by the frequency of the filter clock f _clk input as shown in FIG. Therefore,
The oscillation frequency from the oscillation circuit 18 is divided by the filter clock data D0 to D3 from the CPU 3, and the filter clock can be controlled. After all, the cutoff frequency of the switched capacitor filter 12 can be controlled by the filter clock data D0 to D3 of the CPU 3.

FIG. 15 is a flow chart showing a series of operations of the circuit of FIG. In addition, S in the figure represents a step. First, the state of the switch 4 is checked (S30
1) Then, when the switch 4 is turned on, the voltage of the battery 6 is converted into digital data by the A / D converter 10, and the data is stored in the CPU 3 (S302). Next, the digital data is compared with the minimum camera drivable voltage data V _min preset in the CPU 3 (S303).
If the digital data is less than the data V _min , the operation ends. If V _min or more, take a photograph (S3
Move to 04). In this picture taking operation, the control circuit 5
The known photometry and distance measurement are performed, and the image is taken based on the data. After that, the film is fed (S3
05), a series of operations is completed. The magnetic recording data is S
During the film feeding operation of 305, it is detected as a signal by the reproducing head 1, amplified by the magnetic data reproducing circuit 2, converted into a digital signal, and then taken into the CPU 3.

FIG. 16 is a flow chart showing the details of the film feeding operation of S305 shown in FIG. After the photography operation (process result of S304) is completed, the remaining voltage digital data of the battery 6 (process result of S302) is compared with the preset filter time constant switching point voltage V ₁ (S4).
01) and if the digital data is smaller than V _1, then CP
The filter clock data AH (1010) is output from U3 to the magnetic data reproducing circuit 2. Then, the filter clock outputs a signal having a frequency of 1/20 of the oscillation circuit 18 (S402). Next, when the digital data is V ₁ or more, the CPU 3 outputs the filter clock data CH (1100) to the magnetic data reproducing circuit 2. Then, the filter clock outputs a signal having a frequency of 1/12 of the oscillation circuit 18 (S403). Therefore, when the voltage of the battery 6 is high, that is, when the film feeding speed is fast, the output signal from the magnetic head 1 is large, and the frequency is high, the cutoff frequency of the switched capacitor filter 12 is increased to increase the cutoff frequency of the battery 6. When the voltage is low, that is, when the film feeding speed is slow, the cutoff frequency of the switched capacitor filter 12 is lowered to limit the band of the reproduced signal, and the noise voltage is lowered to accurately reproduce the magnetic data. It can be performed.

After setting the filter in S402 or 403, the counter inside the CPU 3 for counting the pulses generated in the photocoupler 9 is reset (S404),
The film feeding motor drive circuit 7 is started (S40
5) By the perforation on the film fed by the film feeding motor 8, the photo reflector 9
To start counting pulses generated from (S40
6). Then, as described above, the reproduction signal from the magnetic head 1 is converted into a digital signal by the magnetic data reproduction circuit 2 and taken into the CPU 3 (S407). When the perforation detection pulse is sent from the photo reflector 9 to the CPU 3, the number is counted up (S408).
It is checked whether the count value of the pulse is equal to or more than the preset film feeding stop count value C (S409). The film feeding motor drive circuit 7 stops the film feeding motor 8 (S410).

As described above, since the cutoff frequency of the filter is switched stepwise between high speed and low speed depending on the residual voltage of the battery 6, it corresponds to the magnetic recording data reproducing frequency that follows the film feeding speed, and an unnecessary filter is used. By reducing the band of, it is possible to reduce the influence of noise and the like, and it is possible to improve the reproduction capability of magnetic recording data.

[0011]

In the magnetic recording / reproducing circuit in the conventional camera as described above, the cutoff frequency of the filter can be accurately set only by the battery voltage depending on the temperature condition, the load condition of the film motor, and the like. could not.

The present invention has been made in order to solve such a conventional problem, and is provided with a magnetic recording / reproducing circuit capable of setting a cutoff frequency of a filter according to a film feeding speed. An object of the present invention is to provide a camera capable of accurately reading recorded magnetic data.

[0013]

In order to achieve the above object, the magnetic recording / reproducing circuit in the camera of the present invention comprises, in claim 1, a filter circuit for filtering the output of the magnetic head, and A means for measuring the cycle of the reproduced signal from the filter circuit is provided, and a filter circuit for limiting the frequency band of the reproduced signal to a preset frequency band according to the cycle of the reproduced signal is provided. 2 has a means for measuring the amplification degree of the amplification circuit for amplifying the output of the magnetic head, the cycle of the reproduction signal from the magnetic head, and the amplification circuit for setting the amplification degree to a preset amplification degree according to the cycle. And claim 3
In the above configuration, the means for measuring the cycle of the reproduced signal is also used as the decoding circuit for the pulse position modulated signal.

[0014]

In the present invention, the clock interval (cycle) of the pulse position modulation signal is measured by the counter circuit,
It is possible to obtain an accurate film feeding speed and
The cutoff frequency of the filter circuit and the amplification degree of the amplifier circuit are changed according to the cycle of the M (pulse position modulation) signal.

[0015]

1 to 7 show an embodiment of the present invention.
FIG. 1 is a block diagram of an electric circuit according to an embodiment of the present invention.
The apparatus of FIG. 1 is different from the conventional example of FIG. 11 except that an A / D converter circuit 10 is omitted, and the other points are the same, so detailed description will be omitted, but 26 is a magnetic data reproducing circuit. ..

FIG. 2 is a diagram showing the details of the magnetic data reproducing circuit 26 of FIG. 1, 27 is a multiplication circuit (for example, AD534 manufactured by Analog Devices, Inc.), 28 is a D / A converter, and 29.
Is a logic circuit.

3 and 4 show the logic circuit 2 of FIG.
It is a figure which shows the detail of 9, 30 in the figure, 31, 32, 33
Is an input terminal, and 34, 35, 38, 39, 46, 66 are D
Flip-flops, 36, 40, 43, 47, 55, 6
0, 61, 62 are knot circuits, 37, 48 are NAND circuits, 41, 42, 44, 63, 64 are AND circuits, 4
5, 65 are OR circuits, 49, 50, 67, 68, 69,
70, 71, 72, 73 are output terminals, 51, 52, 5
3, 54, 58 and 59 are 4-bit counters (for example, TI
SN74163), 56 and 57 are 4-bit latches (for example, SN74379 made by TI).

In this embodiment, a clock signal period having a constant period of the pulse position modulation signal shown in FIG. 7 is measured by a 14-bit counter consisting of 4-bit counters 51, 52, 53 and 54 shown in FIG. A filter clock signal corresponding to the clock signal period is output to control the switched capacitor filter 12 in a frequency band adapted to the pulse position signal, and at the same time, the D / A converter 28
And the multiplication circuit 27 control so that the amplitude of the pulse position modulation signal becomes constant.

The respective figures will be described below.

In FIG. 2, the output signal of the magnetic head 1 is amplified by the differential amplifier 11 and input to the switched capacitor filter 12. The switched capacitor filter 12 is supplied with its filter clock by the logic circuit 29 in accordance with the clock signal cycle of the pulse position modulation signal. The output of the switched capacitor filter 12 is input to the multiplication circuit 27. The other input of the multiplication circuit 27 is supplied by the output from the D / A converter 28. Therefore, the D / A converter 2 receives the pulse position modulation signal clock latch signal from the logic circuit 29.
The output amplitude of the multiplication circuit 27 is controlled according to the clock signal cycle of the pulse position modulation signal so that the amplitude of the pulse position modulation signal becomes constant. Multiplication circuit 2
The output of 7 is input to the two voltage comparison circuits 15 and 16. The voltage comparison circuit 15 outputs 1 when the pulse position modulation signal falls below the voltage value of the reference voltage 13 and outputs 0 when it rises.

The voltage comparison circuit 16 outputs 1 when the pulse position modulated signal rises above the voltage value of the reference voltage 14, and outputs 0 when it falls.

The logic circuit 29 inputs the output of the voltage comparison circuit 16 into the input terminal 30 and inputs the output of the voltage comparison circuit 15 into the input terminal 33. Further, the output of the oscillation circuit 18 is input to the input terminal 31, and as is apparent from FIG. 7, the input signals are not applied to the input terminals 30 and 33 at the same time.

In FIG. 3, when the output from the voltage comparison circuit 16 changes from 0 to 1, that is, the input terminal 30 changes from 0 to 1, 1 is output to the output terminal 50 two system clocks later. When the input terminal 33 changes from 0 to 1, 0 is output to the output terminal 50 after the system clock. At the same time, 0 is output to the output terminal 49 for one system clock. This is the signal-DND pulse position modulation signal output at every clock of the pulse position modulation signal.

4-bit counters 51, 52, 53, 54
The 14-bit counter consisting of is loaded with input data when the -DND pulse position modulation signal becomes 0. Here, the input data is C000H in hexadecimal notation. If the oscillation frequency of the oscillation circuit 18 is 8 MHz, the carry output of the 4-bit counter 51 becomes 1 after 2.048 mS from the start of counting. The 6-bit latch composed of the 4-bit latches 56 and 57 is set to 1 when the -DND pulse position modulation signal becomes 0.
Latch the upper 6 bits of the 4-bit counter.

Output terminals 68, 69, 70, 71, 72,
The upper 6 bits of the 14-bit counter are output to 73 at the clock cycle of the pulse position modulation signal. That is,
This is the same as counting the clock cycle of the pulse position modulation signal with 6 bits. Output terminals 68, 69, 7
0, 71, 72, 73 are output to the D / A converter 28, and the amplification degree of the multiplication circuit 27 is changed according to the clock cycle of the pulse position modulation signal.

The 6-bit counter including the 4-bit counters 58 and 59 loads the negative output of the 6-bit latch every time it counts up and outputs the Carry signal. Therefore, the cycle of outputting the carry signal changes according to the clock cycle of the pulse position modulation signal.

The D flip-flop 66 inverts the output every time the carry signal of the 4-bit counter 58 becomes 1. The output is switched capacitor filter 12
Output as a filter clock to.

In this embodiment, the clock cycle of the pulse position modulated signal / filter clock cycle = 128.

The relationship between these counters and latches is shown in FIG. When the PPM clock counter is CF00H-
When the DND pulse position modulation signal becomes 0, CFH is latched in the PPM clock latch. After that several system clocks, when the filter clock counter sets the Carry signal to 1 and loads the negative output of the PPM clock latch, it loads F0H and continues counting up. After that, F0H is loaded every time the Carry signal becomes 1. Next, when the PPM clock counter is CE00H,
-When the DND pulse position modulation signal becomes 0, CEH is latched in the PPM clock latch. Therefore, after that, the filter clock counter outputs the Carry signal at 1
Every time, F1H is loaded.

FIG. 6A shows the relationship between the output voltage of the switched capacitor filter 12 and the clock cycle of the pulse position modulation signal. The signal amplitude from the magnetic head 1 is
Proportional to film feed rate. Further, the noise voltage is proportional to the clock cycle because the filter clock of the switched capacitor filter 12 is changed by the logic circuit 29.

Here, when the output level of the D / A converter 28 is set so that the output of the multiplication circuit 27 becomes constant when the output is FFH and C0H, the output amplitude of the multiplication circuit 27 is as shown in FIG. As shown in b), it becomes constant regardless of the clock cycle of the pulse position modulation signal. Therefore, even if the reference voltage of the voltage comparison circuit is constant, the magnetic data information can be reproduced accurately regardless of the clock cycle of the pulse position modulation signal.

FIG. 8 is a diagram showing details of a logic circuit according to another embodiment of the present invention, which corresponds to FIG. In FIG. 8, 4-bit counters 51, 52, 53, 5
4 constitutes a 16-bit PPM clock counter. Therefore, as compared with FIG.
Double), the clock period of the pulse position modulation signal can be counted. Further, by providing the 4-bit counter 74 and counting 2 bits, when the -DND pulse position modulation signal becomes 0 four times, the -4DND pulse position modulation signal becomes 0 once. Therefore, the 16-bit PPM clock counter counts four clock cycles of the pulse position modulation signal, and the PPM clock latch also latches four clock cycles of the pulse position modulation signal as 6 bits.

With the above configuration, the filter clock cycle can be generated by the average cycle of four times of the pulse position modulation signal as compared with the first embodiment. For example,
The filter clock can be stably generated even when the jitter, which is uneven speed during film feeding, is large.

9 and 10 are views showing still another embodiment of the present invention, in which the 4-bit counters 51 and 5 shown in FIG.
The circuit which uses the count value of 2,53,54 for the demodulation of a pulse position modulation signal (pulse position modulation signal) is shown.

In FIG. 9 and FIG. 10, elements added to the circuits of FIGS. 3 and 4 are shown below. That is, in FIG. 9, reference numerals 76, 78, 80 denote knot circuits, and 77, 7
9 is an AND circuit. Due to the addition of these circuits, the output UPDPPM of the AND circuit 77 is set to 1 during one system clock when the pulse position modulation signal rises, that is, when the data signal in the pulse position modulation signal is generated.
Occurs. The output of the knot circuit 78-UPDPPPM
Simultaneously generate 0.

Next, in the circuit of FIG. 10, 81, 82,
84, 95, 96, 101, 102 are AND circuits, 8
3, 85, 97, 103 are knot circuits, 86, 98, 1
Reference numeral 04 is an OR circuit, and 87, 88, 89, 90 are 4-bit counters (for example, SN74163 manufactured by TI).
91, 92, 93, 94 are 4-bit comparators (for example, SN7485 manufactured by TI). 99 and 105 are D flip-flops, and 100 and 106 are output terminals.

Here, the 4-bit counters 51 to 54 are set to 1
A 4-bit counter is formed, and 0 is generated at the trailing edge of the pulse position modulation signal (that is, generated by the clock signal of the pulse position modulation signal) -cleared by DNDPPM. After that, it will count up. Therefore, this 14-bit counter counts the period of the pulse position modulation signal.

Next, the 4-bit counters 87 to 90 are set to 13
It constitutes a bit counter and generates 0 at the rising edge of the pulse position modulation signal (that is, it is generated by the data signal of the pulse position modulation signal) -cleared by UPDPPPM. When the pulse position modulation signal is 0 (here, DD
When PPM≈0), this 13-bit counter stops counting. Otherwise, that is, when the pulse position modulation signal is 1 (here, DDPPM = 1), the 13-bit counter counts up. Therefore, this 13-bit counter counts between the data signal and the clock signal of the pulse position modulation signal. 4-bit comparator 91-
94 compares the outputs of the aforementioned counters. Where 1
The output of the 4-bit counter is compared by deleting the least significant bit. As a result, the position of the 14-bit counter is 1/2
To be done. The 4-bit comparators 91 to 94 are continuously connected to form a 13-bit comparator. The output AGBO of the output 4-bit comparator 91 outputs 1 when the A input (here, the output of the 14-bit counter) is larger than the B input (here, the output of the 13-bit counter).

Further, the AND circuits 101 and 102, the knot circuit 103, the OR circuit 104, and the D flip-flop 10.
The latch circuit composed of 5 outputs the output of the 11-bit comparator when the pulse position modulation signal falls (here,
It is latched at one system clock (DNPPM = 1) and is output to the output terminal 106. The latch circuit composed of the AND circuits 95 and 96, the knot circuit 97, the OR circuit 98, and the D flip-flop circuit 99 generates an error signal when either the 14-bit counter or the 13-bit counter overflows.

The logic circuit shown in FIG. 11 is similar to that shown in FIG.

[0041]

As described above, according to the present invention,
By detecting the PPM clock period, the magnetic recording / reproducing circuit was able to set the optimum cutoff frequency of the filter according to the film feeding speed without increasing the cost. As a result, it became possible to accurately read the magnetic data into the microcomputer.

[Brief description of drawings]

FIG. 1 is a block diagram of an electric circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing details of a magnetic data reproducing circuit 26 of FIG.

FIG. 3 is a diagram showing details of a logic circuit 29 in FIG.

FIG. 4 is a diagram showing details of a logic circuit 29 in FIG.

5 is a diagram illustrating the operation of the logic circuit of FIG.

FIG. 6 is a diagram illustrating operations of the multiplication circuit and the D / A converter of FIG.

FIG. 7 is a diagram illustrating a pulse position modulation signal.

FIG. 8 is a diagram showing details of a logic circuit according to another embodiment of the present invention.

FIG. 9 is a diagram illustrating a logic circuit according to still another embodiment of the present invention.

FIG. 10 is a diagram illustrating a logic circuit according to still another embodiment of the present invention.

FIG. 11 is a diagram illustrating a logic circuit according to still another embodiment of the present invention.

FIG. 12 is a conventional electric circuit block diagram.

FIG. 13 is a diagram showing details of a conventional magnetic data reproducing circuit.

FIG. 14 is a characteristic diagram of the switched capacitor filter in FIG.

FIG. 15 is a flowchart illustrating an operation of the electric circuit block diagram of FIG.

16 is a flowchart illustrating the operation of the electric circuit block diagram of FIG.

[Explanation of symbols]

1 Magnetic Head 2 Magnetic Data Reproducing Circuit 3 CPU 4 Switch 5 Control Circuit 6 Battery 7 Film Feeding Motor Drive Circuit 8 Film Feeding Motor 9 Photo Reflector 10 A / D Converter Circuit 11 Differential Amplifier 12 Switched Capacitor Filter 13, 14 Reference voltage 15,16 Voltage comparison circuit 17 RS flip-flop 18 Oscillation circuit 19 Counter circuit 20,21 Not circuit 22,23 AND circuit 24 OR circuit 25 D flip-flop 26 Magnetic data reproduction circuit 27 Multiplier circuit 28 D / A converter 29 Logic circuit 30, 31, 32, 33 Input terminal 34, 35, 38.39.46.66 D flip-flop 36, 40, 43, 47, 55, 60, 61, 62 Not circuit 37, 48 NAND circuit 41, 42 , 44, 63, 64 AND circuit 45,65 OR circuit 49,50,67,68,69,70,71,72,7
3 output terminals 51, 52, 53, 54, 58, 59 4-bit counter 56, 57 4-bit latch

Claims (3)

[Claims] 1. A camera using a film with a magnetic recording section is provided with a filter circuit for filtering an output of a magnetic head, and means for measuring a cycle of a reproduced signal from the filter circuit is provided. A camera comprising a magnetic recording / reproducing circuit having a filter circuit for limiting the frequency band of the reproduced signal to a preset frequency band according to the cycle. 2. A camera using a film with magnetic recording has means for measuring the amplification degree of an amplifier circuit for amplifying the output of the magnetic head, and a cycle of a reproduction signal from the magnetic head, and according to the cycle, A camera comprising a magnetic recording / reproducing circuit having an amplification circuit for setting a set amplification degree. 3. A camera according to claim 1, wherein in the magnetic recording / reproducing circuit according to claim 1, the means for measuring the period of the reproduced signal is also used as the decoding circuit for the pulse position modulated signal.