JPH0520367U - Surface mount circuit board - Google Patents

Surface mount circuit board

Info

Publication number
JPH0520367U
JPH0520367U JP1630791U JP1630791U JPH0520367U JP H0520367 U JPH0520367 U JP H0520367U JP 1630791 U JP1630791 U JP 1630791U JP 1630791 U JP1630791 U JP 1630791U JP H0520367 U JPH0520367 U JP H0520367U
Authority
JP
Japan
Prior art keywords
circuit board
electronic component
connection
solder
lands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1630791U
Other languages
Japanese (ja)
Other versions
JP2554012Y2 (en
Inventor
秀樹 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1991016307U priority Critical patent/JP2554012Y2/en
Publication of JPH0520367U publication Critical patent/JPH0520367U/en
Application granted granted Critical
Publication of JP2554012Y2 publication Critical patent/JP2554012Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

(57)【要約】 【目的】 表面実装用回路基板において、近接する回路
パターンとの間で橋絡や好ましくない電気的結合が生じ
難く、半田まわりが良好で、チップ立ちの生じ難い回路
基板を提供する。 【構成】 表面実装される電子部品の端子電極が重ねら
れてこれと半田付けされる略四角形状の接続ランドを表
面に形成してなる回路基板であって、その接続ランドの
うち、電子部品と重なる領域からはみ出す接続領域の角
部が直線状もしくは円弧状等に切り欠かれている表面実
装用回路基板である。
(57) [Abstract] [Purpose] In a surface-mounting circuit board, a circuit board in which bridging and unfavorable electrical coupling between adjacent circuit patterns hardly occur, soldering is good, and chip standing does not easily occur provide. A circuit board having a surface on which terminal electrodes of a surface-mounted electronic component are overlapped and soldered to the terminal electrodes, the electronic component of the connecting lands being It is a surface-mounting circuit board in which a corner portion of a connection region protruding from an overlapping region is cut out in a linear shape or an arc shape.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、フラットパッケージ型電子部品やリード端子を有しないチップ型電 子部品を載置して半田付けする表面実装用回路基板に係り、更に詳しくは、それ らの電子部品との接続ランドの形状を改良した表面実装用回路基板に関する。 The present invention relates to a surface mount circuit board on which a flat package type electronic component or a chip type electronic component without a lead terminal is placed and soldered. More specifically, the present invention relates to a land for connecting to these electronic components. The present invention relates to a surface mounting circuit board having an improved shape.

【0002】[0002]

【従来の技術】[Prior Art]

従来、表面実装用回路基板としては、図3および図4に示すように、回路基板 (1)の片面に対をなす長方形形状の接続ランド(3)、(5)を形成し、これ ら接続ランド(3)、(5)から回路パターン(3a)、(5a)を導出してな る構成が良く知られていた。 Conventionally, as a surface mounting circuit board, as shown in FIGS. 3 and 4, a pair of rectangular connecting lands (3) and (5) are formed on one surface of the circuit board (1), and these connecting lands are formed. It is well known that the circuit patterns (3a) and (5a) are derived from the lands (3) and (5).

【0003】 このような表面実装用回路基板は、それら接続ランド(3)、(5)に予め半 田ペーストを塗布しておき、例えばチップ型電子部品(7)の両端の電極(9a )、(9b)をそれら接続ランド(3)、(5)の片半分に重なるように載置し て加熱によって半田ペーストを溶かして接続ランド(3)と電極(9a)、接続 ランド(5)と電極(9b)を半田付けしたり、両端電極(9a)、(9b)が それら接続ランド(3)、(5)の片半分に重なるように電子部品(7)を載置 して仮止めし、溶融半田槽に浸漬して半田付けしていた。図3中、符号(11) は半田である。In such a surface mounting circuit board, solder paste is applied in advance to the connection lands (3) and (5), and for example, electrodes (9a) at both ends of the chip type electronic component (7), (9b) is placed so as to overlap with one half of the connection lands (3) and (5), and the solder paste is melted by heating to form the connection land (3) and the electrode (9a), and the connection land (5) and the electrode. (9b) is soldered, or the electronic component (7) is placed and temporarily fixed so that the electrodes (9a) and (9b) on both ends overlap with one half of the connection lands (3) and (5). It was dipped in a molten solder bath for soldering. In FIG. 3, reference numeral (11) is solder.

【0004】[0004]

【考案が解決しようとする課題】[Problems to be solved by the device]

しかしながら、上述した構成の表面実装用回路基板では、接続ランド(3)、 (5)、が長方形形状となっていたから、以下のような欠点があった。 However, in the surface-mounting circuit board having the above-described configuration, the connection lands (3) and (5) have a rectangular shape, and thus have the following drawbacks.

【0005】 すなわち、接続ランド(3)、(5)のうち、電子部品(7)と重ならない接 続領域(3b)、(5b)の角部(3c)、(5c)が突出した状態となり、例 えば図4のように他の回路パターン(13)が近接形成される場合には、半田( 11)による橋絡が生じたり、好ましくない電気的な結合が生じ易い。That is, among the connection lands (3) and (5), the connection regions (3b) and (5b) that do not overlap with the electronic component (7) have corners (3c) and (5c) protruding. For example, when another circuit pattern (13) is formed in proximity as shown in FIG. 4, bridging due to the solder (11) or undesired electrical coupling is likely to occur.

【0006】 また、半田(11)は融解すると球形状に広がり易いが、角部(3c)、(5 c)が突出しているから、融解から固化時の半田まわりが良好でない。Further, when the solder (11) melts, it tends to spread into a spherical shape, but since the corners (3c) and (5c) protrude, the solder surroundings from melting to solidification are not good.

【0007】 更に、角部((3c)、(5c)が突出していると、半田の固化時に電子部品 (7)に加わる半田の表面張力の中心が、接続ランド(3)、(5)上の電子部 品(7)から離れた位置にあるので、電子部品(7)にはストレスが加わり易く なる。Further, when the corners ((3c), (5c) are projected, the center of the surface tension of the solder applied to the electronic component (7) during solidification of the solder is above the connection lands (3), (5). Since the electronic component (7) is located away from the electronic component (7), stress is easily applied to the electronic component (7).

【0008】 そのため、接続ランド(3)、(5)でストレスのアンバランスがあると、図 32点鎖線のように電子部品の一方が立ち上がる、いわゆるチップ立ち(マンハ ッタン現象)を生じるおそれがあった。Therefore, if there is an imbalance of stress in the connection lands (3) and (5), there is a possibility that one side of the electronic component rises as shown by the dashed line in FIG. It was

【0009】 本考案はこのような従来の欠点を解決するためになされたもので、近接する回 路パターンとの間で橋絡や結合が生じ難く、半田まわりが良好で、チップ立ちの 生じ難い表面実装用回路基板を提供するものである。The present invention has been made in order to solve the above-mentioned conventional drawbacks. Bridging or coupling is unlikely to occur between adjacent circuit patterns, soldering is good, and chip standing is unlikely to occur. A circuit board for surface mounting is provided.

【0010】[0010]

【課題を解決するための手段】[Means for Solving the Problems]

このような課題を解決するために本考案の表面実装用回路基板は、回路基板本 体の表面に、表面実装される電子部品の端子電極が重ねられてこれと半田付けさ れる略四角形状の接続ランドを有しており、その接続ランドについて、その電子 部品と重なる側からはみ出す接続領域の角部が切り欠かれた構成となっている。 In order to solve such problems, the surface mounting circuit board of the present invention has a substantially rectangular shape in which the terminal electrodes of the electronic components to be surface mounted are stacked on the surface of the circuit board body and soldered thereto. It has connection lands, and the corners of the connection area protruding from the side overlapping the electronic component are cut out.

【0011】[0011]

【作用】[Action]

このような手段を備えた本考案では、回路基板本体の表面に形成された接続ラ ンドにおいて、その電子部品と重ならない接続領域の角部が大きく突出しないか ら、近接する他の回路パターンとの間隔が十分にとられる。 In the present invention equipped with such means, in the connection land formed on the surface of the circuit board main body, the corners of the connection area that do not overlap with the electronic component do not significantly project, so that the circuit pattern is different from other circuit patterns in the vicinity. Is sufficiently spaced.

【0012】 また、融解した半田の張力の中心が電子部品の近くに位置する。Further, the center of tension of the melted solder is located near the electronic component.

【0013】[0013]

【実施例】【Example】

以下本考案の実施例を図面を参照して説明する。なお、従来例と共通する部分 には同一の符号を付す。 An embodiment of the present invention will be described below with reference to the drawings. The same parts as those in the conventional example are designated by the same reference numerals.

【0014】 図1は本考案に係る表面実装用回路基板の一実施例を示す要部断面図である。FIG. 1 is a sectional view of an essential part showing one embodiment of a surface mounting circuit board according to the present invention.

【0015】 図において、符号(1)は従来公知の絶縁性の回路基板本体であり、上面には 一対の略四角形状の接続ランド(15)、(17)がフォトエッチング等公知の 手法によって形成されている。In the figure, reference numeral (1) is a conventionally known insulating circuit board body, and a pair of substantially rectangular connection lands (15) and (17) are formed on the upper surface by a known method such as photoetching. Has been done.

【0016】 接続ランド(15)、(17)の間隔は、これに載置する電子部品(7)の先 端が接続ランド(15)、(17)の中程まで延びるように選定されており、接 続ランド(15)、(17)の約半分が電子部品(7)の先端から突出するよう になっている。The spacing between the connection lands (15) and (17) is selected so that the tip ends of the electronic parts (7) placed on the connection lands (15) and (17) extend to the middle of the connection lands (15) and (17). About half of the connection lands (15) and (17) are projected from the tip of the electronic component (7).

【0017】 接続ランド(15)、(17)において電子部品(7)と重ならずに、その先 端から突出する接続領域(15b)、(17b)の角部(15c)、(17c) が直線状に切り欠かれており、それら切り欠き部の間から回路パターン(15a )、(17a)が導出されている。In the connection lands (15) and (17), the corner portions (15c) and (17c) of the connection regions (15b) and (17b) that do not overlap the electronic component (7) and project from the front ends thereof are formed. It is notched linearly, and the circuit patterns (15a 1) and (17a) are led out from between the notches.

【0018】 このような表面実装用回路基板では、従来例の図3と同様に、それら接続ラン ド(15)、(17)に予め半田ペースト等を塗布し、電子部品(7)の端子電 極(9a)、(9b)をそれら接続ランド(15)、(17)の片半分に重なる ように載置し、加熱によって半田付けしたり、電子部品(7)を回路基板本体( 1)に仮止めして溶融半田槽にて半田付けする。In such a surface mounting circuit board, as in the case of FIG. 3 of the conventional example, solder paste or the like is applied in advance to the connection lands (15) and (17), and the terminal electrodes of the electronic component (7) are The poles (9a) and (9b) are placed so as to overlap with one half of the connection lands (15) and (17) and soldered by heating, or the electronic component (7) is mounted on the circuit board body (1). Temporarily fix and solder in the molten solder bath.

【0019】 上述した実施例では、接続ランド(15)、(17)における突出した接続領 域(15b)、(17b)の角部(15c)、(17c)を直線状に切り欠く構 成であったが本考案はこれに限定されない。In the above-described embodiment, the protruding connection areas (15b) and (17b) of the connection lands (15) and (17) are formed by linearly cutting out the corner portions (15c) and (17c). However, the present invention is not limited to this.

【0020】 例えば図2に示すように、接続ランド(19)、(21)における接続領域の 角部を曲線状に切り欠く構成も可能である。For example, as shown in FIG. 2, it is possible to have a configuration in which the corner portions of the connection regions of the connection lands (19) and (21) are cut out in a curved shape.

【0021】 さらに、図示はしないが、多角形状に切り欠く構成も可能であるし、半田レジ ストによって、実質的に接続領域を切り欠いてもよい。Further, although not shown, a polygonal cutout may be formed, or the connection region may be substantially cutout by a solder resist.

【0022】[0022]

【考案の効果】[Effect of the device]

以上説明したように本考案の表面実装用回路基板は、回路基板本体(1)の表 面に形成した略四角形状の接続ランド(15)、(17)、(19)、(21) について、電子部品(7)を重ねたときにはみ出る接続領域(15b)、(17 b)の角部(15c)、(17c)を切り欠いたから、近接する回路パターンと の間の間隔を良好に保つことができ、橋絡や好ましくない電気的結合を防ぐこと ができ、また半田まわりも良好となる。 As described above, in the surface mounting circuit board of the present invention, the connection lands (15), (17), (19) and (21) having a substantially rectangular shape formed on the surface of the circuit board body (1) are Since the corners (15c) and (17c) of the connection regions (15b) and (17b) protruding when the electronic components (7) are stacked are cut out, maintain a good distance between adjacent circuit patterns. It is possible to prevent bridging and undesired electrical coupling, and the soldering area is also improved.

【0023】 しかも、半田の融解から固化時における半田の表面張力の中心が電子部品(7 )に近付くので、電子部品(7)にストレスが加わり難いから、チップ立ちが生 じ難い。Moreover, since the center of the surface tension of the solder when the solder is melted and solidified approaches the electronic component (7), stress is not easily applied to the electronic component (7), and chip standing is less likely to occur.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案に係る表面実装用回路基板の一実施例を
示す要部平面図である。
FIG. 1 is a main part plan view showing an embodiment of a surface mounting circuit board according to the present invention.

【図2】本考案の他の実施例を示す要部平面図である。FIG. 2 is a plan view of an essential part showing another embodiment of the present invention.

【図3】従来の表面実装用回路基板を示す要部断面図
(一部、側面図で示す)である。
FIG. 3 is a cross-sectional view (partially shown in side view) of a main part of a conventional surface mounting circuit board.

【図4】図3の要部平面図である。FIG. 4 is a plan view of an essential part of FIG.

【符号の説明】[Explanation of symbols]

(1) 回路基板本体 (3)(5)(15)(17)(19)(21) 接続
ランド (3b)(5b)(15b)(17b) 接続領域 (3c)(5c)(15c)(17c) 角部 (7) 電子部品 (9a)(9b) 端子電極 (11) 半田 (13) 他の回路パターン
(1) Circuit board body (3) (5) (15) (17) (19) (21) Connection land (3b) (5b) (15b) (17b) Connection area (3c) (5c) (15c) ( 17c) Corner (7) Electronic component (9a) (9b) Terminal electrode (11) Solder (13) Other circuit pattern

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 表面実装される電子部品の端子電極が重
ねられてこれと半田付けされる略四角形状の接続ランド
を回路基板本体の表面に形成してなる表面実装用回路基
板において、 前記接続ランドのうち前記電子部品と重なる領域からは
み出す接続領域の角部が切り欠かれてなることを特徴と
する表面実装用回路基板。
1. A surface-mounting circuit board in which terminal electrodes of a surface-mounting electronic component are overlapped and soldered with the terminal electrodes are formed on the surface of a circuit board body. A surface mounting circuit board, characterized in that a corner portion of a connection region protruding from a region of the land overlapping with the electronic component is cut out.
JP1991016307U 1991-03-19 1991-03-19 Circuit board for surface mounting Expired - Lifetime JP2554012Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991016307U JP2554012Y2 (en) 1991-03-19 1991-03-19 Circuit board for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991016307U JP2554012Y2 (en) 1991-03-19 1991-03-19 Circuit board for surface mounting

Publications (2)

Publication Number Publication Date
JPH0520367U true JPH0520367U (en) 1993-03-12
JP2554012Y2 JP2554012Y2 (en) 1997-11-12

Family

ID=11912881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991016307U Expired - Lifetime JP2554012Y2 (en) 1991-03-19 1991-03-19 Circuit board for surface mounting

Country Status (1)

Country Link
JP (1) JP2554012Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012015329A (en) * 2010-06-30 2012-01-19 Toshiba Lighting & Technology Corp Circuit board

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166377U (en) * 1981-04-13 1982-10-20
JPH01119094A (en) * 1987-10-31 1989-05-11 Toshiba Corp Printed board
JPH0265293A (en) * 1988-08-31 1990-03-05 Toyo Commun Equip Co Ltd Pattern on printed board for surface mounting
JPH02214196A (en) * 1989-02-15 1990-08-27 Toyo Commun Equip Co Ltd Wiring pattern of printed board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166377U (en) * 1981-04-13 1982-10-20
JPH01119094A (en) * 1987-10-31 1989-05-11 Toshiba Corp Printed board
JPH0265293A (en) * 1988-08-31 1990-03-05 Toyo Commun Equip Co Ltd Pattern on printed board for surface mounting
JPH02214196A (en) * 1989-02-15 1990-08-27 Toyo Commun Equip Co Ltd Wiring pattern of printed board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012015329A (en) * 2010-06-30 2012-01-19 Toshiba Lighting & Technology Corp Circuit board

Also Published As

Publication number Publication date
JP2554012Y2 (en) 1997-11-12

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