JPH0520247A - Channel system - Google Patents

Abstract

PURPOSE:To prevent the repeat of retrial and to reduce load by switching a current common interface transfer rate to a lower transfer rate at the time of generating overrun and then executing retrial at the low transfer rate. CONSTITUTION:When a generated overrun is detected by an overrun detecting circuit 4, transfer mode control circuits 5, 10 are informed of the detected result. The circuits 5, 10 read out the transfer rate information of transfer mode registers 7, 11 and form transfer rate information lower only by one step than the transfer rate held at the time of generating the overrun. The contents of the registers 7, 11 are written to the information of one-step lower transfer rate to reduce the transfer rate of the common interface 3. Then data transfer is retried. When the data transfer succeeds by the retrial, the lower transfer rate is returned to the original transfer mode, and if overrun is generated again, retrial based upon a furthermore lower transfer rate is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel system, and more particularly to a channel system capable of controlling a plurality of types of data transfer rates of a common interface.

[0002]

2. Description of the Related Art In a conventional channel system, a transfer rate of a common interface is determined by a data transfer rate (hereinafter referred to as a transfer rate) of a peripheral controller, and once set, it is not changed.

This transfer rate is, for example, 3, 4, 5,
There are multiple types such as 6, 9 megabytes / second, etc., there is a tendency for speeding up year by year, and the response format is also different.

The common interface control circuit of the channel controller is individually prepared for the transfer rate, and the common interface control circuit corresponding to the transfer rate is selected by switching the transfer mode. Therefore, the higher the transfer rate, the larger the amount of data that can be transferred in the same time unit. Further, in this case, when a firmware processing request such as a data chain and page crossing is generated, the input / output control device causes the address after the data chain,
Alternatively, since the address and the like after the page crossing must be calculated, the data transfer request from the channel control device cannot be accepted and waits until the address calculation is completed. Therefore, during that time, the transfer data is stored in the data buffer in the channel controller during the input transfer, and the read operation is continued during the output transfer.

[0005]

In this conventional channel system, the higher the transfer rate, the higher the speed at which the input data sent from the peripheral controller is stored in the data buffer in the channel controller at the time of input transfer. When the input / output control device, which is a higher-level device, cannot wait for the data transfer request, the input data exceeds the capacity of the data buffer, so-called overrun is likely to occur.

Also in the transfer of output data, the read speed of the output data sent from the data buffer to the peripheral control device is increased, and when the input / output control device is not accepted and waits, the output data in the data buffer becomes empty. Therefore, there is a high possibility that an overrun will occur that there is no data to be output.

When an overrun occurs, the data transfer that is currently being performed is returned to the beginning and a retry is made. However, if the previous environment is not improved, the overrun occurs again. Therefore, there is a drawback that unnecessary transfer is performed and the load is increased.

[0008]

SUMMARY OF THE INVENTION The present invention provides a channel comprising a common interface for performing data transfer with a peripheral control device of a host device, a channel control device connected via the common interface, and the peripheral control device. In the system, the channel control device temporarily stores data to be transferred, and the amount of data stored in the data buffer exceeds a storage capacity, or there is no data to be stored in the data buffer. An overrun detection circuit for detecting an overrun at which transfer is impossible, a first transfer mode register for determining a data transfer rate, and a first transfer mode register for detecting the overrun when the overrun detection circuit detects the overrun. A first transfer mode control circuit for switching to the data transfer rate determined by the transfer mode register; A second common interface control circuit for controlling the common interface at a predetermined transfer rate in accordance with a command from the transfer mode control circuit, and the peripheral control device determining a transfer rate of the data. A mode register, a second transfer mode control circuit that switches to the data transfer rate determined by the second transfer mode register when the overrun detection circuit detects the overrun, and the second transfer mode A second common interface control circuit for controlling the common interface to a predetermined transfer rate according to a command from the control circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the channel control device 1 and the peripheral control device 2 are connected via a common interface 3. A common interface control circuit 8 for controlling the common interface 3 and a data buffer 6 for temporarily storing transfer data are provided in the channel control device 3.
And an overrun detection circuit 4 for monitoring overrun
And a transfer mode control circuit 5 and a transfer mode register 7 for instructing transfer rate switching. Further, the peripheral controller 2 includes a common interface control circuit 9 for controlling the common interface 3, a transfer mode control circuit 10 and a transfer mode register 11.

Next, the operation of this embodiment will be described.

When transferring the input data, the transfer data sent from the peripheral controller 2 is once stored in the data buffer 6 in the channel controller 1 via the common interface 3. Since the peripheral controller 2 and the upper device have different data widths, the data is matched with the data width of the upper device and transferred. Further, also in the transfer of the output data, the output data sent from the host device is temporarily transferred to the data buffer 6
Is stored once, is adjusted to the data width of the peripheral control device 2, and is transferred via the common interface 3. The common interface 3 is controlled by the common interface control circuit 8 on the side of the channel control device 1 and the common interface control circuit 9 on the side of the peripheral control device 2 to transfer the transfer data. The control method of the common interface control circuits 8 and 9 differs depending on the transfer rate of the peripheral control device 2, and the control method is determined by the instruction of the transfer mode register 7 having the transfer rate information.

During input data transfer, if the input data in the data buffer 6 cannot be transferred to the host device due to the host device's convenience and the wait state continues for a long time, the peripheral controller 2 continues to transfer the input data, If the output data in the data buffer 6 is overrun or the output data cannot be transferred to the data buffer 6 for a long time due to the host device during the output data transfer, the output data in the data buffer 6 is output to the peripheral control device 2. Subsequently, an overrun occurs in which the transfer data in the data buffer 6 is lost, and when this is detected by the overrun detection circuit 4, it is reported to the transfer mode control circuits 5 and 10. The transfer mode control circuits 5 and 10 read the transfer rate information from the transfer mode registers 7 and 11 and create transfer rate information one step lower than the transfer rate at the time when the overrun occurred. Then, the contents of the transfer mode registers 7 and 11 are rewritten to transfer rate information that is one step lower, and the transfer rate of the common interface 3 is lowered. Then, the data transfer is retried.

If the data transfer is successful in the retry, the original transfer mode is restored, and if the overrun occurs again, the transfer rate is further reduced and the retry is performed.

[0015]

As described above, according to the present invention, when an overrun occurs, the transfer rate of the common interface is switched to a transfer rate lower than the current one and the retry is performed to prevent the retry from being repeated. This has the effect of reducing the load.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 channel control device 2 peripheral control device 3 common interface 4 overrun detection circuit 5, 10 transfer mode control circuit 6 data buffer 7, 11 transfer mode register 8, 9 common interface control circuit

Claims (1)

Claim: What is claimed is: 1. A channel system comprising a common interface for performing data transfer between a host device and a peripheral control device, a channel control device connected via the common interface, and the peripheral control device. There, the channel control device, the data buffer for temporarily storing the data to be transferred, the amount of data to be stored in the data buffer exceeds the storage capacity, or there is no data to be stored in the data buffer, the data transfer An overrun detection circuit that detects impossible overruns,
A first transfer mode register for determining a data transfer rate; and a first transfer for switching to the data transfer rate determined by the first transfer mode register when the overrun detection circuit detects the overrun. A mode control circuit; and a first common interface control circuit for controlling the common interface to a predetermined transfer speed according to an instruction from the first transfer mode control circuit, wherein the peripheral control device transfers the data. A second transfer mode register for determining a speed, and a second transfer mode control circuit for switching to the data transfer rate determined by the second transfer mode register when the overrun detection circuit detects the overrun. And controlling the common interface to a predetermined transfer rate by the instruction of the second transfer mode control circuit. And a second common interface control circuit for controlling the channel system.