JPH0519975A - Address information integrating method for hard disk emulator - Google Patents

Abstract

PURPOSE:To prevent the fall of speed as a hard disk emulator even in a situation that access arises frequently from a host computer. CONSTITUTION:Data to be recorded in a hard disk device 4 or a non-volatile memory to be used as a cache memory has information (address information) to show at which address of the optical disk device 5 of a main storage device each data is to be stored primarily. This address information is stored in a work memory 12. Besides such the address information is apt to increase in the situation that the access arises frequently from the host computer 1. However, by executing the connection processing of the address information shown in each item in this figure, such the increase of the address information can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hard disk emulator which is one of auxiliary storage devices for computers.

[0002]

2. Description of the Related Art An optical disk device is capable of exchanging disks, has no risk of crash due to a non-contact recording system, and has a long disk length, as compared with a hard disk device which is most often used as an auxiliary storage device for computers. It has many advantages such as long life expectancy and large storage capacity.

Therefore, in recent years, it has been attracting attention as an auxiliary storage device replacing the hard disk drive.

[0004]

However, the following problems still exist at the present time for the optical disc device to be widely used as an auxiliary storage device for computers.

The first problem is that the hard disk device has already been widely used as an auxiliary storage device for a computer, and therefore new hardware and software must be prepared in order to connect the optical disk device to the computer. That is.

The second problem is that the throughput of the optical disk device is lower than that of the hard disk device.
The first cause of low throughput of the optical disk device is
The second is that the seek time is long, the second is that the data error rate before error correction is bad, and the verify processing after writing is essential, and the third is that the probability of replacement processing is high due to the same error rate problem. To be

A third problem is that if the optical disk device is of the magneto-optical type, it cannot be overwritten and that a magnetization direction reversal time is required between the erase cycle and the write cycle.

For this reason, the optical disk device has a problem that the processing speed is remarkably reduced as compared with the hard disk device, particularly in the case of a write operation.

That is, the optical disk device has many advantages, but on the other hand, it also has many problems.

One of the inventors of the present application has proposed a technique relating to a hard disk emulator capable of solving such conventional problems in Japanese Patent Application No. 2-230807, which has not been published at the time of filing the present invention. There is.

In this Japanese Patent Application No. 2-230807, a hard disk device or a non-volatile memory used as a cache memory, a host computer, an optical disk device and a hard disk device or a non-volatile memory are provided together with an optical disk device which is a main bulk storage device. In the meantime, as an auxiliary storage device of a computer, which is composed of an emulation unit that operates in response to a request for recording or reproducing data from a host computer while using the hard disk device or non-volatile memory as a cache memory. We propose a valid hard disk emulator.

According to the technique proposed in Japanese Patent Application No. 2-230807, it is possible to eliminate the need for dedicated hardware and dedicated software when introducing the optical disc device and to supplement the low throughput of the optical disc device. It is possible to obtain excellent effects such as

Further, the inventors, including the inventor of the Japanese Patent Application No. 2-230807, will be described as follows.
We have found a theme to further improve the technology of the hard disk emulator proposed in 230807.

That is, when the host computer frequently accesses the optical disk, which serves as the main storage device, according to the latest data of the cache data recorded in the hard disk device used as the cache memory or the non-volatile memory. There is a risk that the process of updating the device data may not catch up.

When such an update process cannot catch up, the first problem is that it has not been transferred to the main storage device.
There is a risk that the cache data as recorded in the hard disk device or the non-volatile memory may become full.

The data recorded in the hard disk device or the non-volatile memory used as the cache memory has information as to which address of the optical disk device the respective data should be originally recorded. Hereinafter, such information is simply referred to as address information.

If a situation occurs in which access is frequently made from the host computer, the second problem is that such address information is accumulated, and the work memory recording such address information. The storage capacity of may become full.

In this way, if the hard disk device or the non-volatile memory used as the cache memory becomes full, or if the work memory for recording the address information becomes full, the hard disk device or the non-volatile memory. While the process of transferring the cache data of the above to the optical disk device progresses, the process of organizing the address information executed in association with the process progresses, and until such a full state is eliminated, It causes waiting for access.

If the host computer is accessed in such a full state, the time until the full state is canceled is added,
The access time from the host computer becomes long and the function as a hard disk emulator deteriorates.

The present invention has been made in view of the theme of further improving the technology of such a hard disk emulator. First, the above-mentioned Japanese Patent Application No. 2-23080.
As in the case of No. 7, the purpose is to eliminate the need for dedicated hardware and dedicated software when introducing the optical disc device, and to supplement the low throughput of the optical disc device.

In addition to the above object, the present invention provides a hard disk device or a non-volatile memory which is used as a cache memory without being transferred to the main bulk storage device even in a situation where access is frequently made from the host computer. The purpose is to prevent the function as a hard disk emulator from deteriorating due to the cache data that has been recorded on the disk being full or the address information in the work memory being full. .

[0022]

SUMMARY OF THE INVENTION The present invention is a cache for temporarily recording data accessed from a host computer and an optical disk device, which is a main storage device, by appropriately using a cache address in which no data is written. Using a hard disk device or a non-volatile memory having an area, emulates an interface specification conforming to a predetermined hard disk device specification, and at the time of the emulation, a plurality of data are written or written in a cache address table. When the respective cache data corresponding to the respective address information are written in the cache area, it is determined whether or not they can be integrated, and it is determined that they can be integrated. Has at least the corresponding multiple By integrating dress information is obtained by achieving the above object.

Further, the judgment as to whether or not the integration is possible is a judgment as to whether or not each address information is continuous in the state of being written in the cache area, and when it is judged that they are continuous. At least, the above object is achieved by connecting a plurality of corresponding address information.

Further, the judgment as to whether or not the integration is possible is a judgment as to whether or not the address information of a certain cache data includes the address information of the cache data recorded before that, and it is judged to include it. In this case, the above object is achieved by making the cache data valid and including the address information.

[0025]

By having an interface specification that conforms to the specifications of any hard disk device, new software or hardware is not required when installing the optical disk device, and it is recognized as a hard disk device by the connected host computer, By replacing, emulation as a large-capacity hard disk device is possible.

Further, according to the present invention, the problem of the optical disk device is reduced by using the hard disk device or the non-volatile memory as the cache memory during such emulation.

Hereinafter, a hard disk device or a non-volatile memory used as such a cache memory is
Also called a data cache device.

That is, when the recording data sent from the host computer is recorded in the hard disk device or the non-volatile memory while the host computer reproduces the already recorded data, the reproduction data is reproduced in the hard disk device or the non-volatile memory. Read from the optical memory or the optical disk device. When there is no access from the host computer, the recording data is transferred from the hard disk device or the non-volatile memory to the optical disk device, or a certain amount of data following the reproduction data area is transferred from the optical disk device to the hard disk. Transfer to device or non-volatile memory.

In this way, by having the emulation function of the hard disk device, it becomes unnecessary to install dedicated hardware and software when installing the optical disk device, and by providing a so-called cache memory and background processing, Make up for low throughput.

The operation of the present invention described above and the excellent effects thereof are described in Japanese Patent Application No. Hei 2 (1994) by one of the inventors of the present application.
It is also exhibited in -230807.

The present invention has the following actions and effects in addition to the above actions and effects.

That is, the present invention has been made paying attention to a comparatively exceptional situation that an access, which is a request for recording data or a request for reproducing data from the host computer, frequently occurs. .

When the host computer is frequently accessed, as described above,
The storage capacity of the hard disk device or non-volatile memory (data cache device) used as a cache memory is full, or the work memory for recording address information is full, and the function as a hard disk emulator deteriorates. There is a risk that

In order to deal with such a relatively exceptional situation, the present invention is arranged to organize the address information recorded in the work memory.

Further, according to the present invention, when organizing the address information recorded in the work memory, in some cases,
It is also possible to reduce the data in the cache area of the data cache device.

Therefore, according to the present invention, it is possible to prevent the address information in the work memory from being filled up even if the host computer frequently accesses the work memory. In some cases, it is possible to prevent the recording capacity of the data cache device from becoming full.

The cache area and address information which is the object of the present invention will be described below.

As for the cache area to which the present invention is applied, one of the inventors of the present invention can apply the above-mentioned Japanese Patent Application No.
When proposing a hard disk emulator technology in 07, it is almost the same as that assumed as the cache area in the hard disk device used in the embodiment of this Japanese Patent Application No. 2-230807.

The cache area will be described in more detail below.

This cache area is for temporarily recording data temporarily accessed from the host computer at an address on the hard disk device where no data is written.

Therefore, in order to use such a cache area, it is necessary to record address information in the work memory or the like.

The above-mentioned Japanese Patent Application No. 2-230807 and the hard disk emulator of the present invention operate in accordance with the interface specifications conforming to arbitrary hard disk device specifications.

That is, access such as recording and reading to the hard disk emulator of the host computer is performed according to the specifications of the emulated hard disk device.

When accessing the host computer, the addressing of the accessed data to the hard disk emulator also conforms to the specifications of the emulated hard disk device.

Hereinafter, the address designated by such a host computer will be referred to as an emulation address.

In such an emulation address, regardless of the track number, the cylinder number, the sector number, etc., an address is designated in units of a block of a predetermined number of bytes, that is, an address is specified according to the serial number of all blocks of a predetermined number of bytes. There are two types, one is to specify and one is to specify a general hard disk device by combining various address values such as track number, cylinder number, sector number, etc., but this is an emulated hard disk device specification. However, the present invention is not limited thereto.

Also in the optical disk device which is the main storage device, a predetermined addressing method is used regardless of whether the physical format of the information recording medium is spiral or a plurality of concentric tracks. have.

Hereinafter, the address designated when the data is accessed to the optical disk device will be referred to as an optical disk address.

Since the emulation address and the optical disk address are in a one-to-one correspondence, hereinafter,
For convenience, the address of the optical disk device is also the emulation address.

Further, even in the hard disk drive, which is a data cache device, and the non-volatile memory, the data access to the data cache device is performed by addressing in a predetermined form.

Hereinafter, the address designated when accessing the data of such a data cache device is called a cache address.

In the transfer of data between the cache area of the data cache device and the host computer and the transfer of data between the cache area and the optical disk device, according to the address information recorded in the work memory or the like, Correspondence between the cache address and the emulation address is made.

Therefore, such address information used when accessing the data cache device becomes a correspondence table of cache addresses and emulation addresses, that is, a cache address table.

The address information integration method of the hard disk emulator of the present invention will be described below.

According to the present invention, whether or not each cache data corresponding to a plurality of address information can be integrated in the state of being written in the cache area is determined by comparing these respective address information with each other. Becomes

The present invention limits specific conditions for determining whether or not integration is possible by comparing a plurality of such address information with each other, and specific processing contents corresponding thereto. is not.

The judgment of whether or not the present invention can be integrated and the predetermined processing according to this judgment are combined,
Hereinafter, this is referred to as address information integration processing.

A specific example of the address information integration process of the present invention will be described below.

FIG. 1 is a diagram showing an address information concatenation process, which is an example of the address information integration process of the present invention.

In the diagram of FIG. 1, the numbers No given for explanation, the conditions under which the processing of the corresponding item is performed, and the processing contents of the corresponding item are shown in order from the left.

In the concatenation process of the address information shown in FIG. 1, adjacent cache data corresponding to different address information is written in a cache area of a data cache device which is a hard disk device or a non-volatile memory. In the case where the address information continues, the different address information is integrated (connected).

First, in the case of number 1 in FIG. 1, it is determined from the address information of the cache address table recorded in the work memory that the cache data adjacent in the cache area is simply continuous in the state of being written in the cache area. In this case, a plurality of pieces of address information corresponding to these adjacent cache data are put together.

That is, each cache address of the address information corresponding to each cache data adjacent in the cache area is continuous due to the adjacent in this cache area. Therefore, when the cache data adjacent in such a cache area is also continuous in terms of emulation addresses, the address information of these cache data can be collected into one.

In addition, in the case of number 2 in FIG. 1, when writing new cache data in the cache area,
Further, when it is determined that the cache data that becomes adjacent in the cache area due to the writing becomes continuous while the emulation address partially overlaps in the state of being written in the cache area, this cache data By writing the write so as to overwrite the overlapped portion, the emulation addresses are simply continuous in the state of being written in the cache area, as in the case of the above-mentioned number 1.

Therefore, also in the case of the number 2 in FIG. 1, the address information of the adjacent cache data can be gathered into one, as in the case of the number 1 described above.

Therefore, after the writing of the current cache data is completed, the previous address information is updated so that the previous address information includes the current address information.

According to the connection processing of the address information of No. 2 in FIG. 1, the storage capacity of the cache data recorded in the cache area can be reduced. That is, it is possible to reduce the storage capacity of the overlapping portion between the previous cache data and the current cache data.
Also, the total number of address information in the work memory can be reduced.

FIG. 2 is a diagram showing an address information inclusion process, which is an example of the address information integration process.

In the diagram shown in FIG. 2 as well, similar to the diagram of FIG. 1 described above, from the left, the number No for explaining, the condition for processing the corresponding item, and the corresponding item Processing details are shown.

In the number 1 in FIG. 2, the address information recorded in the work memory corresponding to the cache data recorded in the cache area of the data cache device which is the hard disk device or the non-volatile memory is the cache data. The condition is whether or not the address information of other cache data recorded before the recording of is included.

When the emulation address of the address information of a certain cache data includes the emulation address of the cache data recorded before the recording of the cache data, only the included (newer) cache data is included. Then, the corresponding emulation address of the optical disk device which is the main valve storage device can be updated to the latest data.

Therefore, when the condition of No. 1 is satisfied,
The included (newer) cache data is validated. Further, when the condition of No. 1 is satisfied, the included (older) cache data becomes unnecessary, so that the address information corresponding to the unnecessary cache data becomes unnecessary. Therefore, this unnecessary address information is discarded, so that a plurality of address information
It is put together in one.

[0073]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 3 shows the basic configuration of the embodiment of the present invention.

The host computer 1 records data in the hard disk emulator 2 via the interface bus 6 and reproduces the data from the hard disk emulator 2.

The hard disk emulator 2 is composed of an emulation unit 3, a hard disk device 4, and an optical disk device 5, and these units and devices 3, 4, and 5 are connected by an interface bus 7.

The emulation unit 3 is a unit that controls the hard disk emulator 2 as a whole, and controls emulation as a hard disk, data transfer with the hard disk device 4 and the optical disk device 5, and data transfer with the host computer 1.

The hard disk device 4 is used as a nonvolatile data cache device and has a smaller capacity than the target hard disk device to be emulated.

The optical disc device 5 is capable of exchanging a disc which is a recording medium, and employs a rewritable type for emulating a hard disc.

FIG. 4 shows a data flow during recording in the above embodiment.

The data sent from the host computer 1 is recorded in the hard disk device 4 via the emulation unit 3. When the recording command sequence from the host computer 1 is completed, the data recorded in the hard disk device 4 is transferred to the optical disk device 5. This transfer is performed while the hard disk emulator 2 is not being activated by the host computer 1, that is, as a background process of the hard disk emulator 2. Also, during this background processing,
When the hard disk emulator 2 is started up from the host computer 1, the background processing is immediately stopped, the started command sequence is executed,
After finishing this, the remaining background processing is restarted and executed.

FIG. 5 shows a data flow during reproduction in the above embodiment.

If the data specified by the host computer 1 is in the hard disk device 4, the data is transferred from the hard disk device 4 to the emulation unit 3
Is sent to the host computer 1 via.

In the background process during reproduction, when the reproduction data is sequential file data which will be described later with reference to FIGS. 7 and 8, the data in the area following the reproduction data is transferred from the optical disk device 5 to the hard disk device 4. To be done. That is, prefetching is performed.

In general, access from the host computer 1 to the auxiliary storage device is often made sequentially, and there is a high possibility that the data following the data will be accessed after the access to the certain data. The prefetch performed in the background process becomes more effective.

If the data designated by the host computer 1 does not exist in the hard disk device 4, it is transferred from the optical disk device 5 via the emulation unit 3.

Since the hard disk device 4 is a randomly accessible memory, the seek time is often not negligible in consideration of the performance of the entire system.

Generally, the seek time of the present hard disk drive is about 20 to 50 ms including the rotation waiting time, while the time required for recording per sector is often 1 ms or less. Considering the case where there are many random accesses, the actual recording is only about several ms, but since the seek requires about several tens of ms, the time required from the viewpoint of the host computer 1 is (several tens ms) + (several ms). Become.

On the other hand, in the hard disk emulator 2 of the above embodiment, since the data is sequentially stored in the hard disk device 4 used as the cache memory regardless of the address designated by the host computer 1, no seek occurs and the host computer The time required from the computer 1 is only a few ms.

Next, a concrete circuit configuration of the emulation unit 3 is shown in FIG.

The emulation unit 3 has an interface with the host computer 1 and an interface with the optical disk device 5 and the hard disk device 4. Inside the emulation unit 3, the host computer side interface control circuit 6 and the memory device side interface control circuit are provided. 7 controls each interface protocol.

The data transfer control circuit 8 is provided between the host computer 1 and the memory device and the optical disk device 5.
And data transfer between the hard disk device 4 and the hard disk device 4. The data buffer 9 operates as a buffer memory when transferring these data.

The overall control of the emulation unit 3 is controlled by the CPU (Central Processing Unit) 10
And a program ROM (program read only memory) 11 and a work RAM (work random access memory) 12.

The work RAM 12 is used not only as a general work area of the CPU 10 but also stores address information of data on the hard disk device 4.

As will be described later with reference to FIGS. 9 and 10, this address information is information indicating the correspondence between the cache address (hard disk address) and the emulation address (same as the optical disk address).
Normally, it is generated every time new data is recorded in the cache area.

When using the cache area,
Based on this address information, the CPU 10 transfers data between the host computer and the hard disk device 4, and performs background processing between the optical disk device 5 and the hard disk device 4.

Since the background processing is performed independently of the host computer 1, the memory power backup circuit 13 for the work RAM 12 prevents the power from being turned off and the address information being lost before the background processing is completed. To provide.

Reference numeral 14 in the drawing denotes an interface bus with the host computer 1, and 15 shows a memory device, that is, an interface bus with the optical disk device 5 and the hard disk device 4. Each block in the emulation unit 3 is connected by a data bus 16 and an address bus 17. Host computer 1
Data between the optical disk device 5 and the hard disk device 4 is transferred via the data bus 16 by the data transfer control signal 18.

This data transfer is generally controlled via the data transfer control signal 18 such as a transfer request signal or a response signal generated by the data transfer control circuit 8 because the transfer speed becomes slower if it is performed via the CPU 10. Code 19
Is from the memory power backup circuit 13 to the work RAM 1
2 shows the backup power supply to be supplied.

The operation of this embodiment will be described below.

In this embodiment, data of continuous emulation addresses including emulation addresses that are frequently accessed are temporarily stored together with general cache areas to which the present invention is applied (hereinafter referred to as normal cache areas). It has a fixed cache area for recording.

The correspondence between the individual addresses of the cache address in the fixed cache area and the consecutive emulation addresses assigned to it is one to one.
It is a correspondence of.

In accessing such a fixed cache area, the address information required in accessing the above-mentioned normal cache area is not required.

Further, even if the host computer frequently records to the emulation address assigned to the fixed cache area, the recording of the data to the corresponding cache address of the fixed cache area is performed only the designated number of times. is there.

That is, by using the fixed cache area in this way, when the normal cache area is used, the data that has not been transferred to the main storage device and remains recorded in the normal cache area becomes full. There is no fear that the address information in the work memory for using the normal cache area will be full.

As described above, in this embodiment, by providing the fixed cache area, the data in the data cache device may become full even in the situation where the host computer frequently accesses the data, and the work memory may not be full. It is possible to reduce the risk that the address information of will become full.

FIG. 7 is a map of the total storage capacity area of the optical disk device 5 of the above embodiment.

In FIG. 7, reference numerals A10b and A12 are used.
b and A14b are a fixed cache area allocation area, a normal cache area allocation area, and a prefetch area allocation area, respectively.

Fixed cache area allocation area A
10b, a normal cache area allocation area A12b, and a prefetch area allocation area A14b are allocated corresponding to a fixed cache area A10a, a normal cache area A12a, and a prefetch area A14a, which will be described later, respectively.

As shown in FIG. 7, the total storage capacity of the optical disk device 5 used in this embodiment is 300M.
It is B (megabytes).

Data relating to the OS management information is recorded in the first 4 MB of the total storage capacity area in the optical disk device 5.

In the optical disk device 5 of this embodiment, the recording medium on which data is actually recorded can be replaced. Accordingly, the OS management information data D3 of 4 MB at the head of the total storage capacity area is mainly information relating to file management of data recorded on the recording medium attached to the optical disk device 5.

The OS management information data D3 is data that is frequently accessed by the host computer.

Therefore, as indicated by the symbol A10b in FIG. 7, the OS management information data D3 is a fixed cache area allocation area.

Further, in FIG. 7, the area designated by reference numeral A12b is a normal cache area allocation area.

The area of 4 MB to which the code A14b is assigned is a prefetch area allocation area.
In the prefetch area allocation area A14b, sequential file data D2 in which access is performed sequentially in the order of addresses is recorded.

The reference numeral D1 in the normal cache area allocation area A12b in FIG. 7 is hot data, and as will be described later with reference to FIG.
The data is expanded in the normal cache area A12a.

FIG. 8 is a map of all cache areas of the hard disk device 4 of the above embodiment.

In FIG. 8, reference numerals A10a and A12 are used.
a and A14a are a fixed cache area, a normal cache area, and a prefetch area, respectively. or,
Reference numerals D1, D2, D3 in FIG. 8 are the same as those of the same reference numerals in FIG.

As shown in FIG. 8, the total storage capacity of the hard disk device 4 is 40 MB.

The total storage capacity of the hard disk device 4 is a cache area composed of a normal cache area A12a, a prefetch area A14a and a fixed cache area A10a.

In the normal cache area A12a, 32 MB is allocated from the head of all the cache areas.

Incidentally, this normal cache area A12a
The data recorded in 1 is hereinafter referred to as hot data D1.

The prefetch area A14a is 4M following the 32MB normal cache area A12a.
This is area B.

At the time of access from the host computer,
The data to be accessed is the code A14b in FIG. 7 described above.
In the case of the sequential file data D2 recorded in the prefetch area allocation area indicated by, the prefetch area indicated by reference numeral A14a in FIG. 8 is used as the cache area.

At the time of access for reading the sequential file data D2 from the host computer, prefetching by the background processing described above with reference to FIG. 5 is performed.

The fixed cache area A10a of 4 MB, which is an area following the pre-fetch area A14a of 4 MB of FIG. 8, corresponds to the OS management information data D3 recorded in the fixed cache area allocation area A10b of FIG. Used for data cache.

The fixed cache area A10a of the hard disk device 4 has a storage capacity of the fixed cache area allocation area A located at the head of the optical disk device 5 described above.
It is the same as the storage capacity of 4 MB of 10b.

In the data cache using the fixed cache area A10a of the hard disk device 4, it is possible to perform the processing promptly without using the address information.

9 to 12 are diagrams showing the cache address table in which the address information of this embodiment is recorded.

The cache address tables shown in FIGS. 9 to 12 are numbers No, a flag, a cache address (hard disk address) consisting of a start address and an end address, and an emulation consisting of a start address and an end address. Address (which is the same as the optical disc address).

9 to 12, the number No.
Is a record of each cache address table, that is, a serial number of individual address information.

Further, the larger the value of this number No, the newer the data.

That is, when specific address information is invalidated by performing address information integration processing as described later, new address information is not written in the invalidated portion, First, in order to fill in this invalid part, the subsequent address information is numbered N
The value of o shifts to a smaller value, and after that, new address information is written at the end.

In the diagrams showing the cache address tables of FIGS. 9 to 12, "flag" is a flag indicating whether the corresponding address information is valid or invalid.

That is, when this flag is "1", the value of the cache address and the value of the emulation address of the corresponding address information are valid. The valid address information also indicates the correspondence between the cache address and the emulation address of the cache data in the corresponding cache area.

On the other hand, when this flag is "0", the address information corresponding to this flag, that is, the cache address and the emulation address are invalid. That is, when this flag is "0", this is ignored regardless of the value of the corresponding address information.

The cache address tables shown in FIGS. 9 to 12 are used when the normal cache area A12a on the hard disk 4 is accessed according to the address specification from the host computer, that is, the address specification by the emulation address. It is used when obtaining the cache address (hard disk address).

Alternatively, this cache address table is used for the hard disk address and the optical disk at the time of data transfer between the normal cache area A12a of the hard disk 4 and the normal cache area allocation area A12b of the optical disk device 5 which is performed in the background processing. It is also used when finding the correspondence with an address.

In this embodiment, the emulation address and the optical disc address correspond to each other on a one-to-one basis and can be regarded as the same.

The address information integration method in the hard disk emulator of this embodiment will be described below with reference to FIGS. 9 to 12.

In the address information integration method of the hard disk emulator of the present embodiment, each item of the address information concatenation process described above with reference to FIG. 1 and each address information inclusion process described above with reference to FIG. Items are being processed.

First, in FIG. 9 and FIG. 10, the processing of the item of number 1 of the concatenation processing of the address information of FIG. 1 is performed.

In FIG. 9, the cache address is 00
The emulation addresses of the cache data indicated by the address information of 0000 to 00001E and the cache data indicated by the address information of 00001F to 00003E are 01F001 to 01F01F or 01F020 to 01F03F, respectively. ing.

That is, the cache data corresponding to the address information of No. 1 and the cache data corresponding to the address information of No. 2 are adjacent to each other while being written in the cache area in the hard disk device,
Moreover, the emulation addresses are consecutive.

Similarly, the respective cache data indicated by the address information of the numbers 4 to 7 in FIG. 9 are continuous in the state of being written in the cache area of the hard disk device.

That is, the respective cache data corresponding to the address information of these numbers 3 to 7 are written in the hard disk cache area in the order of numbers, and the emulation addresses of the cache data of these numbers 3 to 7 are , Are consecutive in this numerical order.

Therefore, the address information of number 1 and the address information of number 2 in FIG. 9 can be integrated according to the processing of the item of number 1 in the concatenation processing of address information in FIG. Similarly, a total of five pieces of address information from No. 3 to No. 7 can be integrated into one piece of address information.

In the cache address table of FIG. 10, a value for which the concatenation process of the address information of the cache address table of FIG. 9 is completed is written.

That is, the address information of number 1 in FIG. 10 is address information obtained by integrating (connecting) the address information of number 1 and the address information of number 2 in FIG. Further, the address information of No. 2 in FIG. 10 is the address information obtained by integrating (connecting) a total of five pieces of address information from No. 3 to No. 7 in FIG.

The values of the cache address and the emulation address written in the address information of numbers 3 to 7 in FIG. 10 are the caches of the address information of numbers 3 to 7 in FIG. 9, respectively. The value written in the address is the same as the value written in the emulation address, but since the flag is "0", these values are invalid.

In this way, by performing the integration (concatenation) processing of the address information of the cache address table of FIG. 9, it is possible to reduce the total of 7 pieces of address information to the total of 2 pieces of address information.

In the diagram showing the cache address table in which the address information shown in FIG. 11 is recorded, the cache data corresponding to the address information of the number 3, that is, the cache address 00002 of the cache area.
The cache data written from F to 00007E is the emulation addresses 01F000 to 01F.
The data is data to be written in 04F and is newer than the cache data corresponding to the address information of number 1 and the cache data corresponding to the address information of number 2.

Therefore, the emulation address of the cache data corresponding to the address information of this number 3 is
The emulation addresses of the cache data corresponding to the address information of No. 1 and the cache data corresponding to the address information of No. 2 recorded before that are included. Therefore, a total of three pieces of address information from No. 1 to No. 3 in FIG. 11 can be integrated (included) according to the processing of the item No. 1 of the inclusion processing of address information in FIG. 2 described above.

The cache data corresponding to the address information of No. 6 in FIG. 11, that is, the cache data having emulation addresses from 000020 to 00005F is recorded before the recording of the cache data corresponding to the address information of No. 6. The emulation addresses of the cache data corresponding to the address information of No. 4 and the cache data corresponding to the address information of No. 5 are included.

Therefore, a total of three pieces of address information from No. 4 to No. 6 can be integrated (included) according to the processing of the item of No. 1 of the inclusion processing of address information in FIG.

In the state shown in FIG. 11,
Emulation address is 000090 to 0000
When a new data of AF is to be written in the normal cache area, this data is written in the cache area following the cache address of the address information of No. 7 in FIG.

The data newly written in the cache area in this way, that is, the cache data, is the cache data corresponding to the address information of number 7 in FIG.
It becomes adjacent in the state of being written in the cache area.

The cache data newly written in the cache area has emulation addresses of 00900 to 0000AF.
Partly overlaps with. That is, these cache data are
Emulation addresses 000090 to 000009
Overlap in F.

Therefore, when writing the cache data to such a new cache area, it is judged that the condition of the item of No. 2 of the concatenation processing of the address information in FIG. 1 is satisfied.

Therefore, the newly written cache data is the emulation address 0000 of the cache data indicated by the address information No. 7 in FIG.
The writing is performed while overwriting the portion corresponding to the overlapping portion of 90 to 000009F.

That is, the newly written cache data has cache addresses 0000C5 to 000.
It is written by 0E4.

Further, the address information of number 7 in FIG. 11 and the address information of the newly written cache data can be integrated (connected).

The cache address table shown in FIG. 12 shows the result of integrating the address information of the cache address table of FIG. 11 described above.

The address information of No. 1 in FIG. 12 is address information in which a total of three pieces of address information of No. 1 to No. 3 in FIG. 11 are integrated. That is, the address information of No. 1 in FIG. 12 is address information in which the address information of No. 1 and the address information of No. 2 in FIG. 11 are included in the address information of No. 3 in FIG. .

Further, the address information of No. 2 in FIG. 12 is the address information in which a total of three pieces of address information of No. 4 to No. 6 in FIG. 11 are integrated. That is,
The address information of No. 2 in FIG. 12 is the address information in which the address information of No. 4 and the address information of No. 5 in FIG. 11 are included in the address information of No. 6 in FIG. .

The address information of No. 3 in FIG. 12 is integrated (concatenated) with the address information of No. 7 in FIG. 11 and the address information of newly written cache data.
Address information.

As shown in FIG. 12, in this embodiment, a total of 7 + 1 address information can be reduced to a total of three pieces of address information.

As described above, according to this embodiment, the address information in the work memory can be reduced,
Further, in some cases, it is possible to obtain an excellent effect that the storage capacity of newly written cache data can be reduced.

As described above, this embodiment is
The optical disk device 5 which is the main storage device and the hard disk device 4 used as a cache area during emulation are used to comply with the emulated hard disk device specifications for recording and reading access from the host computer. is there.

In the present embodiment, a hard disk device is used as a data cache device, and a hard disk emulator that compensates for the disadvantages of the optical disk device is constructed.

[0172]

As described above, according to the present invention, the advantages of the optical disk device are the exchangeability of the disk, the long life, the large capacity, and the crash-free property. In addition, the cache memory and the background processing are provided. By providing the above, it is possible to compensate for the low throughput of the optical disk device, and when recording data with high random accessibility, it can be expected to exceed the throughput of the hard disk device that is the target for emulation.

Further, according to the present invention, by having the emulation function of the hard disk device, it is possible to connect to the host computer in place of the hard disk device without requiring the hardware and software peculiar to the optical disk device. The effect is also obtained.

Further, according to the present invention, in addition to the above effects, even in a situation where access is frequently made from the host computer, it is not transferred to the main bulk storage device and is used as a cache memory or a non-volatile memory device. It is possible to prevent the cache data that has been recorded in the memory from becoming full, and the address information in the work memory from becoming full and preventing the function of the hard disk emulator from deteriorating. The effect can also be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a concatenation process of address information, which is an example of a method of integrating address information according to the present invention.

FIG. 2 is a diagram showing an address information inclusion process which is an example of an address information integration method according to the present invention.

FIG. 3 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 4 is a block diagram showing a data flow during recording in the above embodiment.

FIG. 5 is a block diagram showing a data flow during reproduction in the same manner.

FIG. 6 is a block diagram showing a specific circuit configuration of an emulation unit which is a constituent element in the above embodiment.

FIG. 7 is a map diagram of a total storage capacity area of the optical disk device of the above embodiment.

FIG. 8 is a map diagram of all cache areas of the hard disk device of the embodiment.

FIG. 9 is a diagram showing a cache address table in which address information of this embodiment is recorded.

FIG. 10 is a diagram showing a cache address table in which address information in which the address information of FIG. 9 is integrated is recorded.

FIG. 11 is a diagram showing a cache address table in which address information of this embodiment is recorded.

FIG. 12 is a diagram showing a cache address table in which address information in which the address information of FIG. 11 is integrated is recorded.

[Explanation of symbols]

1 ... host computer, 2 ... Hard disk emulator, 3 ... Emulation unit, 4 ... Hard disk device, 5 ... Optical disk device, 6 ... Host computer side interface control circuit, 7 ... Interface control circuit for memory device side, 8 ... Data transfer control circuit, 9 ... Data buffer, 10 ... CPU, 11 ... Program ROM, 12 ... Work RAM, 13 ... Memory power backup circuit, 14 ... Interface bus, 15 ... Memory device (interface bus), 16 ... Data bus, 17 ... Address bus, 18 ... Data transfer control signal, 19 ... Backup power supply, A4 ... Data cache device all cache areas, A5 ... Total storage capacity area of optical disk device, A10a ... Fixed cash area, A12a ... Normal cash area, A14a ... Prefetch area, A10b ... fixed cache area allocation area, A12b ... Normal cache area allocation area, A14b ... Prefetch area allocation area, D1 ... hot data, D2 ... Sequential file data, D3 ... OS management information data.

Claims (3)

[Claims] 1. An optical disk device which is a main storage device,
Conforms to specified hard disk device specifications by using a hard disk device or non-volatile memory that has a cache area for temporarily recording the data accessed from the host computer, using a cache address where no data is written. In addition to emulating the interface specifications described above, a plurality of address information written in the cache address table at the time of the emulation, or a plurality of written address information are compared with each other, respective cache data corresponding to the respective address information are obtained. In the state of being written in the cache area, it is determined whether or not integration is possible, and if it is determined that integration is possible, at least a plurality of corresponding address information is integrated, address Broadcast integration method. 2. The method according to claim 1, wherein the judgment as to whether or not the integration is possible is a judgment as to whether or not each address information is continuously written in the cache area, and is determined to be continuous. A method for consolidating address information of a hard disk emulator, characterized in that at least a plurality of corresponding address information are concatenated. 3. The judgment according to claim 1, wherein the judgment as to whether or not the integration is possible is a judgment as to whether or not the address information of a certain cache data includes the address information of the cache data recorded before that. A method for integrating address information in a hard disk emulator, characterized in that, when it is determined to include the address information, the cache data is validated to include the address information.