JPH05199118A - A/d converter and d/a converter - Google Patents

Abstract

PURPOSE:To improve the conversion accuracy by deviating a count time of a high-order counter in a constant DC input state so as to detect a difference of conversion outputs and controlling a ratio of high-order and low-order reference currents. CONSTITUTION:The A/D converter of the cascade connection integration system is provided with a high-order counter 28 and a low-order counter 30 whose count state is revised by outputs of comparators 23,25 comparing an output of an integration device 11 and a threshold voltage, and also with current sources 17,19 supplying a high-order reference current IH corresponding to the count of the high-order counter 28 and a low-order reference current I, corresponding to the count of the low-order counter 30 to the integration device 11. Then a control means 26 sets a constant DC input state in the adjustment mode to deviate forcibly the count time of the high-order counter 28 thereby detecting a difference of the A/D conversion outputs. Then the ratio of the high-order reference current IH and the low-order reference current IL outputted from the current sources 17, 19 is controlled variably to adjust automatically the ratio of the IH, IL supplied to the integration device 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for converting an analog signal into a digital signal and a D / A converter for converting a digital signal into an analog signal, and more particularly to a cascade integration A / D conversion. And a D / A converter provided with a cascade integration A / D converter.

[0002]

2. Description of the Related Art Conventionally, as an A / D converter for converting an analog signal into a digital signal, for example, JP-A-61-161
A cascade integration type A / D converter disclosed in, for example, Japanese Patent No. 163723 is known.

This cascade integration A / D converter has an output of the integrator 60 and a threshold value V _TH1 , as shown in FIG.
The upper counter 76 and the lower counter 77, the count states of which are changed by the outputs of the comparators 71 and 72 for comparing V _TH2 , the upper reference current I ₁ corresponding to the count value of the upper counter 75, and the lower counter. It is provided with reference current sources 68 and 70 for supplying a lower-order reference current I ₂ corresponding to the count value to the integrator 60.

In the A / D converter shown in FIG. 4, an analog signal to be digitally converted is input to the integrator 60 from an input terminal 61.

The integrator 60 includes an inverting amplifier 64 to which the analog signal is supplied to an input terminal via a series connection circuit of a resistor 62 and a sample hold switch 63. The inverting amplifier 64 has an input terminal and an output terminal. And are connected via an integrating capacitor 65, and
02 and the sample hold switch 63 are connected to the output terminal of the inverting amplifier 64 via the resistor 66.

The reference current sources 68 and 70 are connected to the input terminals of the inverting amplifier 64 by the switch 6 respectively.
It is connected via 7,69. Here, the reference current I ₁ flowing by the reference current source 68 and the reference current source 7
The ratio of the reference current I ₂ flowing by 0 is generally 2 ⁿ
Alternatively, it is set to 2 ⁿ -1 (n is an integer), for example, I ₁
/ I ₂ = 2 ⁸ −1 = 255.

Further, the output terminal of the inverting amplifier 64 is connected to one input terminal of each of the comparators 71 and 72. A first threshold value V _TH1 is applied to the other input terminal of the comparator 71, and a second threshold value V _TH2 is applied to the other input terminal of the comparator 72. The respective comparison outputs of these comparators 71 and 72 are supplied to the control circuit 74.

The control circuit 74 is supplied with a master clock from a clock terminal 78, and the comparator 71,
Based on each comparison output of 72, the switches 67, 69
The open / close control is performed, and the clocks supplied to the upper counter 76 and the lower counter 77 are controlled.

The lower counter 77 is an 8-bit binary counter, counts the clock supplied from the control circuit 74, and outputs the count output from the output register 80.
And the carry output thereof is supplied to the OR gate 7.
It is supplied to the clock input terminal of the higher-order counter 76 via 5. The upper counter 76 is an 8-bit binary counter, counts the clock supplied from the control circuit 74 and the carry output of the lower counter 77, and supplies the count output to the output register 80. .. Further, the output register 80 has a terminal 8
The sample clock is supplied from 1.

Next, the cascade integration method A having the above-mentioned configuration
The operation of the / D converter will be described with reference to FIG.

In the integrator 60, time t ₂₁ shown in FIG.
By closing the sample-hold switch 63 for the time T ₂₁ of up to t ₂₂ , the input analog signal voltage V
_IN is sampled and stored in the integration capacitor 65, and at time t ₂₂ , the sample hold switch 63 is
Is opened, the sampled voltage is held.

[0012] Next, the control operation of the control circuit 74, together with the switches 67 and 69 is closed at time t _23, the counting operation of the master clock by the upper counter 76 is started. When the switches 67 and 69 are closed, the sum current I ₁ + I ₂ of the reference currents I ₁ and I _{2 from} the reference power sources 68 and 70 is passed to the integrator 60. Then, the time T until the time t ₂₄ when the integrated output of the integrator 60 reaches the first threshold value V _{TH1.
During 22} , the upper counter 76 performs the counting operation.

Further, by the control operation of the control circuit 74, only the switch 69 is closed and the master clock counting operation by the lower counter 77 is started from the time t ₂₄ . When the switch 69 is closed, the reference current I _{2 from the} reference power source 70 is supplied to the integrator 60. The time t at which the integrated output of the integrator 60 reaches the second threshold value V _TH2.
During the time T ₂₃ up to ₂₅ , the master clock is counted by the lower counter 77.

[0014] Here, I ₁ to the respective reference currents I _1, I ₂
/ I ₂ = 255 = 2 ⁸ −1, that is, (I ₁ + I ₂ ) / I
Due to the relationship of ₂ = 2 ⁸ , the one count of the upper counter 76 is weighted 2 ⁸ times the one count of the lower counter 77.

The count value of the master clock by the upper counter 76 during the time T ₂₂ is the upper bit, and the count value of the master clock by the lower counter 77 during the time T ₂₃ is the lower bit. The 16-bit digital value is output as a digital value output corresponding to the input analog signal voltage V _IN to the output register 80.
Is output from.

[0016]

By the way, in the cascade integration A / D converter having the above-described structure, the ratio I of the reference current I _{1 from the} reference power source 68 to the reference current I _{2 from the} reference power source 70 is I. _{Since 1} / I ₂ directly affects the accuracy of D / A conversion, it is necessary to adjust the ratio I ₁ / I ₂ with extremely high accuracy. In a MOS IC having such an A / D converter integrated into a circuit, the ratio I ₁ / I ₂ must be adjusted by time-consuming trimming. Moreover, it is extremely difficult to compensate the accuracy of the ratio I ₁ / I ₂ even if trimming is performed, because it is affected by variations in power supply voltage settings.

Also, in the D / A converter configured to perform the D / A conversion operation by using the reference current sources 68 and 70 and the integrator 60 in the cascade integration type A / D converter as described above, In order to ensure conversion accuracy, the ratio I ₁ /
The accuracy of I ₂ becomes a problem.

Further, in the cascade integration type A / D converter having the above-mentioned configuration, even in the non-input state, integration is performed from the midpoint voltage to the second threshold value V _TH2 which is above the signal amplitude range. Therefore, the integrated current, that is, the variation in absolute value of each of the reference currents I ₁ and I ₂ described above, the integration capacitor 65
The analog midpoint is not converted as the digital midpoint due to variations in the capacitance, variations in the potential difference between the midpoint voltage and the threshold value V _TH2 due to variations in the resistance and transistors in the IC, etc. It has an offset of about several percent.

A level meter or the like which digitizes a voice input by such an A / D converter and lights up purely digitally by the absolute value of the digital output seems to have a voice input even though there is no input state. However, there is a problem in that a significant error occurs. Further, in a digital recording device or the like, there is a problem that a DC level difference is generated between reproduction muting in a recorded portion and a non-recorded portion, and click noise is generated at a starting point and a releasing point of the reproducing muting.

Therefore, in view of the problems in the conventional cascade integration type A / D converter and D / A converter as described above, the present invention is a cascade integration type A / D converter and D / A converter. In order to obtain high conversion accuracy without requiring time-consuming trimming adjustment of the reference current ratio, an A / D converter equipped with an automatic adjustment function of the reference current ratio And a D / A converter. Furthermore, the present invention is based on A of the cascade integration method.
It is an object of the present invention to provide an A / D converter having an automatic offset adjusting function for the purpose of eliminating a conversion error due to an offset in the / D converter and obtaining a high conversion accuracy.

[0021]

In order to solve the above problems, the present invention provides a high-order counter and a low-order counter whose count state is changed by the output of a comparator that compares the output of an integrator with a threshold value. A cascade integration type A / D converter equipped with a current source for supplying an upper reference current corresponding to the count value of the upper counter and a lower reference current corresponding to the count value of the lower counter to the integrator. Sometimes
With a constant DC input state, the counting time of the upper counter is forcibly shifted to detect the difference between the A / D conversion outputs, and the upper reference current and the lower order output from the current source in the direction of decreasing the difference. The control means for variably controlling the ratio of the reference current is provided, and the ratio of the upper reference current and the lower reference current flowing through the integrator by the current source is automatically adjusted by the control means. It is a thing.

In order to solve the above-mentioned problems, the present invention further comprises a high-order counter and a low-order counter whose count state is changed by the output of a comparator for comparing the output of an integrator with a threshold value, and the total of the high-order counter. In a cascade integration type A / D converter equipped with a current source for supplying an upper reference current corresponding to a numerical value and a lower reference current corresponding to the count value of the lower counter to the integrator, A storage means for storing a value, a control means for inputting an input signal for offset detection in the adjustment mode and storing the value of the A / D conversion output thereof in the storage means, and a value stored in the storage means. Offset correction means for performing offset correction of the A / D conversion output based on the above, and the offset correction means corrects the offset of the A / D conversion output. Than it is.

Further, in order to solve the above problem, the present invention integrates the input data by integrating an upper reference current and a lower reference current provided by a current source for a time corresponding to the input data. A D / A converter for converting into an analog signal and outputting the analog signal includes a high-order counter and a low-order counter whose count state is changed by the output of a comparator for comparing the output of the integrator with a threshold value. In the D conversion section and the adjustment mode, the above A /
With the D conversion unit in a constant DC input state, the count time of the upper counter is forcibly shifted to detect the difference between the A / D conversion outputs, and the higher order output from the current source in the direction in which the difference decreases. A control means for variably controlling the ratio of the reference current and the lower reference current is provided, and the ratio of the upper reference current and the lower reference current supplied to the integrator by the current source is automatically adjusted by the control means. It is characterized by that.

[0024]

In the A / D converter according to the present invention, in the adjustment mode, the control means sets the constant DC input state and forcibly shifts the counting time of the upper counter to detect the difference between the A / D conversion outputs. , The ratio of the upper reference current and the lower reference current output by the current source is variably controlled so that the difference becomes smaller, and the ratio of the upper reference current and the lower reference current sent to the integrator is automatically adjusted by the current source. adjust.

Further, in the A / D converter according to the present invention, in the adjustment mode, the control means inputs the input signal for offset detection and stores the value of the A / D conversion output in the storage means. The offset correction means automatically performs offset correction of the A / D conversion output.

Further, in the D / A converter according to the present invention,
In the adjustment mode, the control means keeps the constant DC input state and forcibly shifts the counting time of the upper counter to set A /
The difference between the A / D conversion outputs by the D conversion unit is detected, and the ratio of the upper reference current and the lower reference current output by the current source is variably controlled in the direction in which the difference decreases, and the current source causes an integrator to operate. The ratio between the upper reference current and the lower reference current that is sent is automatically adjusted.

[0027]

EXAMPLE An A / D converter and a D / A according to the present invention will be described below.
An embodiment of the converter will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an A / D / D / A converter which is an embodiment of the present invention.

In this embodiment, the present invention is applied to an A / D / D / A converter having an A / D conversion function and a D / A conversion function used in a digital recording / reproducing system, which is a cascade integration method. And an A / D conversion unit and a D / A conversion unit configured to perform D / A conversion using the reference current source and the integrator of the A / D conversion unit, and are provided to the control circuit. Each changeover switch is controlled to be changed over according to the mode control signal.

In FIG. 1, an analog signal to be digitally converted is input to the analog input terminal 1.
This analog signal is supplied to the emphasis amplifier 3 via the input volume amplifier 2. The output signal from the emphasis amplifier 3 is supplied to the LPF (low pass filter) amplifier 5 via the first changeover switch 4. The output signal from the LPF amplifier 5 is supplied to the analog output terminal 6 and the headphone output terminal 8 via the headphone amplifier variable attenuator 7. The output signal from the LPF amplifier 5 is
Integrator 1 via second and third changeover switches 9 and 10
1 is supplied.

The integrator 11 includes an inverting amplifier 14 to which a signal input through the third changeover switch 10 is supplied to an input terminal through a series connection circuit of a resistor 12 and a sample hold switch 13. , This inverting amplifier 1
The input terminal and the output terminal of 4 are connected through the integrating capacitor 15, and the connection point between the resistor 12 and the sample hold switch 13 is connected through the resistor 16 to the output terminal of the inverting amplifier 14. Become.

In the A / D converter of this embodiment, the upper reference current source 17, the middle reference current source 18, and the lower reference current source 1 are connected to the input terminals of the inverting amplifier 14.
9 are connected via integration switches 20, 21, 22 respectively. Here, each of the reference current sources 17, 18,
The values of the reference currents I _H , I _M and I _L according to 19 are, for example, I
It is assumed that the ratio is _H : _IM : _IL = 256: 16: 1.

Further, the output terminal of the inverting amplifier 14 is connected to one input terminal of each of the first to third comparators 23, 24 and 25. A first threshold value V _THH is applied to the other input terminal of the first comparator 23, and
A second threshold value V _THM is applied to the other input terminal of the second comparator 24, and a third threshold value V _THL is applied to the other input terminal of the third comparator 25. There is.
Then, the comparison outputs of these comparators 23, 24, 25 are supplied to the control circuit 26.

The master clock is supplied from the clock terminal 27 to the control circuit 26, and the comparator 23,
Based on the comparison outputs of 24 and 25, the switch 2
The open / close control of 0, 21, 22 is performed, and the counting operation of each of the upper, middle, and lower counters 28, 29, 30 is controlled.

Each of the counters 28, 29, 30 is controlled by the control circuit 26 to perform a master clock counting operation, and the lower counter 30 supplies a carry output to the middle-order counter 29. 29 carries a carry output to the upper counter 30.

The count values of the upper, middle and lower counters 28, 29, 30 are output from the digital output terminal 32 via the input / output register 31 as A / D conversion outputs. ..

The above-mentioned configuration is a so-called cascade integration type A /
In the configuration of the D converter, in the A / D conversion mode and the adjustment mode, the A / D conversion unit uses the three cascade integration type A / D
The D conversion operation is performed.

Further, in this embodiment, the integrator 11 is used.
Each reference current source 17, 18, 19 for giving a reference current to
The upper reference current source 17 is the lower reference current source 1
248 times the current value to the lower reference current I _L by 9 (the current source unit 17A of 248I _L, 0.25 times,
0.5 times, 1 times, 2 times, 4 times and 8 times the current value (0.2
5I _L , 0.5I _L , 1I _L , 2I _L , 4I _L , 8
I _L ), each of the current source units 17a _{I to} 17f _I and each of the correction switches 17a _{S to} 17f _S are connected in parallel, and by setting the correction switches 17a _{S to} 17f _S , the lower reference 248 times to 2 for current 19
The current value of the reference current I _H of the upper is adjustable in a range of 64.75 times the current value 248I _L ~264.75I _L or about 256I _L ± 8I _L. The open / closed state of each correction switch 17a _{S to} 17f _S of the higher-order reference current source 17 is switched and set according to the count value of the up / down counter 33 that counts the sample clock.

In the adjustment mode, the input signal V _REF for adjustment of a predetermined DC level is supplied from the buffer amplifier 34 to the integrator 11 via the third changeover switch 10. Further, a series circuit of a switch 35s and a current source 35i is connected in parallel to a current source 35 which gives a first threshold value V _THH to the other input terminal of the first comparator 23, and the switch is operated in the adjustment mode. Three
5 s is controlled to open and close by the sample clock,
The threshold value V _{THH of} is reduced by ΔV every other sample.

Further, the latch outputs are compared with the first and second latch circuits 36 and 37 for latching the count values of the upper, middle and lower counters 28, 29 and 30, that is, the A / D conversion outputs. And a digital comparator 38 for
The converted output is latched by the first latch circuit 36, the A / D converted output for an even sample is latched by the second latch circuit 37, and each latched output is compared by the digital comparator 38. .. The digital comparator 38 controls the counting operation of the up / down counter 33.

The digital comparator 38 inputs the latch output of the first latch circuit 36 to the A input, and outputs the second latch signal to the second latch circuit 36.
The latch output of the latch circuit 37 of
When A = B, the up / down counter 33 is controlled to count up, and when A = B, the up / down counter 33 is controlled to stop counting. When A <B, the up / down counter 33 is counted down. It is designed to control the state.

With the above configuration, the ratio I _L : I _H between the lower reference current I _L and the upper reference current I _H flowing in the integrator 11 of the A / D converter is automatically adjusted to 1: 256 in the adjustment mode. Adjust accordingly.

Further, in this embodiment, the latch output of the first latch circuit 36 for latching the A / D conversion output for the odd sample in the adjustment mode is the AND gate 39.
A D / A conversion circuit 40 supplied via
The D / A conversion output from the A / A conversion circuit 40 is used as an offset correction signal via the resistor 41 to the resistor 1 of the integrator 11.
2 and the sample-hold switch 13 are connected to each other.

With the above configuration, the D of the A / D conversion section is
The offset of the / A conversion output is automatically adjusted.

Next, the D / A conversion unit in this embodiment is constructed by adding the following configuration to the A / D conversion unit as described above.

That is, in FIG. 1, a digital signal to be converted into an analog signal is supplied to the digital input terminal 42. This digital signal is sent from the digital input terminal 42 through the input / output register 31 to the upper, middle, and lower counters 28, 29, 3 respectively.
Loaded to zero. Then, the control circuit 26 controls the opening and closing of the integration switches 20, 21, 22 in accordance with the digital signals loaded in the counters 28, 29, 30 and is controlled by the reference current sources 17, 18, 19 in the upper order. , Middle and lower reference currents I _H , I _M and I _L are passed through the integrator 11. Further, the precharge voltage V _PRE is supplied to the integrator 11 from the precharge buffer 43 via the second changeover switch 9.

The integrated output of the integrator 11 is supplied to the deglitch sample and hold circuit 44.

Deglitch sample hold circuit 4
4 is provided with an inverting amplifier 47 to which the integrated output of the integrator 11 is supplied to an input terminal via a series connection circuit of a resistor 45 and a sample hold switch 46. The inverting amplifier 47 has an input terminal and an output terminal Hold capacitor 48
And the connection point between the resistor 45 and the sample hold switch 46 is connected to the output terminal of the inverting amplifier 47 via the resistor 49. The hold output of the deglitch sample and hold circuit 44 is supplied from the de-emphasis amplifier 50 to the LPF amplifier 5 via the first changeover switch 4.

Next, the operation of the A / D converter of the A / D / D / A converter having such a configuration will be described with reference to FIGS.
Will be described.

In this A / D / D / A converter,
The first and second changeover switches 4 and 9 are for switching between the A / D conversion mode and the D / A conversion mode.
Switching control is performed as follows according to a mode control signal applied to the control circuit 26 via the control input terminal 51.
That is, the first changeover switch 4 selects the output signal from the emphasis amplifier 3 in the A / D conversion mode and selects the output signal from the de-emphasis amplifier 50 in the D / A conversion mode. Control circuit 2
Switching control is performed by 6. Further, the second changeover switch 9 selects the output signal from the LPF amplifier 5 in the A / D conversion mode and selects the signal from the precharge buffer amplifier 43 in the D / A conversion mode. Switching control is performed by the control circuit 26.

Further, the third changeover switch 10 is
The A / D conversion mode, the D / A conversion mode, and the adjustment mode are switched, and the switching control is performed as follows according to the mode control signal given to the control circuit 26.
That is, the third changeover switch 10 outputs the output signal from the LPF amplifier 5 or the precharge buffer supplied through the second changeover switch 9 in the A / D conversion mode and the D / A conversion mode. The control circuit 2 selects the signal from the amplifier 43 and selects the signal from the adjustment buffer amplifier 34 in the adjustment mode.
Switching control is performed by 6.

In the A / D conversion mode, after the analog signal supplied to the analog input terminal 1 is controlled to have an appropriate amplitude by the input volume amplifier 2, the emphasis amplifier 3 has a time constant of 5 for example.
After the pre-emphasis of the characteristics of 0 μs and 15 μs is applied, the LPR is changed through the first changeover switch 4.
It is sent to the amplifier 5. In the LPF amplifier 5, the input analog signal is band-limited to 1/2 or less of the sampling rate, and so-called anti-aliasing processing is performed. The output signal from the LPF amplifier 5 passes through the second and third changeover switches 9 and 10 and the integrator 11
Sent to.

In the integrator 11, the time t ₁ shown in FIG.
By closing the sample-hold switch 13 for a time T ₁ of up to t ₂ , the input analog signal voltage V
_IN is sampled and stored in the integration capacitor 15, and at the time t ₂ , the sample-hold switch 13
Is opened, the sampled voltage is held.

Next, by the control operation of the control circuit 26, the upper integration switch 20 is closed at time t ₃ and the master clock counting operation by the upper counter 28 is started. Above integration switch 2
By closing 0, the upper reference current I _{H from} the reference power supply 17 is passed through the integrator 11. Then, the integrated output of the integrator 11 is the first threshold value V _THH.
During the time T ₂ until the time t ₄ which reaches, the counting operation by the upper counter 28 is performed.

Further, by the control operation of the control circuit 26, from the time t ₄ , the integration switch 21 of the middle level is started.
Is closed and the counting operation of the master clock by the intermediate counter 29 is started. By closing the intermediate integration switch 21, the reference power source 1
A medium reference current I _M of 8 is supplied to the integrator 11. Then, during the time T ₃ until the time t _{5 at} which the integrated output of the integrator 11 reaches the second threshold value V _THM , the counting operation of the master clock by the middle-order counter 29 is performed.

Further, by the control operation of the control circuit 26, from the time t ₅ , the integration switch 22 of the middle level is started.
Is closed and the counting operation of the master clock by the lower counter 30 is started. When the lower integration switch 22 is closed, the reference power source 1
The lower reference current I _L of 9 is supplied to the integrator 11. Then, during the time T ₄ until the time t _{6 at} which the integrated output of the integrator 11 reaches the second threshold V _THL , the counting operation of the master clock by the lower counter 30 is performed.

Here, each of the reference currents I _L , I _M , I _H
I _L : I _M : I _H = 2 ⁰ : 2 ⁴ : 2 ⁸ = 1: 16: 2
By having the relationship of 56, the upper counter 2
The 1 count of ⁸ is weighted 2 ⁸ times the 1 count of the lower counter 30, and the 1 count of the middle counter 29 is the 2 count of the 1 count of the lower counter 30.
Weighted ^four times.

Then, the count value of the master clock by the high-order counter 28 during the time T ₂ is set to the high-order bit, and the count value of the master clock by the middle-order counter 29 during the time T ₃ is set to the middle bit. A digital value which is a bit and whose lower bit is the count value of the master clock by the lower counter 30 during the time T ₄ is output from the output register 31 as a digital value output corresponding to the input analog signal voltage V _IN. Output terminal 32
Output serially via.

In the adjustment mode, instead of the input analog signal, a signal of a predetermined DC level is input to the integrator 11 from the adjustment buffer amplifier 34 via the third changeover switch 10. In this embodiment, the adjustment input signal from the buffer amplifier 34 gives the integrator 11 a DC level V _REF in the non-input state, that is, the muting state.

In the A / D conversion section, the control circuit 26 controls the opening / closing of the switch 35s so that the first threshold value V _THH is Δ for each even sample.
Input signal V _REF for the above adjustment with V lowered
The A / D conversion operation of the three cascade connection method as described above is performed.

Here, each of the reference currents I _L , I _M , I _H
If the ratio ( _IL : _IM : _IH ) of (1) is correctly adjusted, even if the first threshold value _VTHH is decreased by ΔV, the middle and lower counters 29, 30 perform a large counting operation. However, the digital value of the A / D conversion result does not change.

However, if the upper reference current I _H is deviated to have a large current value, for example, the upper counter 28 corresponding to ΔV obtained by lowering the first threshold V _THH is used.
The counters 30 in the middle and lower ranks have a larger count than the decrement of the count value x16, and the count operation is performed.
The digital value of the conversion result becomes a larger value accordingly.
On the contrary, if the higher-order reference current I _H has a small current value, the digital value of the A / D conversion result has a correspondingly small value.

In this embodiment, the first threshold value V _THH is lowered by ΔV for every even sample, and the A / D conversion operation of the three cascade connection system as described above is performed for the adjustment input signal V _REF . The A / D conversion output at the first threshold value V _THH for each odd sample is latched by the first latch circuit 36, and at the same time, the first threshold value V _THH − for every even sample.
The A / D conversion output at ΔV is transferred to the second latch circuit 3
7 and the difference, that is, the error in the ratio of the upper reference current I _{H to} the lower reference current I _{L is} detected by the digital comparator 38.

Then, the digital comparator 38
By controlling the counting operation of the up / down counter 33 by accumulating the difference between the converted output of the odd sample and the converted output of the even sample, and by the counted value of the up / down counter ○, the upper reference current. By switching the correction switches 17a _{S to} 17f _S of the source 17, the value of the upper reference current I _H is automatically adjusted so that the difference between the converted output of the odd sample and the converted output of the even sample becomes zero. Adjust to.

Further, in order to average and absorb the influence of fluctuations in the converted output due to noise or the like, the upper bit output of the up / down counter 33 causes the correction switches 17a _{S to} 17f _{S of the} upper reference current source 17 to be output. The switching setting of is set.

In the adjustment mode, the first threshold value V
Instead of lowering _THH by ΔV for every even sample, the control circuit 26 may control to forcibly shorten the counting operation period of the upper counter 28.

In this way, the value of the higher-order reference current I _H is automatically adjusted in the adjustment mode, and the adjusted value is held in the up / down counter 33. And in D / A conversion mode,
Each adjustment switch 17a _{S of the} upper reference current source 17 is adjusted by the adjustment value held in the up / down counter 33.
By switching and setting ~ 17f _S , the A / D conversion operation and the D / A conversion operation can be performed with extremely high accuracy.

Further, in the adjustment mode, since the input signal for adjustment having the DC level V _REF in the muting state is applied from the buffer amplifier 34 to the integrator 11, the first input signal for each odd sample is supplied. The first latch circuit 36 that latches the A / D conversion output at the threshold value V _THH of 1 latches the DC offset component in the A / D conversion unit. Therefore, in the A / D conversion section of this embodiment, the control circuit 26 opens the AND gate 39 in the A / D conversion operation mode.
As a result, the latch output of the first latch circuit 36 is given to the D / A conversion circuit 40 as offset correction data. The D / A conversion output of the D / A conversion circuit 40 is supplied to the integrator 11 via the resistor 41,
It is added to the input analog signal as an offset correction signal.

That is, in the A / D converter of this embodiment, offset correction is also automatically performed.

In the adjustment mode, one of the latch output by the first latch circuit 36 and the latch output by the second latch circuit 37 or the average output thereof is
Depending on whether the value itself is positive or negative, an up / down counter provided separately may be moved, or it may be accumulated as it is by an accumulator provided separately and fed back to the input. Further, instead of adding the conversion output of the D / A conversion circuit 40 as an offset correction signal to the input analog signal of the integrator 11, the offset correction data may be subtracted from the A / D conversion output by a digital subtractor. , The upper, middle, and lower counters 28,
A value obtained by subtracting the offset correction data from the original initial load value may be given to 29 and 30 as the initial load value.

Next, the operation of the D / A conversion mode will be described. In the D / A conversion mode, the integrator 11
In samples the constant precharge voltage V _PRE every sample, the reference current I _H according to the reference current source 7,18,19, I _M, changing the integrated output at a constant rate by integrating the I _L Then, the operation is stopped at the time of integration for a time corresponding to the input digital signal from the digital input terminal 42, and the integrated output is sampled and held by the sample hold circuit 44 for deglitch to obtain a stepwise output signal. There is.

That is, in the D / A conversion mode, the input digital signal is sampled from the digital input terminal 42 through the input / output register 31 for each upper sample,
The counters 28, 29, 30 of the middle and lower levels are loaded. Further, the precharge voltage V _PRE is supplied from the precharge buffer amplifier 43 to the integrator 11 via the second changeover switch 9.

In the integrator 11, time t ₁₁ shown in FIG.
When the sample-hold switch 13 is closed, the precharge voltage V _PRE from the precharge buffer amplifier 43 is applied to the input terminal of the inverting amplifier 14, and its integrated output after a predetermined time T _{11 has} elapsed. the time t ₁₂ converges to a high constant precharge voltage than the signal maximum voltage.

Next, by the control operation of the control circuit 26, the integration switches 20, 21, 22 are closed at time t _13, and the upper, middle _{, and} lower counters 28, 29, 30 are also closed. The counting operation of the master clock is started by. The control circuit 26 causes the upper counter 28 to count the value of the upper bit of the input digital signal loaded via the input / output register 31 during the period T ₁₂
Only the upper integration switch 20 is closed. Further, the middle-order integration switch 21 is closed only during the period T ₁₃ when the middle-order counter 29 counts the value of the middle-order bit of the input digital signal. Further, the lower integration switch 22 is closed for the period T _{14 in} which the lower counter 30 counts the value of the lower bit of the input digital signal.
When the integration switches 20, 21, 22 are closed, the reference currents I _H , I _M , I _{L from the} reference power sources 17, 18, 19 flow into the integrator 11, and the reference current I _H. , I _M , I _L , the integrated output is obtained. In FIG. 3, the integral component of the upper reference current I _H is indicated by a broken line a, and the integral component of the middle reference current I _M is indicated by a broken line b.
, And the integral component of the lower reference current I _L is indicated by the broken line c. The integrated output of the integrator 11 is sampled in voltage by the sample-hold switch 46 of the deglitch sample-hold circuit 44 being closed for a predetermined time from time t _17, and the hold capacitor 47 is used. Retained. As a result, a stepped output voltage as shown by V _OUT in FIG. 3 is obtained.
The time t ₁₇ is set after the time when the integration operation is finished even when the maximum digital value is input from the time t ₁₃ . The D / A conversion operation is performed by repeating such an operation for each sample.

Deglitch sample hold circuit 4
The stepped output voltage V _OUT obtained at 4 is sent to the de-emphasis amplifier 50, and de-emphasis that returns the pre-emphasis of 50 μs and 15 μs applied by the emphasis amplifier 3 to the original flat frequency characteristic. Can be hung. This de-emphasis amplifier 50
The output from is sent to the LPF amplifier 5 via the first changeover switch 4 and is 1 / of the sampling rate.
When the band is limited to 2 or less, it is converted into a smooth analog voltage waveform. The output signal from the LPF amplifier 5 is taken out as it is from the analog output terminal 6 as an analog line output, and the signal level is controlled by the headphone amplifier attenuator 7 and taken out as a headphone amplifier output from the headphone output terminal 8. ..

[0075]

In the A / D converter according to the present invention, in the adjustment mode, the control means brings the constant DC input state,
The difference between the A / D conversion outputs is detected by forcibly shifting the counting time of the high-order counter, and the ratio of the high-order reference current and the low-order reference current output by the current source is variably controlled so that the difference decreases. Since the ratio of the upper reference current and the lower reference current flowing through the integrator is automatically adjusted by the current source, high conversion accuracy can be obtained without the need for time-consuming trimming adjustment of the reference current ratio. Therefore, according to the present invention, when the A / D converter is integrated into an integrated circuit, the yield thereof can be increased, the cost can be reduced, and an inexpensive and high-performance A / D converter can be provided.

In the A / D converter according to the present invention, in the adjustment mode, the control means inputs the input signal for offset detection and stores the value of the A / D conversion output in the storage means. Since the offset correction means automatically corrects the offset of the A / D conversion output, it is possible to eliminate the conversion error due to the offset and obtain high conversion accuracy.

Further, in the D / A converter according to the present invention,
In the adjustment mode, the control means keeps the constant DC input state and forcibly shifts the counting time of the upper counter to set A /
The difference between the A / D conversion outputs by the D conversion unit is detected, and the ratio of the upper reference current and the lower reference current output by the current source is variably controlled in the direction in which the difference decreases, and the current source causes an integrator to operate. Since the ratio between the upper reference current and the lower reference current to be supplied is automatically adjusted, high conversion accuracy can be obtained without requiring time-consuming trimming adjustment of the ratio of the reference current. Therefore, according to the present invention, when the D / A converter is integrated into a circuit, the yield thereof can be increased, the cost can be reduced, and the inexpensive and high-performance D / A converter can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an A / D / D / A converter that is an embodiment of the present invention.

FIG. 2 A / D in the A / D / D / A converter
6 is a time chart for explaining the operation of the conversion mode.

FIG. 3 is a D / A in the A / D / D / A converter.
6 is a time chart for explaining the operation of the conversion mode.

FIG. 4 is a block diagram showing a configuration of a conventional cascade integration A / D converter.

FIG. 5 shows A / D of the conventional cascade integration type A / D converter.
6 is a time chart for explaining a D conversion operation.

[Explanation of symbols]

 1 ... Analog signal input terminal 5 ... LPF amplifier 6 ... Analog signal output terminal 10 ... Changeover switch 11 ... Integrator 17,18,19 ... Reference current source 20,21,22・ ・ ・ Integration switch 23, 24, 25 ・ ・ ・ Comparator 26 ・ ・ ・ ・ ・ ・ Control circuit 28 ・ ・ ・ ・ ・ ・ ・ High-order counter 29 ・ ・ ・ ・ ・ ・ ・ ・Position counter 30 ・ ・ ・ ・ ・ ・ Lower counter 31 ・ ・ ・ ・ ・ ・ Input / output register 32 ・ ・ ・ ・ ・ ・ ・ Digital signal output terminal 33 ・ ・ ・・ Up-down counter 34 ・ ・ ・ ・ ・ ・ ・ ・ Adjustment buffer amplifier 35i ・ ・ ・ ・ ・ ・ Current source 35s ・ ・ ・ ・ ・ ・ Switch 36, 37 ・ ・ ・ ・ ・ ・ ・ ・ Latch circuit 38 ... Digital comparator 39 ... ··· AND gate 40 ········· D / A conversion circuit

Claims (3)

[Claims] 1. A high-order counter and a low-order counter whose count state is changed by the output of a comparator that compares the output of an integrator with a threshold value, a high-order reference current corresponding to the count value of the high-order counter, and the low-order counter. In a cascade integration type A / D converter equipped with a current source for supplying a lower reference current corresponding to the count value of 1 to the integrator, in the adjustment mode, a constant DC input state is set, and the counting time of the upper counter is A control unit is provided which detects the difference between the A / D conversion outputs by forcibly shifting and variably controls the ratio of the upper reference current and the lower reference current output from the current source in the direction of reducing the difference. An A / D converter characterized in that a ratio of an upper reference current and a lower reference current passed through the integrator by the current source is automatically adjusted by the control means. 2. A high-order counter and a low-order counter whose count state is changed by the output of a comparator that compares the output of the integrator with a threshold value, a high-order reference current corresponding to the count value of the high-order counter, and the low-order counter. In a cascade integration A / D converter equipped with a current source for flowing a lower reference current corresponding to the count value of the above into the integrator, storage means for storing the value of the A / D conversion output, and Control means for inputting an input signal for offset detection and storing the value of the A / D conversion output in the storage means, and offset correction of the A / D conversion output based on the value stored in the storage means An A / D converter characterized in that an offset correction means is provided, and the offset of the A / D conversion output is corrected by the offset correction means. 3. A D / A conversion for converting the input data into an analog signal and outputting the analog signal by integrating an upper reference current and a lower reference current provided by a current source for a time corresponding to the input data by an integrator. In the converter, a cascade integration type A / D converter having an upper counter and a lower counter whose count state is changed by the output of the comparator that compares the output of the integrator with a threshold value, and the A / D converter in the adjustment mode With the D conversion unit in a constant DC input state, the count time of the upper counter is forcibly shifted to detect the difference between the A / D conversion outputs, and the higher order output from the current source in the direction in which the difference decreases. A control means for variably controlling the ratio of the reference current and the lower reference current is provided, and the ratio of the upper reference current and the lower reference current flowing through the integrator by the current source is controlled by the control means. A D / A converter characterized in that it is automatically adjusted by.