JPH05197551A - Coprocessor control system - Google Patents

Abstract

PURPOSE:To minimize a decrease in the performance of a CPU by providing a coprocessor interruption-inhibiting status without increasing the widths of buses between a CPU and a coprocessor and operating it. CONSTITUTION:This system is equipped with the coprocessor 2 and the coprocessor interruption-inhibiting status 7 which inhibits and allows the transmission of a coprocessor exception signal in the case of that exception is generated. The CPU 1 inputs and decodes instructions in order and sends only a coprocessor instruction to the coprocessor 2 on condition that the coprocessor interruption-inhibiting status 7 is ON once deciding the coprocessor instruction, thereby inhibiting the address of the coprocessor instruction from being sent out. When the coprocessor interruption-inhibiting status 7 is OFF, on the other hand, the coprocessor instruction and its address are sent out to the coprocessor 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coprocessor control system for controlling a coprocessor from a CPU.

With the recent demand for higher speed computer systems, systems in which a coprocessor is provided in addition to the CPU have become common. In this system, of the instructions fetched by the CPU, a specific instruction (hereinafter referred to as a coprocessor instruction) is passed to a coprocessor and executed by the coprocessor, and the result is received. At this time, high speed processing is required.

[0003]

2. Description of the Related Art Conventionally, as a system provided with a coprocessor in addition to a CPU, there is a system having a configuration as shown in FIG. This will be described below.

In FIG. 4A, a CPU 31 is a processing device, which decodes and executes an instruction read from a memory 33. The coprocessor 32 executes coprocessor instructions.

The memory 33 holds instructions and data. The memory bus 34 is from the memory 33 to the CPU 3
1 and the data transfer between the memory 33 and the CPU 31 and the coprocessor 32.

The coprocessor bus 35 transfers instruction codes / addresses between the CPU 31 and the coprocessor 32. The coprocessor exception signal 36 notifies the CPU 31 when an exception event occurs during execution of a coprocessor instruction by the coprocessor 32 (for example, an exception event such as overflow or underflow in the case of a floating point operation coprocessor).

Next, according to the time chart of FIG. 4B, the instruction execution of the CPU 31 is performed in the following sequence. (1) Fetch necessary instructions from the memory 33 through the memory bus 34 (stage F).

(2) The instruction is decoded (stage D). (3) Execute the instruction (stage E). (3-1) If the decoding result is not a coprocessor instruction (hereinafter referred to as a general instruction), the CPU 31 executes this general instruction.

(3-2) If the decoding result is a coprocessor instruction, the coprocessor instruction is sent to the coprocessor 32 through the coprocessor bus 35.

The address of this coprocessor instruction, which is a resource required for interrupt processing in the next cycle, is sent to the coprocessor 32 through the coprocessor bus 35 in advance.

(4) Store the result (stage W). On the other hand, the coprocessor 32 executes the coprocessor instruction in the following sequence. (11) Execute the instruction (stage CE).

(12) Store the result (stage C
W). Here, when a coprocessor exception (for example, an exception called overflow or underflow in the case of a floating point arithmetic coprocessor) is detected after the end of the stage CW, the coprocessor 32 sends the CP via the coprocessor exception signal 36.
The U31 is notified of the exception occurrence by an interrupt. The CPU 31 generates an interrupt according to the notification if the coprocessor interrupt is enabled. Then, in the interrupt processing routine, predetermined interrupt processing is performed using the instruction code and the address of the instruction held in the coprocessor 32.

If the coprocessor interrupt is disabled,
Ignore the notification.

[0014]

As described above, conventionally, the coprocessor instruction and the address of the instruction are always sequentially sent from the CPU 31 to the coprocessor 32 through the coprocessor bus 35 which is a single bus.
One would need a cycle for both of these,
There was a problem that performance was lowered.

The present invention solves these problems by
The purpose is to provide a coprocessor interrupt prohibition status and operate it without increasing the bus width between the CPU and the coprocessor, and to suppress the deterioration of the performance of the CPU to a necessary minimum.

[0016]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, a CPU 1 reads an instruction, decodes it, requests the coprocessor 2 to execute it when it is a coprocessor instruction, and executes it when it is another general instruction.

The coprocessor 2 is a processor for executing coprocessor instructions requested by the CPU 1. The memory 3 holds instructions and data.

The memory bus 4 transfers instructions and data between the memory 3 and the CPU 1 and the coprocessor 2. The coprocessor bus 5 is a bus for sending a coprocessor instruction or the like from the CPU 1 to the coprocessor 5.

The coprocessor exception signal 6 notifies the CPU 1 when the coprocessor 2 executes a coprocessor instruction and an exception occurs. The coprocessor interrupt prohibition status 7 is a status that prohibits / permits the transmission of the coprocessor exception signal to the CPU 1 when the coprocessor 2 causes an exception due to execution of the coprocessor instruction.

[0020]

According to the present invention, as shown in FIG. 1, when the CPU 1 sequentially fetches an instruction from the memory 3 through the memory bus 4 and decodes it to find a coprocessor instruction, when the coprocessor interrupt prohibition status 7 is ON. Only coprocessor instructions through coprocessor bus 5 to coprocessor 2
To prevent the address of the coprocessor instruction from being sent, while the coprocessor interrupt disable status 7 indicates OF
At F, the coprocessor instruction and the address of the coprocessor instruction are sent to the coprocessor 2.

When a coprocessor instruction is sent from the CPU 1 and the coprocessor 2 that fetches the coprocessor instruction executes and an exception occurs, the coprocessor interrupt prohibition status 7
Is turned on, the notification of the exception to the CPU 1 is suppressed, exception processing is performed, and the result is stored as an execution result. On the other hand, when the coprocessor interrupt prohibition status 7 is off, the exception (coprocessor The exception signal 6) is notified to the CPU 1, and the CPU 1 having received the notification performs a predetermined interrupt process based on the coprocessor instruction held by the coprocessor 2 and its address.

Therefore, without increasing the bus width between the CPU 1 and the coprocessor 2, the coprocessor interrupt prohibition status 7 is provided and operated to eliminate the transmission of unnecessary instruction addresses, thereby degrading the performance of the CPU 1. Can be prevented.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 2 shows a block diagram of an embodiment of the present invention.
In FIG. 2, the CPU 1 includes a memory 3 to a memory bus 4
It reads and decodes an instruction through to perform various processes. Here, when it is decoded and found to be a coprocessor instruction, only the coprocessor instruction is sent to the floating point coprocessor 21, here, to the floating point coprocessor 21 when the coprocessor interrupt prohibition status 7 is ON, and on the other hand, Coprocessor interrupt disable status 7
When is OFF, the coprocessor instruction and the address of the instruction are sent together to the floating point coprocessor 21 through the coprocessor bus 5 to request execution. When the floating-point coprocessor 21 executes the coprocessor instruction and an exception (overflow, underflow) occurs,
When the coprocessor interrupt prohibition status 7 is ON, the coprocessor exception signal 6 is suppressed and the result of exception processing is stored in the memory 3 as an execution result. On the other hand, when the coprocessor interrupt prohibition status 7 is OFF, the coprocessor exception signal 6 is notified to the CPU 1, and the CPU 1 that has accepted the interrupt refers to the coprocessor instruction and the address of the instruction held by the floating point coprocessor 21, Perform predetermined interrupt processing.

The floating point coprocessor 21 is a CPU 1
From the coprocessor bus 5 and executes the coprocessor instruction.
When an exception (overflow or underflow) occurs as a result of execution, when the coprocessor interrupt disable status 7 is ON, the coprocessor exception signal 6 is set to C.
It suppresses sending to PU1 and stores the maximum value or zero as an execution result in the memory 3 as an exception process. On the other hand, the coprocessor interrupt disable status 7 is OFF
In the case of, the coprocessor exception signal 6 is sent to the CPU 1.

The memory 3 holds instructions and data. The memory bus 4 transfers an instruction read from the memory 3 to the CPU 1, transfers data sent from the CPU 1 to the memory 3, and the like.

The coprocessor bus 5 transfers the coprocessor instruction, instruction address, etc. sent from the CPU 1 to the floating point coprocessor 21. The coprocessor exception signal 6 is a signal that the floating-point coprocessor 21 sends to the CPU 1 when an exception occurs when the coprocessor interrupt prohibition status 7 is OFF.

The coprocessor interrupt prohibition status 7 is a status for prohibiting exception interruption from the floating point coprocessor 21, and the instruction fetched and decoded by the CPU 1 is a coprocessor instruction, and when this is ON. Only the coprocessor instruction is sent to the floating point coprocessor 21, and the sending of the instruction address is suppressed. On the other hand, when this is OFF, both the coprocessor instruction and the address of the instruction are sent to the floating point coprocessor 21.
Then, when the floating-point coprocessor 21 executes the requested coprocessor instruction and an exception (overflow or underflow) occurs, when the coprocessor interrupt disable status 7 is ON, the coprocessor exception signal 6 is output. It suppresses sending to the CPU 1 and performs exception processing. On the other hand, the coprocessor interrupt disable status 7 is OFF
When, the coprocessor exception signal 6 is sent to the CPU 1,
The CPU 1 performs an interrupt process.

The register 11 sets the coprocessor interrupt prohibition status 7. In this register 11, an application program or the like turns ON / OFF a bit in advance.
ON / OFF the coprocessor interrupt prohibition status 7.
To do.

Next, referring to the time chart of FIG.
The operation of the above configuration will be described in detail. FIG. 3A is a time chart of the coprocessor interrupt prohibited state (when the coprocessor interrupt prohibited status 7 is ON). here,
The shaded area is the CI (coprocessor instruction) of this embodiment.

In FIG. 3A, stage F: CP
U1 fetches (reads) the shaded coprocessor instruction CI from the memory 3 through the memory bus 4. Stage D: The read coprocessor instruction CI is decoded, and it is determined here as a coprocessor instruction, and
The coprocessor interrupt status 7 of the register 11 is read and recognized.

Stage E: Execute instruction. here,
Only the coprocessor instruction CI is sent to the floating-point coprocessor 21 through the coprocessor bus 5 because it is determined that the coprocessor instruction is in the stage D and the coprocessor interrupt status 7 is turned on. At this time, since the coprocessor interrupt status 7 is ON, sending of the address of the coprocessor instruction CI is suppressed.

Stage W: The result is stored in the general instruction, but it is not stored here. The requested floating point coprocessor 21 stores the result in the stage CW. As described above, the CPU 1 decodes the instruction at the stage D and finds that it is a coprocessor instruction, and it turns out that the coprocessor interrupt status 7 is ON. Notify the processor 21 and request execution. This allows the CPU
1 does not need to pass the address of the coprocessor instruction, which has been passed along with the coprocessor instruction in the past, and the amount of processing is reduced by this amount, and the performance of the CPU 1 can be improved.

Next, stage CE: CPU at stage D
The floating point coprocessor 21 to which the coprocessor instruction CI is passed from 1 executes this coprocessor instruction CI.

Stage CW: The execution result is stored in a predetermined address of the memory 3. If an exception (overflow or underflow) occurs during this execution, the floating-point coprocessor 21 has found that the coprocessor interrupt prohibition status 7 is ON here. To store. The coprocessor exception signal is not notified to the CPU 6.

By the above, the floating point coprocessor 2
1 does not need to notify the CPU 6 of the coprocessor exception signal in response to the occurrence of an exception when the requested coprocessor instruction is executed, so that the CPU 1 is not interrupted and the processing is simplified. .. In particular, as described above, the coprocessor exception signal eliminates the need for an address for the CPU 1 to determine which coprocessor instruction caused the exception in the interrupt processing, and when requesting, the CPU 1 sets the address of the coprocessor instruction to the floating point. Since there is no need to notify the coprocessor 21, the amount of processing by the CPU 1 is reduced, and a decrease in performance can be prevented.

FIG. 3B is a time chart of the coprocessor interrupt enable state (when the coprocessor interrupt disable status 7 is OFF). Here, the shaded portion is the CI (coprocessor instruction) of this embodiment.

In FIG. 3B, stage F: CP
U1 fetches (reads) the shaded coprocessor instruction CI from the memory 3 through the memory bus 4. Stage D: The read coprocessor instruction CI is decoded, and it is determined here as a coprocessor instruction, and
Coprocessor interrupt status 7 of register 11 is OFF
Read and recognize.

Stage E: Execute instruction. here,
Since the coprocessor instruction is found to be a coprocessor instruction at stage D and the coprocessor interrupt status 7 is found to be OFF, both the coprocessor instruction CI and the address of the coprocessor instruction CI are transferred to the floating point coprocessor 21 through the coprocessor bus 5. To notify.

Stage W: A general instruction stores the result, but not here. The requested floating point coprocessor 21 stores the result in the stage CW. As described above, when the CPU 1 decodes the instruction in the stage D and finds that it is a coprocessor instruction, the coprocessor interrupt status 7 is found to be OFF. Therefore, in the instruction execution stage of the stage E, both the coprocessor instruction and the address are processed. The floating point coprocessor 21 is notified and requested to be executed.

Next, in the stage CE: stage D, the CPU
The floating point coprocessor 21 to which the coprocessor instruction CI is passed from 1 executes this coprocessor instruction CI.

Stage CW: The execution result is stored in a predetermined address of the memory 3. When an exception (overflow or underflow) occurs during this execution, the floating-point coprocessor 21 notifies the CPU 1 of the coprocessor exception signal 6 because the coprocessor interrupt prohibition status 7 is found to be OFF here. Then, an interrupt is generated in the CPU 1, and in the interrupt process, a predetermined exception process is performed based on the coprocessor instruction of the floating point coprocessor 21 and its address.

[0043]

As described above, according to the present invention,
When the CPU 1 sequentially fetches and decodes the instructions and finds that they are coprocessor instructions, only the coprocessor instruction is sent to the coprocessor 2 when the coprocessor interrupt disable status 7 is ON, and the address of the coprocessor instruction is sent. Since the CPU 1 and the coprocessor 2 are configured to suppress the sending of the coprocessor exception signal when the coprocessor 2 executes the requested coprocessor instruction and an exception occurs, the coprocessor 2 does not notify the CPU 1. Without increasing the bus width between the two, the coprocessor interrupt prohibition status 7 is provided and operated to eliminate unnecessary instruction address transmission and prevent the performance degradation of the CPU 1.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an example of a time chart of the present invention.

FIG. 4 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: CPU 11: Register 2: Coprocessor 21: Floating point coprocessor 3: Memory 4: Memory bus 5: Coprocessor bus 6: Coprocessor exception signal 7: Coprocessor interrupt disable status

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyasu Nonomura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Toru Watanabe, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Takeno, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Shinya Kato, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited (72) Inventor Pawnshai Chung Suvarnapaisan 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (3)

[Claims] 1. A coprocessor control system for controlling a coprocessor from a CPU, wherein a coprocessor (2) requests execution of a coprocessor instruction by the CPU (1) and an exception occurs when the coprocessor (2) executes the coprocessor instruction. When a CPU (1) sequentially fetches and decodes instructions, the coprocessor interrupt inhibit status (7) that inhibits / permits the sending of a coprocessor exception signal when When the coprocessor interrupt prohibition status (7) is ON, only the coprocessor instruction is sent to the coprocessor (2), the sending of the address of the coprocessor instruction is suppressed, while the coprocessor interrupt disable status is given. When (7) is OFF, the coprocessor instruction and the address of the coprocessor instruction are sent to the coprocessor (2). Coprocessor control method, characterized by being configured to. 2. When a coprocessor instruction is sent from the CPU (1) and the coprocessor (2) that takes in the coprocessor instruction executes it and an exception occurs, the coprocessor interrupt disable status (7) is ON. Occasionally the CPU (1)
Notify the exception to the above, but when the coprocessor interrupt disable status (7) is OFF, the exception is sent to CP.
The U (1) is notified, and the CPU (1) that has received the notification performs a predetermined interrupt process based on the data held by the coprocessor (2). The coprocessor control method described in the paragraph. 3. When the coprocessor (2) executes and an exception occurs, it is suppressed that the exception is notified to the CPU (1) when the coprocessor interrupt disable status (7) is ON. 3. The coprocessor control method according to claim 2, wherein the exception processing result is stored as an execution result.