JPH0519728A - Display controller - Google Patents

Abstract

PURPOSE:To secure the compatibility between displays by realizing a normal data display on a display device having different horizontal resolution even when the number of horizontal display dots which is adapted to certain horizontal resolution is set by the display controller which enables different kind of display devices to be used in common. CONSTITUTION:The number of horizontal display dots of the higher horizontal resolution is set in a 1st horizontal display end value register 10b. In a 2nd horizontal display end value register 10c, on the other hand, the number of horizontal display dots of lower horizontal resolution is set. The counted value of a horizontal timing counter 10a is compared with the number of horizontal display dots. When the comparison result indicates a discrepancy, a horizontal display end signal HE which ends display operation of one line period of a screen is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device which functions as a shared display controller for a CRT display device and a flat panel display device.

[0002]

2. Description of the Related Art Conventionally, a personal computer has a CRT display device (hereinafter simply referred to as CRT) and a flat panel display device (FP) as a display device.
There is a method of using one of D) interchangeably. In this method, as a display control device for controlling each display device, for example, VGA (Video Graphics) is used.
Shared display controllers such as Array) have been developed.

When displaying characters on a CRT or FPD screen, the number of characters displayed on one line is determined by the display character size per raster (the number of dots in the horizontal direction of the screen) and the horizontal resolution of the screen. .. In particular,
When the display character size per raster is, for example, 8 dots, 1 is displayed on a CRT screen having a horizontal resolution of 640 dots.
80 characters are displayed per line.

The display controller executes data display in dot units in the horizontal direction of the screen of the CRT at the horizontal display timing as shown in FIG. The 1-line scanning time which is the generation timing of the horizontal synchronizing signal is determined by the horizontal timing counter which counts the clock corresponding to the timing of horizontally shifting the display data in dot units. The display period is started by the initial setting of the horizontal timing counter (the generation timing of the horizontal display start signal), and the display period is ended by the horizontal display end signal.

That is, as shown in FIG. 3, the one-line display period which is the horizontal direction of the screen is determined. The one-line display period is determined by the horizontal display end signal output when the count value of the horizontal timing counter and the preset horizontal display end value (horizontal display dot number) match. Here, the period from the horizontal display end signal to the next horizontal display start signal is referred to as blanking time, and is used for the return time of one line scanning, the refresh of the display memory, the generation of the horizontal synchronizing signal, and the like.

By the way, the horizontal display end value, that is, the number of horizontal display dots for one line is set by an application program executed by a computer. In the case of a CRT having a horizontal resolution of 640 dots, the number of horizontal display dots corresponding to a maximum of 80 characters per line is set.

In the case of the shared system of CRT and FPD, the horizontal resolution of FPD is usually smaller than the horizontal resolution of CRT. Therefore, if the number of horizontal display dots that is greater than the number of horizontal display dots applied to the horizontal resolution of the FPD is set by the application program created for the CRT, normal data display on the FPD screen is impossible. Becomes

[0008]

In a system in which a CRT and an FPD are commonly used, the horizontal resolutions of both screens are usually different. Therefore, the number of horizontal display dots (the number of display characters for one line) applied to the larger horizontal resolution. ) Is set, normal data cannot be displayed on the screen with the smaller horizontal resolution. Therefore, depending on the contents of the application program, compatibility between the CRT and FPD display devices may not be ensured.

It is an object of the present invention, in a display control device of a system in which different types of display devices are shared, even when the number of horizontal display dots applied to one horizontal resolution is set, the display device of the other horizontal resolution is set. It is to realize normal data display and ensure compatibility of each display device.

[0010]

The present invention is a CRT and an FP.
In a display control device of a system sharing D, horizontal timing counter means for counting the number of dots when displaying display data in 1-dot units in the horizontal direction of the screen for one line period of the screen, and horizontal resolution of the display device. And a horizontal display control means for terminating the display operation for one line period of the screen.

[0011]

In the present invention, the horizontal display control means compares each horizontal display dot number corresponding to the horizontal resolution stored in the register means with the count value output from the horizontal timing counter means. When the count value and one of the numbers of horizontal display dots match according to the comparison result, the display operation for one line period of the screen is ended.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of a horizontal display control circuit which is a main part of the display control apparatus according to the embodiment. FIG. 2 is a block diagram showing the configuration of the display control device according to the embodiment.

The display control device 1 is a device for controlling a display device mounted on, for example, a personal computer, and operates under the control of a host computer (CPU). In the present invention, the display device is a CRT display device (hereinafter simply referred to as CRT) and a flat display device (FPD) such as a liquid crystal display.

As shown in FIG. 2, the apparatus 1 includes a horizontal display control circuit 10, a parameter register 11, a graphics / video data generation circuit 12, a text / video data generation circuit 13, a mode setting circuit 14 and a transparency control circuit. It is equipped with 15.

The parameter register 11 is a memory that holds various parameters transferred from the CPU 2. The various parameters include an address A, an I / O write control signal, and display data CD. The graphics / video data generation circuit 12 includes a graphics memory 3
Graphics data stored in the video data G
This is a circuit for converting to D. The text / video data generation circuit 13 generates text (font data) / video data TD corresponding to the character code data CC from the CPU 2.
Is a circuit for outputting. The mode setting circuit 14 is a circuit for setting the transparent mode in the case of performing superimposition display of graphics and text (character data) according to the parameter (graphics display mode) from the parameter register 11. . The transparent mode is a mode for displaying text with graphics as a background. The transparency control circuit 15 is a circuit that outputs a transparency control signal based on the transparency mode from the mode setting circuit 14 and the attribute data (display attribute data) AD from the CPU 2.

Here, the CPU 2 stores the attribute data AD and the character code data CC in the text memory 20. The CPU 2 controls to read out the attribute data AD and the character code data CC from the text memory 20 in synchronization with the screen display control signal when displaying on the screen of the CRT 5 or the FPD 6.

Further, the present apparatus includes a selection control circuit 16, a clock generation circuit 17 and a CRT output circuit 18. The clock generation circuit 17 generates various clock signals CL and CR necessary for display operation. Clock signal CR
Is a clock pulse that determines the timing of displaying in dots in the horizontal direction of the screen of the display device,
It is supplied to the horizontal display control circuit 10. CRT output circuit 1
Reference numeral 8 denotes a D / A conversion circuit (D / A conversion circuit) for converting the CRT output data, which is the graphics video data GD or the text video data TD, output from the video data generation circuits 12 and 13 based on the selection signal from the selection control circuit 16. DA
C) Output to 4. Based on the display data CD and CRT output data from the CPU 2, the DAC 4 outputs the CRT 5
Outputs RGB signals for color display on the screen.

The FPD 6 performs a display operation on the screen according to the FPD display signal output from the FPD conversion circuit 21. The FPD conversion circuit 21 is a circuit that receives the RGB signal (256 colors) from the DAC 4 and the CRT output data from the CRT output circuit 18, and is an A / D that converts the RGB signal that is an analog signal into a digital signal.
It has a conversion circuit.

The horizontal display control circuit 10 is a circuit related to the gist of the present invention, and as shown in FIG. 1, a horizontal timing counter 10a and a first horizontal display end value register 10 are provided.
b, a second horizontal display end value register 10c, a first comparison circuit 10d, a second comparison circuit 10e, and an OR gate circuit 10f.

The horizontal timing counter 10a counts the clock signal CR from the clock generation circuit 17,
The counting operation is performed up to the count value corresponding to the period of one line in the horizontal direction of the screen. The number of horizontal display dots corresponding to the horizontal resolution of the CRT 5 is set in the first horizontal display end value register 10b from the CPU 2 through the parameter register 11. The number of horizontal display dots of the CRT 5 is a display end value for one line, and is the maximum number of display dots for one line displayed in dot units.

The number of horizontal display dots corresponding to the horizontal resolution of the FPD 6 is set in the second horizontal display end value register 10c. The number of horizontal display dots of this FPD 6 is F
This is the display end value for one line of PD6 and is normally CR
It is a value smaller than the number of horizontal display dots of T5. That is, F
The horizontal resolution of PD6 is usually smaller than that of CRT5.

The first comparison circuit 10d compares the count value of the horizontal timing counter 10a with the number of horizontal display dots of the first horizontal display end value register 10b, and if they match, outputs the horizontal display end signal HE to the OR gate circuit. Output to 10f. On the other hand, the second comparison circuit 10e compares the count value of the horizontal timing counter 10a with the number of horizontal display dots of the second horizontal display end value register 10c, and if they match, outputs the horizontal display end signal HE to the OR gate circuit 10.
output to f. The OR gate circuit 10f outputs the horizontal display end signal HE as a display enable signal to the graphics / video data generating circuit 12 and the text / video data generating circuit 13. Next, the operation of the embodiment will be described.

First, the CPU 2 of the personal computer
Starts the superimposed display of, for example, text and graphics in response to the execution of the application program (step S1 in FIG. 4). Here, the CRT 5 is used as the display device (step S in FIG. 4).
2 NO).

In the display control device 1, the CR which is the graphics video data GD or the text video data TD output from the video data generation circuits 12 and 13 is used.
The T output data is output to the D / A conversion circuit (DAC) 4. The DAC 4 outputs an RGB signal for performing color display on the screen of the CRT 5 based on the display data CD and CRT output data from the CPU 2. The clock signal C from the clock generation circuit 17 is displayed on the screen of the CRT 5.
In synchronization with R, data display for one line is executed in dot units.

By the application program, a predetermined horizontal display dot number is set in the first horizontal display end value register 10b through the parameter register 11 within the range of the horizontal resolution of the CRT 5 (step S8). The horizontal timing counter 10a counts the clock signal CR and counts up to a count value corresponding to the number of horizontal display dots set by the application program. The horizontal timing counter 10a outputs a count value for each count (step S9).
That is, when the number of dots for one line on the screen of the CRT 5 is displayed, the horizontal timing counter 10a outputs the count value.

The first comparison circuit 10d compares the count value of the horizontal timing counter 10a with the horizontal display dot number of the first horizontal display end value register 10b (step S10). If the comparison results match (step S1
1), the first comparison circuit 10d outputs the horizontal display end signal HE to the OR gate circuit 10f. The OR gate circuit 10f outputs the horizontal display end signal HE to the graphics / video data generating circuit 12 and the text / video data generating circuit 13. As a result, as shown in FIG. 3, after the horizontal display is started, the horizontal display end signal H
The display operation for one line until the occurrence of E is executed.

On the other hand, as a display device, an FPD is used.
When 6 is used (YES in step S2), the number of horizontal display dots corresponding to the horizontal resolution of the FPD 6 is set in the second horizontal display end value register 10c through the parameter register 11 (step S3). ). The number of horizontal display dots is a fixed value determined by the horizontal resolution of the FPD 6.

The horizontal timing counter 10a counts the clock signal CR and counts up to a count value corresponding to the number of horizontal display dots set by the application program. The second comparison circuit 10e compares the count value of the horizontal timing counter 10a with the number of horizontal display dots of the second horizontal display end value register 10c (step S5). Here, the number of horizontal display dots of the second horizontal display end value register 10c is a value smaller than the number of horizontal display dots set by the application program.

If the comparison results match (Y in step S6)
ES), the second comparison circuit 10e causes the horizontal display end signal HE
Is output to the OR gate circuit 10f. OR gate circuit 1
0f outputs the horizontal display end signal HE to the graphics / video data generation circuit 12 and the text / video data generation circuit 13.

As a result, the display of one line on the screen of the FPD 6 ends, but the latter half of the number of horizontal display dots set by the application program is deleted. That is, among the data displayed on the screen of the CRT 5, the data on the right end side of the screen is not displayed on the screen of the FPD 6.

On the other hand, as shown in FIG. 3, by generating the horizontal display end signal HE, the blanking time can be secured, so that the return of one line scanning, the refresh of the display memory, and the horizontal synchronizing signal are performed. Occurrence can be reliably performed. Therefore, the application
Although a part of the display set by the program is deleted, the display in the range corresponding to the horizontal resolution of the FPD 6 is normal.

[0033]

As described above in detail, according to the present invention, in a display control device of a system in which different kinds of display devices are shared, for example, by an application program,
When the number of horizontal display dots applied to the one with the larger horizontal resolution is set, it is possible to realize normal data display on the screen of the display device with the smaller horizontal resolution. Therefore, compatibility of each display device can be ensured.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a horizontal display control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of a display control device according to the embodiment.

FIG. 3 is a timing chart for explaining a conventional method.

FIG. 4 is a flowchart for explaining the operation of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Display control device, 2 ... CPU, 10a ... Horizontal timing counter, 10b ... 1st horizontal display end value register,
10c ... Second horizontal display end value register, 10d ... First
Comparing circuit 10e ... Second comparing circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G09G 5/18 8121-5G

Claims (1)

Claim: What is claimed is: 1. A display control device for performing display control such that a CRT display device and a flat panel display device can be shared, for displaying on a display screen of the CRT display device or the flat panel display device. Display data generating means for generating the display data of, and a horizontal line for counting one line display period of the display screen when the display data output from the display data generating means is displayed in the horizontal direction of the display screen. Timing counter means, and a first horizontal display dot number and a second horizontal display dot number corresponding to one line display period of the display screen according to each horizontal resolution of the CRT display device and the flat panel display device. Register means for storing, and the first and second horizontal display dots stored in the register means And comparing means for comparing the count value output from the horizontal timing counter means, and based on the comparison result by the comparing means, when the count value and one of the horizontal display dot numbers match, A display control device comprising: a horizontal display control means for terminating the display operation for one line display period of the display screen.