JPH05191296A - 1-7rll code conversion circuit - Google Patents

Abstract

PURPOSE:To easily form the 1-7RLL code conversion circuit by logically generating a clock whose frequency is 2/3 with respect to a reference clock frequency from the reference clock and automatically adjusting the duty ratio. CONSTITUTION:An internal clock generating section 2 generates an internal clock A14 whose frequency is 2/3 of a frequency of a reference clock. A delay circuit section 3 delays the internal clock A 14 to generate internal clocks 1-N whose delay differs from each other. A duty adjustment section 5 generates a (2/3) f clock 17 from the internal clocks 1-N. A duty control section 4 generates duty control signals 1-N by recognizing the duty ratio of the (2/3) f clock 17 and adjusts automatically the duty ratio by sending them to a duty adjustment section 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording code conversion circuit having a data conversion rate of 2/3, and more specifically, a (1,7) RLL recording code for a recording medium such as a magnetic disk device.
The present invention relates to a 1-7 RLL code conversion circuit using a code.

[0002]

2. Description of the Related Art Recording in a magnetic disk system is performed by converting a data string into a recording code suitable for magnetic recording. The recording code is RLL (Run-Length-Limi
The recording density is improved by using the ted) code. Many RLL codes have been devised and each has its own characteristics, but the (1,7) RLL code is widely adopted as one suitable for magnetic recording. (1,
7) The RLL code has a coding rule that a minimum of one and a maximum of seven "0" s are inserted between adjacent "1" s in a coded data string. In this encoding format, it is known that the conversion rate for converting 2 bits of coded data into 3 bits of encoded data is optimum. Therefore, the converter (encoder, decoder) in the system using this recording code needs to have a clock of frequency (2/3) f with respect to the frequency f of encoded data. Of course, the two clocks must be synchronized.

Normally, a dedicated VFO (Voltage-F)
(requiry-oscillator)
A clock of frequency (2/3) f is derived from the reference clock of frequency f. However, such a method increases the hardware and complicates the system. In addition, the frequency f and the frequency (2 /
3) In order to derive f, there is a method of preparing a reference clock of frequency 2f or using the reference clock with frequency f and a duty ratio of 33% or 66%. The former requires a frequency twice as high as that of encoded data, and therefore requires high-speed circuit operation and is prone to malfunction due to noise or the like caused by a high-frequency clock. The latter depends on the other party (hard disk control, etc.) with which the data string is transferred, but since this (2/3) f clock is normally used as the reference clock for subsequent processing, the duty ratio is expected (50 % Is required), and the hard disk controller may malfunction at the above duty.

Therefore, a method of adjusting the duty ratio by using a delay circuit or an external delay element has been proposed (JP-A-2-302128). However, this method requires the delay amount of the delay unit to be constant and the duty ratio of the reference clock to be constant. In addition, a method has been proposed in which data is encoded and decoded for every 8 bits (1 byte) and a clock of frequency (2/3) f is unnecessary (Japanese Patent Laid-Open No. 61-288624). Since this method transfers data in units of 8 bits, it is necessary to change the entire system including the peripheral of the converter for a general serial data encoding system, which lacks versatility. ..

[0005]

In the conventional circuit, the system becomes complicated and there is a problem in versatility and reliability, and it is not effective especially for downsizing the system. The object of the present invention is to solve the above-mentioned problem. It is possible to obtain a (2/3) f clock from a reference clock of frequency 1f by a logical method without using the reference clock of frequency 2f, and further The code conversion is performed by a clock that can be sufficiently guaranteed even when the duty ratio of the system has a plurality of transfer rates in a single system, and can be sufficiently ensured even when the delay value of the system changes due to an external environment. It is to provide a -7RLL code conversion circuit.

[0006]

In order to achieve the above object, the 1-7RLL code conversion circuit according to the present invention converts an unconstrained data sequence into a constrained code sequence or inverse conversion, and the conversion ratio is 2 /. In the 1-7 RLL conversion circuit which is 3, an internal clock generating means for generating an internal clock and (2/3) of the internal clock from the internal clock
Means for deriving a clock of frequency, said (2/3)
It comprises a duty adjusting means for adjusting the duty ratio of the frequency clock and a duty controlling means for automatically controlling the adjustment amount of the duty ratio.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 is a circuit block diagram showing an embodiment of a 1-7 RLL code conversion circuit according to the present invention. In this embodiment, a selector 1 for selecting either the read clock 11 or the write clock 12, an internal clock generator 2 for generating a clock required for internal operation from a selected clock 13 selected by the selector 1, and an internal clock generator 2. Of the two outputs, a delay circuit section 3 for extracting and delaying an internal clock A14 having a frequency of 2/3 with respect to the selected clock 13 and a duty control from internal clocks 1 to N15 delayed by the delay circuit section 3 for the internal clock A14 Duty control section 4 for generating signals 1 to N16, internal clocks 1 to N15 and duty control signals 1 to N16
Adjust the duty ratio by (2/3) f clock 17
Is formed by a duty adjusting unit 5 and an encoder / decoder 6 that performs code decoding of data.

The reading operation of the embodiment shown in FIG. 1 will be described below with reference to FIGS. At the time of reading, the selector 1 selects the read clock 11 as the selected clock 13, and the internal clock generator 2 uses this read clock 11 as the reference clock. FIG. 2 is a circuit block diagram showing details of the internal clock generator 2.
The internal clock generator 2 includes an inverter 2e, flip-flops 2a, 2b, 2c and 2d, AND circuits 2f, 2
g, 2h and 2i, and an OR circuit 2j. The inverted Q output of the flip-flop 2a outputs an internal clock B21 having a cycle three times as long as the reference clock. Further, from the Q output of the flip-flop 2c, an internal clock having a period three times as long as the reference clock and having a phase of π
The internal clock C22 shifted by (180 °) is output.
These internal clocks B21 and C22 are input to the OR circuit 2j, and the output of the OR circuit 2j outputs 2 clocks of the reference clock.
A clock having a frequency of / 3 (internal clock A14) is output. The duty ratio of the internal clock A14 is about 6
6%. FIG. 6 shows the timing waveform.

FIG. 3 is a circuit block diagram showing details of the delay circuit section 3 of FIG. The delay circuit unit 3 includes a plurality of delay elements 3
a to 3n-1. The internal clock A14 is sequentially delayed by the delay elements 3a to 3n-1, and internal clocks 1 to N are generated from the outputs of the delay elements. The internal clock 1 is taken from the input of the delay element in the first stage and is the same as the internal clock A14. FIG. 7 shows the timing waveform at that time.

FIG. 4 is a circuit block diagram showing details of the duty control unit 4. The duty control unit 4 is composed of flip-flops 4a to 4n and a duty comparison circuit 41. The (2/3) f clock is input to the D input of each flip-flop 4a to 4n, and the internal clock 1 is input to the CK terminal of each flip-flop 4a to 4n.
~ N is input. Q of each flip-flop 4a-4n
From the output, duty comparison signals 1 to N are output. In the duty comparison circuit 41, since the difference in delay amount between the internal clocks 1 to N is constant, “H” is X in the duty comparison signal.
Assuming that Y and X are "L" and "L", duty ratio signals 1 to N are output by comparing the values of X and Y-X. FIG. 8 shows the timing waveform.

FIG. 5 is a circuit block diagram showing details of the duty adjusting section 5. The duty adjusting section 5 is composed of NAND circuits 5a to 5N, a NAND circuit 51, and an AND circuit 52. The internal clock 1 and the duty control signal 1 are input to the NAND circuit 5a, the internal clock 2 and the duty control signal 2 are input to the NAND circuit 5b, and the internal clock n is input to the NAND circuit 5n in the same manner. The outputs of the NAND circuits 5a to 5n are input to the NAND circuit 51, and the output of the NAND circuit 51 and the internal clock 1 are input to the AND circuit 52. In this way, the duty ratio of the (2/3) f clock is adjusted by the duty control signals 1 to N. FIG. 9 shows the timing waveform at this time. In FIG. 9, (2/3) f clock 17
When the duty ratio is larger than 50%, if the duty control signal Z + 1 is set to "H", the duty ratio becomes smaller and approaches 50%. When the duty ratio of the (2/3) f clock 17 is smaller than 50%, the duty ratio increases when the duty control signal Z is set to "L".
It approaches 0%. By repeating the above operation in the duty comparison circuit of the duty control unit 4, the duty ratio can be automatically adjusted.

[0012]

As described above, according to the present invention, in the encoding / decoding circuit in which the data conversion ratio is 2/3, a clock having a frequency 2/3 times that of one reference clock is derived by a logical means. Since the duty ratio is automatically adjusted, the (2/3) f clock is derived from the reference clock of the frequency 1f without using the reference clock of the frequency 2f, and the duty ratio of the clock is derived. Is adjusted regardless of the frequency and duty ratio of the reference clock, so that the encoding / decoding circuit can be easily and accurately realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a 1-7 RLL conversion circuit according to the present invention.

FIG. 2 is a circuit diagram showing details of an internal clock generator of FIG.

FIG. 3 is a circuit diagram showing details of a delay circuit section in FIG.

FIG. 4 is a circuit diagram showing details of a duty control unit in FIG.

FIG. 5 is a circuit diagram showing details of a duty adjusting unit in FIG.

FIG. 6 is a timing chart for explaining the operation of the internal clock generator of FIG.

FIG. 7 is a timing chart for explaining the operation of the delay circuit section in FIG.

FIG. 8 is a timing chart for explaining the operation of the duty control unit in FIG.

9 is a timing chart for explaining the operation of the duty adjustment unit in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Selector 2 ... Internal clock generation part 3 ... Delay circuit part 4 ... Duty control part 5 ... Duty adjustment part 6 ... Encoder / decoder 14 ... Internal clock A 15 ... Internal clocks 1-N 16 ... Duty control signals 1-N 17 … (2/3) f clock

Claims (2)

[Claims] 1. An internal clock generation means for generating an internal clock in a 1-7RLL conversion circuit, which converts or reverse-converts an unconstrained data sequence into a constrained code sequence and has a conversion ratio of 2/3. Means for deriving a clock of (2/3) frequency of the reference clock from the internal clock; duty adjusting means for adjusting the duty ratio of the clock of (2/3) frequency; and automatic adjustment of the adjustment amount of the duty ratio. A 1-7 RLL code conversion circuit comprising: 2. A means for deriving the clock of the (2/3) frequency comprises a delay circuit section for delaying the internal clock to generate N delayed internal clocks. 1. The 1-7 RLL code conversion circuit described in 1.