JPH05190687A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH05190687A JPH05190687A JP2060892A JP2060892A JPH05190687A JP H05190687 A JPH05190687 A JP H05190687A JP 2060892 A JP2060892 A JP 2060892A JP 2060892 A JP2060892 A JP 2060892A JP H05190687 A JPH05190687 A JP H05190687A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- current
- interlayer
- lower wiring
- upper wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、集積回路装置におけ
る多層配線構造の改良に関し、特に下方配線層から上方
配線層に通電される第１の層間接続部に比べて上方配線
層から下方配線層に通電される第２の層間接続部の電流
密度を小さくしたことにより第２の層間接続部でのエレ
クトロマイグレーションによる断線を防止したものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a multilayer wiring structure in an integrated circuit device, and more particularly to a wiring layer from an upper wiring layer to a lower wiring layer as compared with a first interlayer connecting portion which is energized from the lower wiring layer to the upper wiring layer. By lowering the current density of the second interlayer connecting portion that is energized to the wire, disconnection due to electromigration in the second interlayer connecting portion is prevented.
【０００２】[0002]
【従来の技術】従来、ＭＯＳ型ＬＳＩ等の集積回路装置
にあっては、図３〜４に示すような多層配線構造が採用
されていた。2. Description of the Related Art Conventionally, in an integrated circuit device such as a MOS type LSI, a multilayer wiring structure as shown in FIGS.
【０００３】図３〜４において、シリコン等の半導体基
板１０の表面を覆うシリコンオキサイド等の絶縁膜１２
の上には、下層配線層１４を介して層間絶縁膜１６が形
成される。絶縁膜１６には、所望の層間接続部１８ａ，
１８ｂに対応した接続孔が設けられ、これらの接続孔を
介して配線層１４に接続されるように絶縁膜１６上に上
方配線層１８Ａ，１８Ｂが形成される。層間接続部１８
ａ，１８ｂにそれぞれ対応した接続孔は、実質的に同一
のサイズで形成される。3 to 4, an insulating film 12 of silicon oxide or the like covering the surface of a semiconductor substrate 10 of silicon or the like.
An interlayer insulating film 16 is formed on the upper surface of the lower wiring layer 14 via the lower wiring layer 14. The insulating film 16 has a desired interlayer connection portion 18a,
Connection holes corresponding to 18b are provided, and upper wiring layers 18A and 18B are formed on the insulating film 16 so as to be connected to the wiring layer 14 through these connection holes. Interlayer connection 18
The connection holes respectively corresponding to a and 18b are formed with substantially the same size.
【０００４】[0004]
【発明が解決しようとする課題】図３〜４に示したよう
な多層配線構造について層間接続部に高温下で高密度の
電流を流すことによりエレクトロマイグレーション耐性
の評価を行なったところ、断線不良の殆どは電流Ｉが上
方配線層から下方配線層に流れる１８ａ等の層間接続部
で生じていることが判明した。すなわち、層間接続部１
８ａ，１８ｂに対応する同一サイズの接続孔では、上層
から下層に電流が流れる接続孔の方がエレクトロマイグ
レーション耐性が低く、断線しやすいことがわかった。The electromigration resistance of the multilayer wiring structure as shown in FIGS. 3 to 4 was evaluated by applying a high density current to the interlayer connection at high temperature. It was found that most of the current I is generated in the interlayer connection portion such as 18a that flows from the upper wiring layer to the lower wiring layer. That is, the interlayer connection portion 1
It was found that among the contact holes of the same size corresponding to 8a and 18b, the contact holes through which the current flows from the upper layer to the lower layer have lower electromigration resistance and are easily broken.
【０００５】この発明の目的は、層間接続部でのエレク
トロマイグレーションによる断線を防止した新規な集積
回路装置を提供することにある。An object of the present invention is to provide a novel integrated circuit device which prevents disconnection due to electromigration in an interlayer connection portion.
【０００６】[0006]
【課題を解決するための手段】この発明は、下方配線層
から上方配線層に所定の電流が流れる１又は複数の第１
の層間接続部と、上方配線層から下方配線層に前記所定
の電流又はこの電流と等しい大きさの電流が流れる１又
は複数の第２の層間接続部とをそなえた集積回路装置に
おいて、前記第１の層間接続部の総面積に基づく電流密
度よりも前記第２の層間接続部の総面積に基づく電流密
度を小さく設定したことを特徴とするものである。According to the present invention, a predetermined current flows from a lower wiring layer to an upper wiring layer.
An inter-layer connection part, and one or a plurality of second inter-layer connection parts through which the predetermined current or a current equal in magnitude to the predetermined current flows from the upper wiring layer to the lower wiring layer. The current density based on the total area of the second interlayer connecting portion is set to be smaller than the current density based on the total area of the first interlayer connecting portion.
【０００７】この明細書において、第１又は第２の層間
接続部に関して総面積とは、層間接続部が１つであれば
１つの層間接続部の面積のことであるが、層間接続部が
複数であれば総ての層間接続部の面積の合計のことであ
る。第１及び第２の層間接続部については、いずれも単
数、いずれも複数、いずれか一方が単数で他方が複数の
３種類の組合せが考えられるが、いずれの組合せを採用
してもよい。In this specification, the total area of the first or second interlayer connecting portions means the area of one interlayer connecting portion if there is one interlayer connecting portion. If so, it means the total area of all interlayer connecting portions. Regarding the first and second interlayer connection parts, three types of combinations are conceivable, all of which are singular, all of which are plural, one of which is singular and the other of which is plural, but any combination may be adopted.
【０００８】[0008]
【作用】この発明の構成によれば、第２の層間接続部の
エレクトロマイグレーション耐性が低い点に着目して第
２の層間接続部の総面積に基づく電流密度を第１の層間
接続部の総面積に基づく電流密度より小さくするように
したので、第２の層間接続部ではエレクトロマイグレー
ション耐性が向上し、断線を防止することができる。According to the structure of the present invention, attention is paid to the fact that the electromigration resistance of the second interlayer connecting portion is low, and the current density based on the total area of the second interlayer connecting portion is calculated as the total current of the first interlayer connecting portion. Since the current density is set to be smaller than the area-based current density, electromigration resistance is improved in the second interlayer connection portion, and disconnection can be prevented.
【０００９】すなわち、エレクトロマイグレーション耐
性は、電流密度をｉとし、ｎを１〜３とすると、ｉ-nに
比例することがわかっている。一例としてｎ＝２（実験
値）とし、電流密度を１／２（総面積を２倍）とすれ
ば、エレクトロマイグレーション耐性を４倍向上させる
ことができる。That is, it has been known that the electromigration resistance is proportional to i −n when the current density is i and n is 1 to 3. As an example, if n = 2 (experimental value) and the current density is 1/2 (total area is twice), electromigration resistance can be improved four times.
【００１０】[0010]
【実施例】図１は、この発明の一実施例による集積回路
装置の多層配線構造を示すものである。1 shows a multilayer wiring structure of an integrated circuit device according to an embodiment of the present invention.
【００１１】図１において、下方配線層２４Ａと上方配
線層２８Ａとの間には図４で示したと同様に層間絶縁膜
に設けた接続孔に対応して層間接続部２８ａが形成され
ている。また、下方配線層２４Ｂと上方配線層２８Ｂと
の間にも層間絶縁膜に設けた接続孔に対応して層間接続
部２８ｂが形成されている。In FIG. 1, an interlayer connecting portion 28a is formed between the lower wiring layer 24A and the upper wiring layer 28A so as to correspond to the connecting hole formed in the interlayer insulating film, as shown in FIG. Further, an interlayer connection portion 28b is also formed between the lower wiring layer 24B and the upper wiring layer 28B so as to correspond to the connection hole formed in the interlayer insulating film.
【００１２】下方配線層２４Ａ及び２４Ｂは、図４の配
線層１４と同様に連続したものであってもよいし、ある
いは別々のものであってもよい。また、下方配線層２４
Ａ及び２４Ｂが別々のものであるときは、上方配線層２
８Ａ及び２８Ｂは連続したものであってもよいし、ある
いは別々のものであってもよい。いずれにしても、層間
接続部２８ｂには下方配線層２４Ｂから上方配線層２８
Ｂに向けて直流電流又はパルス電流等の所定の電流Ｉが
流れ、層間接続部２８ａには上方配線層２８Ａから下方
配線層２４Ａに向けて電流Ｉ又はこの電流と等しい大き
さの電流が流れるものとする。The lower wiring layers 24A and 24B may be continuous as in the wiring layer 14 of FIG. 4, or may be separate layers. In addition, the lower wiring layer 24
When A and 24B are different, the upper wiring layer 2
8A and 28B may be continuous or separate. In any case, the lower wiring layer 24B to the upper wiring layer 28 are formed in the interlayer connection portion 28b.
A predetermined current I such as a direct current or a pulse current flows toward B, and a current I or a current equal in magnitude to this current flows from the upper wiring layer 28A to the lower wiring layer 24A in the interlayer connection portion 28a. And
【００１３】このような状況下において、層間接続部２
８ａ及び２８ｂが同一面積であれば、層間接続部２８ｂ
より層間接続部２８ａの方がエレクトロマイグレーショ
ン耐性が低いことは前述した通りである。そこで、この
実施例では、層間接続部２８ｂの面積（ａ×ｂ）よりも
層間接続部２８ａの面積（Ａ×Ｂ）を大きくして層間接
続部２８ａの電流密度を下げることによりエレクトロマ
イグレーション耐性を向上させている。Under such circumstances, the interlayer connecting portion 2
If 8a and 28b have the same area, the interlayer connecting portion 28b
As described above, the interlayer connection portion 28a has lower electromigration resistance. Therefore, in this embodiment, the area (A × B) of the interlayer connecting portion 28a is made larger than the area (a × b) of the interlayer connecting portion 28b to reduce the current density of the interlayer connecting portion 28a, thereby improving electromigration resistance. Is improving.
【００１４】図２は、この発明の他の実施例による集積
回路装置の多層配線構造を示すもので、この例の特徴は
下方及び上方の配線層間に多数の層間接続部を設けたこ
とである。FIG. 2 shows a multilayer wiring structure of an integrated circuit device according to another embodiment of the present invention, which is characterized in that a large number of interlayer connecting portions are provided between lower and upper wiring layers. ..
【００１５】図２において、下方配線層３４Ａと上方配
線層３８Ａとの間には層間絶縁膜に設けた多数の接続孔
に対応して多数の層間接続部３８ａが形成されている。
また、下方配線層３４Ｂと上方配線層３８Ｂとの間にも
層間絶縁膜に設けた多数の接続孔に対応して層間接続部
３８ｂが形成されている。In FIG. 2, a large number of interlayer connecting portions 38a are formed between the lower wiring layer 34A and the upper wiring layer 38A corresponding to the large number of connecting holes formed in the interlayer insulating film.
Further, between the lower wiring layer 34B and the upper wiring layer 38B, interlayer connection portions 38b are formed corresponding to a large number of connection holes formed in the interlayer insulating film.
【００１６】下方配線層３４Ａ及び３４Ｂあるいは上方
配線層３８Ａ及び３８Ｂについて連続又は別個のいずれ
の構成も採用できることは図１の場合と同様である。ま
た、層間接続部３８ｂには下方配線層３４Ｂから上方配
線層３８Ｂに向けて電流Ｉが流れ、層間接続部３８ａに
は上方配線層３８Ａから下方配線層３４Ａに電流Ｉ又は
この電流と等しい大きさの電流が流れるものとする。As in the case of FIG. 1, the lower wiring layers 34A and 34B or the upper wiring layers 38A and 38B can be either continuous or separate. A current I flows from the lower wiring layer 34B to the upper wiring layer 38B in the interlayer connection portion 38b, and a current I from the upper wiring layer 38A to the lower wiring layer 34A in the interlayer connection portion 38a or a magnitude equal to this current. It is assumed that the current flows.
【００１７】この実施例では、総ての層間接続部３８ｂ
の面積の合計よりも総ての層間接続部３８ａの面積の合
計を大きくして層間接続部３８ａの総面積に基づく電流
密度を下げることによりエレクトロマイグレーション耐
性を向上させている。In this embodiment, all interlayer connection parts 38b are formed.
The electromigration resistance is improved by increasing the total area of all the interlayer connecting portions 38a to be smaller than the total area of the above and lowering the current density based on the total area of the interlayer connecting portions 38a.
【００１８】図１又は２の実施例において、層間接続部
２８ａ又は３８ａの面積をどの程度大きくするかは、エ
レクトロマイグレーション耐性をどの程度大きくするか
に依存している。すなわち、エレクトロマイグレーショ
ン耐性は、前述したようにｉ-nに比例するから、例えば
ｎ＝２としてエレクトロマイグレーション耐性を１０倍
向上させたいときは、電流密度を１０の平方根分の１に
低減すればよい。換言すれば、層間接続面積を１０の平
方根倍すればよく、図１の場合は層間接続部２８ａの面
積（Ａ×Ｂ）を、（ａ×ｂ）×（１０の平方根）とすれ
ばよい。また、図２の場合は、層間接続部３８ａ及び３
８ｂを同一サイズとし且つそのうちの１つの面積をＳ
［ｃｍ2 ］とすれば、層間接続部３８ｂの総面積を１０
Ｓ［ｃｍ2］とし、層間接続部３８ａの総面積を３３Ｓ
［ｃｍ2 ］とすればよい。この場合、層間接続部３８ｂ
の電流密度を１とすれば、層間接続部３８ａの電流密度
は約０．３となる。In the embodiment of FIG. 1 or 2, how large the area of the interlayer connection 28a or 38a is depends on how much the electromigration resistance is increased. That is, since the electromigration resistance is proportional to i −n as described above, when it is desired to improve the electromigration resistance 10 times by setting n = 2, for example, the current density may be reduced to 1 / square root of 10. .. In other words, the inter-layer connection area may be multiplied by the square root of 10, and in the case of FIG. 1, the area (A × B) of the inter-layer connection portion 28a may be (ax × b) × (square root of 10). Further, in the case of FIG. 2, the interlayer connecting portions 38a and 3
8b have the same size and one of them has an area of S
If [cm 2 ] is set, the total area of the interlayer connecting portion 38b is 10
S [cm 2 ] and the total area of the interlayer connection 38a is 33S.
[Cm 2 ] may be used. In this case, the interlayer connection portion 38b
If the current density of 1 is 1, the current density of the inter-layer connection portion 38a is about 0.3.
【００１９】図５は、ｎ＝２とした場合において目標と
するエレクトロマイグレーション耐性（ＥＭ耐性）と必
要とする層間接続面積（相対値）との関係を示すもの
で、このグラフを参考にして層間接続部を設計すること
ができる。なお、図５において、×印の個所は、図３〜
４の従来例に相当するものである。FIG. 5 shows the relationship between the target electromigration resistance (EM resistance) and the required interlayer connection area (relative value) when n = 2. The connection can be designed. In addition, in FIG. 5, the portions marked with “X” are shown in FIG.
4 corresponds to the conventional example.
【００２０】[0020]
【発明の効果】以上のように、この発明によれば、下方
配線層から上方配線層に通電される第１の層間接続部の
総面積に基づく電流密度よりも上方配線層から下方配線
層に通電される第２の層間接続部の総面積に基づく電流
密度を小さくして第２の層間接続部でのエレクトロマイ
グレーションによる断線を防止するようにしたので、信
頼性の高い集積回路装置を実現できる効果が得られるも
のである。As described above, according to the present invention, the current density from the upper wiring layer to the lower wiring layer is higher than the current density based on the total area of the first interlayer connecting portions energized from the lower wiring layer to the upper wiring layer. Since the current density based on the total area of the energized second interlayer connection portion is reduced to prevent disconnection due to electromigration in the second interlayer connection portion, a highly reliable integrated circuit device can be realized. The effect can be obtained.
【図１】 この発明の一実施例による配線構造を示す基
板上面図である。FIG. 1 is a top view of a substrate showing a wiring structure according to an embodiment of the present invention.
【図２】 この発明の他の実施例による配線構造を示す
基板上面図である。FIG. 2 is a substrate top view showing a wiring structure according to another embodiment of the present invention.
【図３】 従来の配線構造の一例を示す基板上面図であ
る。FIG. 3 is a substrate top view showing an example of a conventional wiring structure.
【図４】 図３のＸ−Ｘ’線に沿う基板断面図である。FIG. 4 is a cross-sectional view of the substrate taken along the line X-X ′ of FIG.
【図５】 目標とするＥＭ耐性と必要とする層間接続面
積との関係を示すグラフである。FIG. 5 is a graph showing a relationship between a target EM resistance and a required interlayer connection area.
２４Ａ，２４Ｂ，３４Ａ，３４Ｂ：下方配線層、２８
Ａ，２８Ｂ，３８Ａ，３８Ｂ：上方配線層、２８ａ，２
８ｂ，３８ａ，３８ｂ：層間接続部。24A, 24B, 34A, 34B: lower wiring layer, 28
A, 28B, 38A, 38B: upper wiring layer, 28a, 2
8b, 38a, 38b: interlayer connecting portions.
Claims (1)
が流れる１又は複数の第１の層間接続部と、上方配線層
から下方配線層に前記所定の電流又はこの電流と等しい
大きさの電流が流れる１又は複数の第２の層間接続部と
をそなえた集積回路装置において、 前記第１の層間接続部の総面積に基づく電流密度よりも
前記第２の層間接続部の総面積に基づく電流密度を小さ
く設定したことを特徴とする集積回路装置。1. A one or a plurality of first interlayer connecting portions through which a predetermined current flows from a lower wiring layer to an upper wiring layer, and the predetermined current flowing from the upper wiring layer to the lower wiring layer or a magnitude equal to this current. In an integrated circuit device having one or a plurality of second interlayer connecting parts through which a current flows, based on a total area of the second interlayer connecting parts rather than a current density based on a total area of the first interlayer connecting parts. An integrated circuit device having a small current density.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2060892A JPH05190687A (en) | 1992-01-09 | 1992-01-09 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2060892A JPH05190687A (en) | 1992-01-09 | 1992-01-09 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05190687A true JPH05190687A (en) | 1993-07-30 |
Family
ID=12031981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2060892A Pending JPH05190687A (en) | 1992-01-09 | 1992-01-09 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05190687A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004006328A1 (en) * | 2002-07-09 | 2004-01-15 | Sony Corporation | Semiconductor device and method for manufacturing same |
| JP2004158846A (en) * | 2002-10-18 | 2004-06-03 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit and method of manufacturing the same |
-
1992
- 1992-01-09 JP JP2060892A patent/JPH05190687A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004006328A1 (en) * | 2002-07-09 | 2004-01-15 | Sony Corporation | Semiconductor device and method for manufacturing same |
| US7038317B2 (en) | 2002-07-09 | 2006-05-02 | Sony Corporation | Semiconductor device and method of manufacturing same |
| JP2004158846A (en) * | 2002-10-18 | 2004-06-03 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit and method of manufacturing the same |
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