JPH05189229A - Microprocessor - Google Patents

Abstract

PURPOSE:To take out internal information during the execution of a program to an external part without switching a monitor program and a context by providing a microprogram memory and storing a microprogram. CONSTITUTION:Codes designating registers transferring the address (xyz) of an instruction immediately before internal information is transferred to a transfer address register 15, and the head address of an internal information transfer destination to a register list register 17 are respectively written into a PC brake pointer 9 by the execution of the instruction. When a brake hit signal 12 is inputted, a micro instruction entry control block 2 sets the micro instruction entry code of an internal information transfer sequence 13 in a micro instruction entry pointer 4. Thus, the internal information transfer sequence 13 in The micro program memory 5 is started after the execution of the address (xyz) is completed, and an internal information transfer processing is executed. The execution of the original program after transfer terminates is continued.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a program development support function,
In particular, it relates to a microprocessor having a micro program memory.

[0002]

2. Description of the Related Art In developing a program for a microprocessor, information inside the microprocessor during execution of the program may be taken out. Here, the information inside the microprocessor is context information such as contents of various registers inside the microprocessor.

FIG. 5 is a block diagram for explaining the operation of extracting information inside the microprocessor during program execution to the outside in a conventional microprocessor. In the figure, 1 is a microinstruction entry code output from an instruction decoder (not shown), 2 is a microinstruction entry control block, and 3 is a constant register holding a microinstruction entry code for interrupt processing. Four
Represents a micro instruction entry pointer, 5 represents a micro program memory, and 6 represents an interrupt processing sequence described in the micro program memory 5. 7 is a control signal for instruction execution, 8 is an instruction execution block, 9 is a PC break pointer, 10 is an operand break pointer, 11
Is a break point detection block, and 12 is a break hit signal.

FIG. 6 is a schematic diagram showing an example of an instruction execution sequence for extracting the internal information of the microprocessor during program execution to the outside in the conventional microprocessor. In the figure, 21 and 22 are instructions (1) and (2) of the user program, 27 and 30 are instructions for setting a PC breakpoint, 28 is an interrupt process, and 29 is a monitor program.

Next, the operation will be described with reference to FIGS. 5 and 6. Here, it is assumed that the microprocessor takes out the internal information of the microprocessor immediately after the execution of the instruction (1) 21 at the address (A + m + 1) is completed. First, by executing the instruction (a) 27 at the address (A), (A + m + 1) is written in the PC break pointer 17. When the execution of the user program progresses and the microprocessor fetches the instruction (1) 21 at the address (A + m + 1), the value of the PC break pointer 17 and the address of the fetched instruction match, so the execution of the instruction (1) 21 When started, the breakpoint detection block 11 inputs a break hit signal 12 to the microinstruction entry control block 2. The micro-instruction entry control block 2 normally sets the micro-instruction entry code 1 output from an instruction decoder (not shown) in the micro-instruction entry pointer 4 after the execution of the previously executed instruction is completed. However, when the break hit signal 12 is input, the microinstruction entry code of the interrupt processing sequence 6 stored in the constant register 3 is set in the microinstruction entry pointer 4 after the execution of the previously executed instruction is completed. Therefore, (A + m +
1) Interrupt processing 2 after execution of instruction (1) 21 at address is completed
8 is started. By this interrupt processing 28, the user program currently being executed is interrupted and the monitor program 2
9 is activated. The monitor program 29 fetches the contents of various registers in the microprocessor into an external memory (not shown), and when the monitor program 29 ends, the interrupt process 28 ends and the user program returns (A
The instruction (2) 22 at the address + m + 2) is resumed.

In order to retrieve the internal information of the microprocessor after the execution of the instruction to be executed subsequent to the instruction (2) 22 is completed, a monitor instruction (b) 30 is provided in the monitor program 29 and the PC break pointer 9 is provided. The value of must be rewritten.

The above operation has been described for the case where the breakpoint is specified by the value of the program counter, but the breakpoint may be specified by the address of the operand. In this case, an instruction to write the address of the operand to the operand break pointer 10 is executed instead of the instruction (a) 27 at the address (A). When the microprocessor accesses the operand at the address stored in the operand break pointer 10 by executing the user program, the breakpoint detection block 11 sends the break hit signal 12 to the micro instruction entry during the execution of the instruction that accessed the operand. Input to control block 2. Therefore, an interrupt is generated after the execution of the instruction that has accessed the operand of the address stored in the operand break pointer 10 is completed, and thereafter, the same operation as when the breakpoint is specified by the value of the program counter is performed.

[0008]

As described above, there is a problem that a monitor program is required to retrieve internal information during execution of a program by a conventional microprocessor, and a context to the monitor program by an interrupt occurs. There is a problem that it takes time because of the switching, and the real-time property is impaired. Further, it is necessary to rewrite the contents of the PC break pointer, the operand break pointer, etc. by executing the instruction. For example, when the information inside the microprocessor is taken out after the execution of each of the plurality of instructions is completed, it is necessary to rewrite the PC break pointer every time. There was a problem called.

The present invention has been made in order to solve such a problem, and it is possible to take out internal information during program execution to the outside without a monitor program and context switching, and to register a breakpoint for executing an instruction. An object of the present invention is to obtain a microprocessor which can take out internal information during program execution to the outside by an external signal without rewriting.

[0010]

In a microprocessor according to the present invention, a microprogram memory is first provided to store the microprogram, the microprocessor executes an instruction at a specified address, and then the microprocessor executes in accordance with the microprogram. The internal information indicating the above situation is transferred to the outside, and after this transfer is completed, the microprocessor is provided with a means for returning to the instruction sequence of the address executed before the external transfer. Further, in the invention of claim 2, the microprogram is stored in the memory, and further an internal information output request terminal is provided, and when the output request signal is received by this, the microprocessor executes the instruction being executed at that time, and then the microprogram is executed. According to the above, there is provided means for transferring the internal information indicating the status being executed by the microprocessor to the outside, and after completing the transfer, returning to the instruction sequence of the address executed by the microprocessor before the external transfer.

[0011]

The microprocessor according to the present invention transfers the internal information to the outside by the microprogram after executing the instruction of the predetermined address or the operand of the address. Alternatively, when the internal information output request signal is received, the internal information is transferred to the outside by the microprogram after the execution of the instruction currently being executed by the microprocessor.

[0012]

【Example】

Example 1. FIG. 1 is a block diagram for explaining an operation of extracting information inside the microprocessor during execution of a program to the outside in one embodiment of the microprocessor according to the present invention. In the figure, 1 to 12 indicate the same or corresponding parts as in the conventional example of FIG. Reference numeral 13 is a sequence for transferring the microprocessor internal information described in the micro program memory 5 to an external memory (not shown). Reference numeral 14 is a constant register for holding the micro instruction entry code of sequence 13 for transferring the microprocessor internal information to an external memory (not shown), and 15 is a transfer destination address register for holding the transfer destination address of the microprocessor internal information. Reference numeral 16 is a decrementer, and 17 is a register list register for designating registers inside the microprocessor to be transferred to an external memory (not shown).

FIG. 2 is a schematic diagram showing an example of an instruction execution sequence for extracting the internal information of the microprocessor during program execution to the outside in the embodiment of the microprocessor according to the present invention shown in FIG. In the figure, 21,
Reference numeral 22 denotes the same or corresponding portion as the conventional example shown in FIG. 26a is a process for transferring the information inside the microprocessor provided by the present invention to an external memory (not shown).

Next, the operation will be described with reference to FIGS. 1 and 2. Similar to the conventional example, here, the microprocessor corresponds to the instruction (1) 21 and the address (A + m + 1) of the address (xyz) corresponding to the address (A + m + 1) of the conventional example (x).
It is assumed that the instruction (2) 22 at the address yz + 1 is sequentially executed and the internal information of the microprocessor immediately after the completion of the execution of the instruction (1) 21 at the address (xyz) is taken out to the outside. First, the PC is executed in advance by executing an instruction (not shown).
(Xyz) is set to the break pointer 9, the start address of the transfer destination of the microprocessor internal information is set to the transfer destination address register 15, and the code that specifies the register inside the microprocessor to be transferred to the external memory (not shown) is set to the register list register 17. Write in each. The operation until the break hit signal 12 is input to the micro instruction entry control block 2 is the same as that of the conventional example. First, the micro instruction entry control block 2
Normally sets the microinstruction entry code 1 output from an instruction decoder (not shown) in the microinstruction entry pointer 4 after the execution of the previously executed instruction is completed. When the break hit signal 12 is input, the previously executed instruction is executed and then the microinstruction entry code of the next instruction to be executed is waited. Then, the microinstruction entry code of sequence 13 for transferring the microprocessor internal information to an external memory (not shown) is set in the microinstruction entry pointer 4. Therefore, after the execution of the instruction (1) 21 at the address (xyz) is completed, the sequence 13 for transferring the microprocessor internal information to the external memory (not shown) is activated, and the processing 26a for transferring the information inside the microprocessor to the external memory (not shown). Is done.

Here, in the sequence 13 for transferring the microprocessor internal information to the external memory (not shown), the contents of the register inside the microprocessor specified by the register list register 17 are transferred to the external memory.
As the transfer address, the value held in the transfer destination address register 15 is used. The decrementer 16 decrements the value of the transfer destination address register 15 each time the transfer of one word is completed. Therefore, the contents of the registers inside the microprocessor designated by the register list register 17 are sequentially transferred from the address previously written in the transfer destination address register 15 toward the lower address side. When the processing 26a for transferring the information inside the microprocessor to an external memory (not shown) is completed,
The microinstruction entry control block 2 sets the microinstruction entry code of the instruction (2) at the waiting address (xyz + 1) in the microinstruction entry pointer 4, and the execution of the instruction (2) 22 is started.

The above operation has been described for the case where the breakpoint is specified by the value of the program counter, but there are cases where the breakpoint is specified by the address of the operand. In this case, first, when an operand address is written in the operand break pointer 10 by executing an instruction (not shown) in advance, the breakpoint detection block 11 sends a break hit signal 12 to the micro instruction entry control block by the same operation as in the conventional example. Enter in 2. Therefore, an interrupt is generated after the execution of the instruction that has accessed the operand of the address stored in the operand break pointer 10 is completed, and thereafter, the same operation as in the case where the breakpoint is specified by the value of the program counter is performed.

Embodiment 2. FIG. 3 is a block diagram for explaining the operation of the microprocessor according to the second embodiment of the present invention to take out information inside the microprocessor during execution of a program to the outside. In the figure, 1 to 17 indicate the same or corresponding parts as in the first embodiment of FIG. Reference numeral 31 is an internal information output request signal provided in this embodiment, and 32 is a timing block.

FIG. 4 is a schematic diagram showing an example of an instruction execution sequence for extracting the internal information of the microprocessor executing the program to the outside in the microprocessor according to this embodiment shown in FIG. In the figure, 20 to 25 are instructions of a user program, and 26a to 26c are processes for transferring internal information of the microprocessor provided by the present invention to an external memory (not shown).

Next, the operation will be described with reference to FIGS. 3 and 4. Here, it is assumed that the internal information of the microprocessor immediately after the completion of execution of each instruction from the instruction (1) 21 at the address (A + m + 1) to the instruction (n) 23 at the address (A + m + n) is taken out. First, by executing an instruction (not shown), a transfer destination address of the microprocessor internal information is transferred to the transfer destination address register 15, and a code that specifies a register inside the microprocessor to be transferred to an external memory (not shown) is transferred to the register list register 17. Write in each. Until the execution of the instruction (0) 20 at the address (A + m), the internal information of the microprocessor is not fetched to the outside, so the internal information output request signal 11 is not inputted from the outside. In this case, the microinstruction entry control block 2 sets the microinstruction entry code 1 output from the decoder (not shown) in the microinstruction entry pointer 4 after the execution of the previously executed instruction is completed. Therefore, each instruction is sequentially executed in the order of addresses.

Instruction (1) at address (A + m + 1)
With regard to No. 21, since the internal information of the microprocessor is taken out after the execution is completed, the address (A + m + 1)
When fetching the instruction (1) 21 at the address, the internal information output request signal 11 is input from the outside. The internal information output request signal 11 input from the outside is input to the timing block 32, and the timing block 10 receives the address (A + m +
1) When the execution of the instruction (1) 21 at the address is started, the break hit signal 12 is input to the micro instruction entry control block 2. When the break hit signal 12 is input, the microinstruction entry control block 2 waits for the microinstruction entry code of the instruction to be executed next. Then, after executing the previously executed instruction, the microinstruction entry code of the sequence 12 to be transferred to the external memory stored in the constant register 14 is set in the microinstruction entry pointer 4. Therefore, after the execution of the instruction (1) 21 at the address (A + m + 1) is completed, the sequence 13 for transferring the microprocessor internal information to the external memory (not shown) is activated, and the processing 26a for transferring the internal information to the external memory is performed. Here, in the sequence 13 for transferring the microprocessor internal information to the external memory, the contents of the register inside the microprocessor specified by the register list register 17 are transferred to the external memory. As the transfer address, the value held in the transfer destination address register 15 is used. The decrementer 16 decrements the value of the transfer destination address register 15 each time the transfer of one word is completed. Therefore, the contents of the registers inside the microprocessor designated by the register list register 17 are sequentially transferred from the address previously written in the transfer destination address register 15 toward the lower address side. When the processing 26a for transferring the internal information to the external memory is completed, the microinstruction entry control block 2 has been waiting (A + m +).
2) The micro instruction entry code of the instruction (2) 22 at the address is set in the micro instruction entry pointer 4, and the execution of the instruction (2) 22 is started.

Instruction (1) at address (A + m + 1)
21 to instruction (n) 23 at address (A + m + n)
When the internal information of the microprocessor immediately after the completion of execution of each instruction is fetched to the outside, if the internal information output request signal 11 is input from the outside every time the instruction is fetched, the microprocessor is executed each time the execution of each instruction is completed. Internal information of will be transferred to the external memory. Also in this transfer, the contents of the register inside the microprocessor designated by the register list register 17 are transferred to the external memory. The transfer address is the transfer destination address register 15
The value held in is used. Decrementer 16 is 1
The value of the transfer destination address register is decremented each time the word transfer is completed. Therefore, the addresses written in advance in the transfer destination address register 15 are headed toward the low address side in order of the register list register 1
The contents of the register inside the microprocessor designated by 7 are transferred. Instruction (n + 1) 24 at address (A + m + n + 1) and address (A + m + n + 2)
If it is unnecessary to transfer the internal information of the microprocessor to the external memory after the execution of the instruction (n + 2) 25 at the address is completed, the instruction (n + 1) at the address (A + m + n + 1)
24 and instruction (n +) at address (A + m + n + 2)
2) When fetching 25, if the internal information output request signal 11 is not input from the outside, the instruction (n + 1) 24 at the address (A + m + n + 1) and the address (A + m + n +)
2) After the execution of the instruction (n + 2) 25 at the address is completed, the internal information of the microprocessor is not transferred to the external memory.

Although the internal information output request signal 11 is input at the time of instruction fetch in the second embodiment, the internal information output request may be input at the time of operand access. In this case, the internal information output request signal 31
Is input to the timing block 32, the break hit signal 1 is output during execution of the instruction that accessed the operand.
2 into microinstruction entry control block 2. After that, the same operation as in the case of inputting the internal information output request signal 31 at the time of instruction fetch is performed.

Other Embodiments The decrementer 15 can also obtain the same effect by using an incrementer.

In each of the above embodiments, there is no monitor program,
Let's quantitatively evaluate the advantage of being able to transfer internal information to the outside without interrupt processing. Assume the following: The number of internal registers read out to the outside is 16 general-purpose registers.
It is read by the re Multiple instruction and has 23 control registers. This is the Store from Contro.
It is read by the l Space instruction. First, in the conventional example, the number of bus accesses is 67 times as follows. On the other hand, the number of times of bus access required in the case of the present invention may be 39 times in total. Note that the number of instruction fetches in the above-described conventional example is the minimum, and may increase more than this. Even if the internal processing of the CPU is ignored in this way, there is such a difference, but considering the internal processing such as interrupt preprocessing, return processing, and internal processing when each instruction is executed, the difference in execution time is It is thought to spread. Further, in a CPU that performs pipeline processing, the pipeline is flushed during interrupt processing, so the difference in execution time further widens.

[0025]

As described above, according to the present invention, the microprogram is stored in the microprogram memory, and after the microprocessor executes the instruction at the specified address, the internal state indicating the status executed by the microprocessor is displayed according to the microprogram. Since the information is transferred to the outside and the processing is returned to the original after this transfer, or the internal information output request terminal is provided and the same operation is performed when the output request signal comes in, the monitor It is possible to take out internal information during program execution to the outside without a program and without interrupt processing, which has the effect of shortening the processing time.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is an execution sequence diagram for explaining the operation of the embodiment of FIG.

FIG. 3 is a configuration block diagram showing another embodiment of the present invention.

FIG. 4 is an execution sequence diagram for explaining the operation of the embodiment of FIG.

FIG. 5 is a configuration diagram in the case of transferring internal information of a conventional microprocessor to the outside.

FIG. 6 is an execution sequence diagram illustrating the operation of FIG.

[Explanation of symbols]

 1 Microinstruction entry code 2 Microinstruction entry control block 3,14 Constant register 4 Microinstruction entry pointer 5 Microprogram memory 8 Instruction execution block 9 PC break pointer 10 Operand break pointer 11 Breakpoint detection block 12 Break hit signal 13 Internal information transfer Sequence 15 Transfer destination address register 16 Decrementer 17 Register list register 20-25 User program instruction 26a-26c Internal information transfer processing 31 Internal information output request signal 32 Timing block

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[Procedure amendment]

[Submission date] April 15, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010]

In a microprocessor according to the present invention, a microprogram memory is first provided to store the microprogram, the microprocessor executes an instruction at a specified address, and then the microprocessor executes in accordance with the microprogram. The internal information indicating the above situation is transferred to the outside, and after this transfer is completed, the microprocessor is provided with a means for returning to the instruction sequence of the address executed before the external transfer. According to the second aspect of the present invention, the microprogram is stored in the memory, and an internal information output request terminal is further provided so that the instruction fetch or the operand access is performed.
At the time of access, the internal information output request pin receives an output request signal.
Then, the microprocessor is
The instruction that was performing the instruction or operand access
After that, according to this microprogram , the internal information indicating the condition that the microprocessor was executing is transferred to the outside, and after this transfer is completed, the microprocessor returns to the instruction sequence of the address that was being executed before the external transfer. Provided.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

The microprocessor according to the present invention has a predetermined
The instruction at the address or the operand at the given address
After executing the instruction to be used, the microprogram transfers the internal information to the outside. Alternatively, the internal information output request signal
Received at instruction fetch or operand access
Then, the microprocessor is
Or use the operand accessed at that time
After the execution of the instruction is completed, the microprogram transfers the internal information to the outside.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Next, the operation will be described with reference to FIGS. 1 and 2. Similar to the conventional example, here, the microprocessor corresponds to the instruction (1) 21 and the address (A + m + 1) of the address (xyz) corresponding to the address (A + m + 1) of the conventional example (x).
It is assumed that the instruction (2) 22 at the address yz + 1 is sequentially executed and the internal information of the microprocessor immediately after the completion of the execution of the instruction (1) 21 at the address (xyz) is taken out to the outside. First, the PC is executed in advance by executing an instruction (not shown).
(Xyz) is set to the break pointer 9, the start address of the transfer destination of the microprocessor internal information is set to the transfer destination address register 15, and the code that specifies the register inside the microprocessor to be transferred to the external memory (not shown) is set to the register list register 17. Write in each. The operation until the break hit signal 12 is input to the micro instruction entry control block 2 is the same as that of the conventional example. First, the micro instruction entry control block 2
Normally sets the microinstruction entry code 1 output from an instruction decoder (not shown) in the microinstruction entry pointer 4 after the execution of the previously executed instruction is completed. When the break hit signal 12 is input, the previously executed instruction is executed and then the microinstruction entry code of the next instruction to be executed is waited. Then, the microinstruction entry code of sequence 13 for transferring the microprocessor internal information to an external memory (not shown) is set in the microinstruction entry pointer 4. Therefore, after the execution of the instruction (1) 21 at the address (xyz) is completed, the sequence 13 for transferring the microprocessor internal information to the external memory (not shown) is activated, and the processing 26a for transferring the information inside the microprocessor to the external memory (not shown). Is done.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

The above operation has been described for the case where the breakpoint is specified by the value of the program counter, but there are cases where the breakpoint is specified by the address of the operand. In this case, first, when an operand address is written in the operand break pointer 10 by executing an instruction (not shown) in advance, the breakpoint detection block 11 sends a break hit signal 12 to the micro instruction entry control block by the same operation as in the conventional example. Enter in 2. Therefore, after the execution of the instruction that accessed the operand of the address stored in the operand break pointer 10 is completed , the value of the program counter becomes
Similar to specifying more breakpoints, micro
Transfers processor internal information to external memory (not shown)
Processing is performed. After that, perform the above operand access
Execution starts from the instruction to be executed next to the executed instruction.
It

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

Instruction (1) at address (A + m + 1)
With regard to No. 21, since the internal information of the microprocessor is taken out after the execution is completed, the address (A + m + 1)
When fetching the instruction (1) 21 at the address, the internal information output request signal 11 is input from the outside. The internal information output request signal 11 input from the outside is input to the timing block 32 , and the timing block 32 receives the address (A + m +
1) When the execution of the instruction (1) 21 at the address is started, the break hit signal 12 is input to the micro instruction entry control block 2. When the break hit signal 12 is input, the microinstruction entry control block 2 waits for the microinstruction entry code of the instruction to be executed next. Then, after executing the previously executed instruction, the microinstruction entry code of the sequence 12 to be transferred to the external memory stored in the constant register 14 is set in the microinstruction entry pointer 4. Therefore, after the execution of the instruction (1) 21 at the address (A + m + 1) is completed, the sequence 13 for transferring the microprocessor internal information to the external memory (not shown) is activated, and the processing 26a for transferring the internal information to the external memory is performed. Here, in the sequence 13 for transferring the microprocessor internal information to the external memory, the contents of the register inside the microprocessor specified by the register list register 17 are transferred to the external memory. As the transfer address, the value held in the transfer destination address register 15 is used. The decrementer 16 decrements the value of the transfer destination address register 15 each time the transfer of one word is completed. Therefore, the contents of the registers inside the microprocessor designated by the register list register 17 are sequentially transferred from the address previously written in the transfer destination address register 15 toward the lower address side. When the processing 26a for transferring the internal information to the external memory is completed, the microinstruction entry control block 2 has been waiting (A + m +).
2) The micro instruction entry code of the instruction (2) 22 at the address is set in the micro instruction entry pointer 4, and the execution of the instruction (2) 22 is started.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction content]

In each of the above embodiments, there is no monitor program,
Let's quantitatively evaluate the advantage of being able to transfer internal information to the outside without interrupt processing. Assume the following: Read out
The number of internal registers is 16 general-purpose registers and control register
Twenty-three. 16 general-purpose registers can be executed once
St for transferring the contents of a plurality of general-purpose registers to an external memory
ore Multiple instruction (hereinafter referred to as STM instruction)
Read), and the 23 control registers are read once.
To transfer the contents of one control register to external memory
Store from Control Space
Read by e command (hereinafter referred to as STC command)
It First, in the conventional example, the bus access count is 67 in total.
Times. On the other hand, the number of bus accesses required in the case of the present invention may be 39 times in total as follows. Note that the number of instruction fetches in the above-described conventional example is the minimum case, and may increase more than this. Even if the internal processing of the CPU is ignored in this way, there is such a difference, but considering the internal processing such as interrupt preprocessing, return processing, internal processing when each instruction is executed, etc. It is thought to spread. Further, in a CPU that executes pipeline processing, the pipeline is flushed during interrupt processing, so the difference in execution time further widens.

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (2)

[Claims] 1. A microprocessor is provided with a microprogram memory, the microprogram is described in the microprogram memory, and after executing an instruction of a specified address or an operand of an address, the microprocessor executes the microprocessor itself itself. A microprocessor comprising means for transferring internal information to the inside, and after completing the transfer to the outside, returning to an instruction sequence following the instruction at the address and continuing execution. 2. A microprocessor comprising a microprogram memory, a microprogram written in the microprogram memory, and an internal information output request terminal, wherein the microprocessor requests an output to the internal information output request terminal when executing an instruction. When the signal is received, after executing the above instruction, the microprogram continuously transfers the internal information of the microprocessor execution itself to the outside, and after the completion of the transfer to the outside, the microprocessor executes it before outputting the internal information. A microprocessor equipped with means for returning to the instruction sequence following the existing instruction and continuing execution.