JPH05189090A - Reset signal generating circuit - Google Patents

Abstract

PURPOSE:To provide the reset signal generating circuit which performs the stable reset operation with a simple constitution. CONSTITUTION:This reset signal generating circuit generates a reset signal to reset the operation of a microcomputer 7 at the time of reduction of a supply voltage. The supply voltage is divided by first and second voltage dividing resistors R1 and R2 to obtain a first voltage division signal, and a reference voltage Vre outputted from a reference voltage generating circuit 3 is divided by third and fourth resistors R5 and R6 to obtain a second voltage division signal, and voltages of first and second voltage division signals are compared with each other by a comparator 6a to detect the reduction of the supply voltage, thus generating the reset signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal generating circuit suitable for application to various electronic devices using a microcomputer as a control unit.

[0002]

2. Description of the Related Art Conventionally, in various electronic devices using a microcomputer as a control unit, a reset signal for resetting the operation is supplied to the microcomputer when the power is turned on so that the microcomputer always starts up in a constant state. ing. A block configuration of a circuit for generating such a reset signal when the power is turned on is shown in FIG. 2. In the figure, B indicates a battery (battery), and a DC low voltage signal of about 1.5 V supplied from the battery B is DC. /
The voltage is supplied to the DC converter 1 and boosted to a desired voltage. Then, the boosted signal is supplied as the power supply voltage V _DD from the power supply terminal 2 to each circuit (load) in the device as a drive power supply.

Further, the output of the battery B is compared with the reference voltage generation frequency.
Is supplied to the path 3 and has a constant potential reference voltage V_refGenerate
It In this case, the reference voltage generating circuit 3 is a Zener.
A diode or the like is used. And this reference voltage
Reference voltage V output from raw circuit 3 _refVoltage error amplifier circuit
Supply to 4. In this voltage error amplifier circuit 4,
Obtained feedback signal for setting power supply voltage and reference voltage V_refWith
The difference is amplified to form an error voltage, and this error voltage is set to DC / D.
The DC / DC converter 1 is supplied to the C converter 1
Power supply voltage V to output_DDControl.

Further, the power supply voltage V _DD output from the DC / DC converter 1 and the reference voltage V _ref output from the reference voltage generation circuit 3 are supplied to the reset pulse generation circuit 6.
The reset pulse generation circuit 6 is a circuit that outputs a reset pulse based on the result of comparing the power supply voltage _VDD and the reference voltage _Vref in a predetermined state, and supplies this reset pulse to the reset terminal of the microcomputer 7. .. The microcomputer 7 controls the operation of each part of the device, and resets the operating state of the microcomputer to the initial state when a reset pulse is supplied to the reset terminal. In this case, the reset pulse is always supplied to the microcomputer 7 when the power of this device is turned on.

Here, FIG. 3 shows a conventional configuration of the reset pulse generating circuit 6 for generating a reset pulse when the power is turned on and the surroundings thereof. FIG. 3 shows that the output of the battery B is DC / DC via the terminal 1a. It is supplied to the converter 1, when the power supply voltage V _DD from the DC / DC converter 1 is output, and supplies the power supply voltage V _DD to a series circuit of resistors R1, R2, both resistors R1, R2 The divided voltage signal is taken out from the connection midpoint of the resistors R1 and R2. Then, the voltage-divided signal is converted into a subtractor 4 which constitutes the voltage error amplifier circuit 4.
a, the subtractor 4a subtracts the divided voltage signal from the reference voltage V _ref output by the reference voltage generation circuit 3, and the subtraction output is supplied to the amplifier circuit 4b. Then, the signal amplified by the amplifier circuit 4b is supplied to the DC / DC converter 1 as an error signal.

Then, D is used to generate a reset pulse.
The power supply voltage V _DD output from the C / DC converter 1 is supplied to the series circuit of the resistors R3 and R4, and the signal divided by the resistors R3 and R4 is taken out from the connection midpoint of the resistors R3 and R4. Then, this divided voltage signal is supplied to the-side of the comparator 6a that constitutes the reset pulse generation circuit 6. Further, the reference voltage V _ref output by the reference voltage generation circuit 3 is compared with the comparator 6
Supply to the + side of a. Then, when the potential of the divided voltage signal of the power supply voltage V _DD by the resistors R3 and R4 becomes lower than the reference voltage V _ref by the comparison in the comparator 6a, a pulse to be inverted is output, and this pulse is output. The reset pulse is supplied to the microcomputer 7.

With such a configuration, before the power supply voltage V _DD rises to the specified potential when the power is turned on, the comparator 6a forming the reset pulse generating circuit 6 allows the voltage division signal of the power supply voltage V _DD to be generated. The reset pulse is output when it is detected that the potential of is lower than the reference voltage V _ref . Therefore, the reset pulse is always supplied to the microcomputer 7 when the power is turned on.
Will be activated after it is reset to the initial state.

[0008]

By the way, if a reset pulse is output while a device incorporating such a reset pulse generating circuit is in use, the operation of this device is interrupted. It is necessary to have a configuration in which the reset pulse is not output except when it is required. However, when the circuit facing the reset pulse generation circuit 6 is configured as described above, even when the power is not turned on, There is a possibility that a reset pulse may be output due to fluctuations in the power supply voltage or changes in the surrounding environment.

In order to prevent the careless output of the reset pulse, it is necessary to perform the voltage comparison in the reset pulse generating circuit 6 with high precision, but in order to perform the voltage comparison with high precision,
Since expensive and highly accurate parts have to be used or highly accurate adjustments have to be made after manufacturing, there has been the inconvenience of time and cost.

Here, the error with respect to power supply fluctuation in the circuit of FIG. 3 described above will be described using mathematical expressions. First, the power supply voltage V _DD is expressed by the following [Equation 1].

[0011]

[Equation 1]

If the power supply voltage when the reset operation is performed (hereinafter referred to as the reset operation setting voltage) is V _DD ′, this reset operation setting voltage V _DD ′ is expressed by the following equation (2). ..

[0013]

[Equation 2]

Then, the reset operation setting ratio is expressed by the following equation (3).

[0015]

[Equation 3]

Here, Rn = Rn (1 + Δn) (n:
1 to 4), the actual operation ratio is expressed by the following [Equation 4].

[0017]

[Equation 4]

In this equation (4), Δ1 =
If Δ4 = −0.05, Δ2 = Δ3 = + 0.05, and the power supply voltage fluctuates by 5%, the following equation (5) is obtained.

[0019]

[Equation 5]

On the other hand, the ratio between the power supply voltage V _DD and the reference voltage V _ref and the ratio between the power supply voltage V _DD and the reset operation setting voltage V _DD ′ are expressed by the following formulas (6) and (7). Set as shown.

[0021]

[Equation 6] V _DD : V _ref = 5: 2

[0022]

[Formula 7] V _DD ′ / V _DD = 0.9

By setting as shown in the equation (7), when the power supply voltage drops to 90% of the potential (that is, 10
%), The reset pulse is set to be output. Then, by setting in this way, the relationship between the resistors R1 and R2 is R1 = 1.50 ×
R2, and the relationship between the resistors R3 and R4 is R3 = 1.
It becomes 25 × R4. By substituting this condition into the formula [5], the reset operation setting ratio is expressed by the following formula [8].

[0024]

[Equation 8]

As the reset operation setting ratio becomes 0.986 as shown in the equation (8), 1-0.98
6 = 0.014, and a reset pulse will be output when there is a 0.014V _DD voltage drop, and I would like to have the reset pulse output when the power supply voltage drops by 10%. A setting error of 86% occurs in the operation setting ratio. If the power supply voltage fluctuates by 5% in this way and a setting error of 86% occurs in the reset operation setting ratio, the reset operation is more likely to be erroneously performed.

In view of the above point, the present invention has an object to provide a circuit of this kind which can perform a stable reset operation with a simple structure.

[0027]

According to the present invention, for example, as shown in FIG. 1, in a reset signal generation circuit for generating a reset signal for resetting the operation of the microcomputer 7 when the power supply voltage drops, the first power supply voltage is applied. And the second
The voltage dividing resistors R1 and R2 are used to obtain a first voltage dividing signal, and the reference voltage V _ref output by the reference voltage generating circuit 3 is _divided by the third and fourth voltage dividing resistors R5 and R6. A second voltage-divided signal is obtained, and a comparator 6a compares the first voltage-divided signal and the second voltage-divided signal to detect a decrease in the power supply voltage and generate a reset signal. Is.

[0028]

By doing so, the second voltage division signal based on the reference voltage V _ref determines the setting ratio of the reset operation, and the comparator 6a maintains a constant state even if the power supply voltage fluctuates. The voltage comparison can be carried out, and the reset signal can be stably output based on the voltage comparison.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIGS. 2 and 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this example, as shown in FIG.
The power supply voltage V _DD output from the / DC converter 1 is supplied to the series circuit of the resistors R1 and R2, and both resistors R1 and R2 are connected.
The signal divided by is taken out from the connection midpoint of the resistors R1 and R2. Then, this voltage division signal is supplied to the voltage error amplifier circuit 4
Is supplied to the subtractor 4a, which subtracts the divided voltage signal from the reference voltage V _ref output by the reference voltage generation circuit 3 and supplies the subtraction output to the amplifier circuit 4b. Then, the signal amplified by the amplifier circuit 4b is supplied to the DC / DC converter 1 as an error signal.

In this example, the resistors R1 and R2 are
The signal divided by is directly supplied to the-side of the comparator 6a.
Further, the reference voltage V _ref output by the reference voltage generation circuit 3 is supplied to the series circuit of the resistors R5 and R6, and both resistors R5 and R5 are supplied.
The signal divided by R6 is taken out from the connection midpoint of the resistors R5 and R6. Then, this divided voltage signal is supplied to the + side of the comparator 6a. And by this comparison with the comparator 6a,
When the potential of the divided voltage signal of the power supply voltage V _DD by the resistors R1 and R2 becomes lower than the potential of the divided signal of the reference voltage V _ref by the resistors R5 and R6, an inversion pulse is output. Is supplied to the microcomputer 7 as a reset pulse.

The other parts are configured similarly to the reset pulse generating circuit shown in FIG. 3 as a conventional example.

With this configuration, like the circuit shown in FIG. 3 as a conventional example, when the power is turned on, the power supply voltage V
Before the _DD rises to the specified potential, the potential of the divided voltage signal of the power supply voltage V _DD is lower than the potential of the divided voltage signal of the reference voltage V _{ref in} the comparator 6a that constitutes the reset pulse generation circuit 6. Is detected and a reset pulse is output.

Further, in this embodiment, with such a configuration, the reset operation (that is, the output of the reset pulse) can be stably performed even if the power supply voltage fluctuates or the power supply voltage is non-uniform. If this is explained using mathematical formulas,
First, the power supply voltage V _DD and the reset operation setting voltage V _DD ′ will be described. Regarding the power supply voltage V _DD , the conditions are the same as those of the circuit shown in FIG. Is applied. Further, the reset operation setting voltage V _DD ′ is expressed by the following equation (9).

[0035]

[Equation 9]

The reset operation setting ratio is expressed by the following equation (10).

[0037]

[Equation 10]

Here, Rn = Rn (1 + Δn) (n:
1 to 4), the actual operation ratio is
It is shown by the formula.

[0039]

[Equation 11]

Then, in this equation (11), Δ3
= -0.05, Δ4 = + 0.05, the power supply voltage is 5
If it fluctuates by%, it becomes as shown in the following [Equation 12].

[0041]

[Equation 12]

On the other hand, the ratio between the power supply voltage V _DD and the reference voltage V _ref and the ratio between the power supply voltage V _DD and the reset operation setting voltage V _DD ′ are determined by the following equation (6) and [Equation 7]
As shown in the equation, V _DD : V _ref = 5: 2, V _DD ′ / V _DD
= 0.9, the reset pulse is set to be output when the power supply voltage drops to 90% (that is, when it drops 10%). At this time, the relation between the resistors R5 and R6 is 10 × R5 = R6. This condition is [Equation 1
Substituting into equation 2), the reset operation setting ratio is
It is expressed by the following equation (13).

[0043]

[Equation 13]

Since the reset operation setting ratio is 0.917 as shown in the equation (13), the setting error is 17% as compared with the designed reset operation setting ratio 0.9. This 17% setting error is significantly improved as compared with the setting error 86% in the case of the circuit of FIG. 3 shown as a conventional example.

In this case, the setting error is improved only by changing the circuit configuration, and the accuracy itself of the comparator 6a and each resistor forming the reset pulse generating circuit 6 is calculated as the same as the conventional one. Therefore, it is not necessary to use highly accurate components. Further, the reset operation setting ratio, as shown in [Equation 10] wherein the reference voltage V _{re f}
It is determined only by a pair of voltage dividing resistors R5 and R6 that divide the voltage, and can be set with high accuracy, and adjustments during manufacturing are unnecessary. Further, even when the setting of the power supply voltage is changed, only the resistors R1 and R2 need to change the resistance value by changing the setting of the power supply voltage, and the reference voltage V _ref
Since the voltage dividing resistors R5 and R6 that divide the voltage are not affected,
There is no need to change the reset voltage.

In particular, when the circuit facing the reset pulse generating circuit 6 is formed of an integrated circuit and the power source setting terminal is provided to set the power source voltage by the external partial pressure resistor, the voltage dividing resistor R5 for reset pulse is used. R6 can be built into the integrated circuit with high accuracy, and the power supply setting terminal (corresponding to the connection midpoint of the resistors R1 and R2) can also be used as the voltage detection terminal for resetting, which is an external component. Can be reduced, the number of parts can be reduced, the manufacturing cost can be reduced, and the reliability can be improved.

[0047]

According to the present invention, even if the power supply voltage fluctuates, the voltage comparison between the power supply voltage side and the reference voltage side can be performed in a constant state in the reset signal generating circuit, and the reset signal based on the voltage comparison can be used. The output can be stable.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a reset pulse generating circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a power supply circuit to which an embodiment is applied.

FIG. 3 is a configuration diagram showing an example of a conventional reset pulse generation circuit.

[Explanation of symbols]

 1 DC / DC converter 2 power supply terminal 3 reference voltage generation circuit 4a subtractor 4b amplifier 6a comparator 7 microcomputer

Claims (1)

[Claims] 1. A reset signal generating circuit for generating a reset signal for resetting the operation of a microcomputer when a power supply voltage drops, wherein the power supply voltage is divided by a first and a second voltage dividing resistor.
Is obtained, and the reference voltage is divided by the third and fourth voltage dividing resistors to obtain a second voltage divided signal, and the first voltage divided signal and the second voltage divided signal A reset signal generation circuit configured to detect a decrease in power supply voltage by voltage comparison and generate the reset signal.